A cache request processing method, device and medium

Abstract

The present invention discloses a cache request processing method, device and medium, which belongs to the field of data processing technology, and is used to solve the technical problem that after the prior art reduces the cache line size, the system needs to process cache requests more frequently, which increases the complexity and overhead of cache management. The method includes: merging n block requests into a total request, wherein n is a positive integer; determining whether the target data block corresponding to any block request in the total request is cache hit; if the target data block cache hits, then obtaining the cache data corresponding to the target data block from the cache; if the target data block cache misses, then sending the miss request to the L2 cache, allocating target cache space for the target data block in the L1 cache, and obtaining the corresponding cache data from the target cache space. Through the above method, the present invention reduces the cache line size while reducing the frequency of processing cache requests, thereby reducing the complexity and overhead of cache management.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a cache request processing method, device and medium. Background Art

[0002] In the architectural design of modern general-purpose computing on GPUs (GPGPUs), cache plays a vital role as a core component for improving memory system efficiency and accelerating data processing and graphics rendering tasks. However, some inherent characteristics of GPGPU applications, especially their irregular memory access patterns and poor spatial locality, have brought unprecedented challenges to the effective use of cache. These characteristics make the distribution of data in the cache unpredictable and difficult to effectively use the cache space. At the same time, the massive multi-threaded nature of GPGPU further complicates the problem. Multiple threads running simultaneously will cause a lot of cache contention, making it difficult to fully utilize the powerful features of on-chip cache. As a result, a large amount of valuable cache space is not fully utilized, which not only wastes hardware resources, but also seriously affects the overall performance and efficiency of GPGPU.

[0003] In order to deal with this complex problem, researchers have been exploring various possible solutions. One widely studied method is to adjust the size of the cache line. Experimental data clearly shows that by using smaller cache lines, the utilization of cache space can be improved to a certain extent, allowing more data to be cached in the limited cache space. However, this method is not without cost. Due to the reduction of cache lines, the system needs to process cache requests more frequently, which increases the complexity and overhead of cache management, which may lead to significant performance losses. Summary of the invention

[0004] The present invention provides a cache request processing method, device and medium to solve the technical problem that after reducing the cache line size in the prior art, the system needs to process cache requests more frequently, which increases the complexity and overhead of cache management.

[0005] In a first aspect, the present invention provides a cache request processing method, comprising:

[0006] Merge n block requests into one total request, where n is a positive integer;

[0007] Determine whether a target data block corresponding to any block request in the total requests is cache hit;

[0008] If the target data block cache hits, obtaining cache data corresponding to the target data block from the cache;

[0009] If the target data block cache misses, a miss request is sent to the L2 cache, a target cache space is allocated for the target data block in the L1 cache, and corresponding cache data is obtained from the target cache space.

[0010] In a feasible implementation, n block requests are merged into one total request, including:

[0011] Combine 32 consecutive byte requests into one block request;

[0012] Combine the 4 chunk requests into one total request.

[0013] In a feasible implementation manner, the cache includes at least two cache groups, the cache group includes at least two cache lines, the cache line includes n cache data blocks, the size of the cache data block is the same as the size of the target data block, the cache data block includes a tag and a block offset, the block request includes a tag, a group index and an inter-block offset, and determining whether a target data block corresponding to any block request in the total request is cache hit includes:

[0014] Determining a target data block mask of a target data block corresponding to the block request based on the inter-block offset in the block request;

[0015] Based on the tag, group index and mask of the block request, a comparison is performed with the tag and block offset of the cached data block in the cache to determine whether the target data block is a cache hit.

[0016] In a feasible implementation manner, based on the tag, group index and mask of the block request, the tag and block offset of the cached data block in the cache are compared to determine whether the target data block is cache hit, including:

[0017] Determining a target data block mask of a target data block corresponding to the block request based on the inter-block offset in the block request;

[0018] Based on the group index in the block request, determining in the cache a first cache data block corresponding to the group index;

[0019] Based on the tag of the first cache data block, determining, in the first cache data block, a second cache data block that is consistent with the tag in the block request;

[0020] Determining a second cache data block mask of the second cache data block based on the block offset of the second cache data block;

[0021] Based on the second cache data block mask, determining whether there is a third cache data block consistent with the target data block mask in the second cache data block;

[0022] If so, it is determined that the target data block is cache hit, and the cache data block corresponding to the target data block is the third cache data block.

[0023] In a feasible implementation manner, the tag in the block request and the tag in the cache data block are both composed of a public tag and a private tag. There are at least two cache data blocks with the same public tag in the cache, and the at least two cache data blocks with the same public tag have different private tags. Based on the tag of the first cache data block, a second cache data block consistent with the tag in the block request is determined in the first cache data block, including:

[0024] Based on the public tag of the first cache data block, determining, in the first cache data block, a fourth cache data block that is consistent with the public tag in the block request;

[0025] Based on the private tag of the fourth cache data block, a second cache data block consistent with the private tag in the block request is determined in the fourth cache data block.

[0026] In a feasible implementation manner, the cache data block includes a valid bit, and if the target data block cache misses, a miss request is sent to the L2 cache, a target cache space is allocated for the target data block in the L1 cache, and corresponding cache data is obtained from the target cache space, including:

[0027] If the target data block cache misses, a miss request is sent to the L2 cache to determine whether there is a free cache data block in the L1 cache that matches the public tag of the target data block, and the value of the valid bit of the free cache data block is 0;

[0028] If so, the free cache data block is determined as the target cache space of the target data block, and the corresponding cache data is obtained from the target cache data block.

[0029] In a feasible implementation manner, the cache data block includes an NRU bit, the value of the NRU bit is 0 or 1, the value of the NRU bit is 1 indicating that the cache data block has a usage record within a first preset time, and the value of the NRU bit is 0 indicating that the cache data block has no usage record within the first preset time. After determining whether there is an idle cache data block matching the public tag of the target data block in the L1 cache, the method further includes:

[0030] If not, the cache data block with the NRU bit value of 0 is determined as the target cache space of the target data block, and the corresponding cache data is obtained from the target cache space.

[0031] In a feasible implementation manner, before determining whether a target data block corresponding to any one of the total requests is cache hit, the method further includes:

[0032] Recording the access timestamp of the target data block in the access record table of the target data block;

[0033] Determining whether the target data block is a hot data block based on an access record table of the target data block corresponding to the block request;

[0034] When the tags of at least two of the hot data blocks are the same, determining the at least two hot data blocks as hot associated data blocks;

[0035] When a cache hit occurs in the at least two hot associated data blocks, at least one of the at least two hot associated data blocks is moved so that the storage locations of the at least two hot associated data blocks in the cache are smaller than a preset distance threshold.

[0036] In a feasible implementation manner, determining whether the target data block is a hot data block based on an access record table of the target data block corresponding to the block request includes:

[0037] Calculating the access time difference between the current access timestamp of the target data block and the access timestamp of the most recent access;

[0038] Determining the number of accesses to the target data block within a second preset time based on the access record table of the target data block;

[0039] When the access time difference is smaller than a preset time difference threshold, and the access times is larger than a preset times threshold, the target data block is determined as a hot data block.

[0040] In a second aspect, the present invention provides a cache request processing device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor so that the at least one processor can execute a cache request processing method described in any of the above embodiments.

[0041] In a third aspect, the present invention provides a non-volatile computer storage medium, which is a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores at least one program, each of which includes instructions, and when the instructions are executed by a terminal, the terminal executes a cache request processing method described in any of the above embodiments.

[0042] Compared with the prior art, the cache request processing method, device and medium provided by the present invention have the following beneficial technical effects:

[0043] (1) The present invention combines multiple block requests into one total request, and when a cache miss occurs for the target data block corresponding to the block request, cache space is allocated for the target data block. In this way, by reducing the cache line size to the size of a target data block, the cache is fine-grained, unnecessary space occupation is avoided, and the adaptability of the cache space to different data volume requirements is improved, thereby improving the overall utilization rate, allowing more data to be effectively cached, reducing the probability of cache misses, and avoiding additional memory requests frequently initiated due to misses, thereby maintaining the number of memory requests relatively stable from the source. At the same time, by combining multiple block requests into one total request and processing the total request, the frequency of processing cache requests is reduced compared to processing each block request separately, and the complexity and overhead of cache management are reduced.

[0044] (2) The present invention splits the tag into two parts: a public tag and a private tag. Multiple data blocks with different private tags have the same public tag, which can effectively reduce storage overhead. In addition, by comparing the public tag and the private tag respectively, it is determined whether the tag of the cached data block is consistent with the tag in the block request, which can reduce the number of comparisons and reduce the access delay of the cache request.

[0045] (3) The present invention migrates the hot associated data blocks with the same tag that are frequently accessed recently in the cache to reduce the distance between the hot associated data blocks. The fine-grained characteristics of the cache can be utilized to reduce the fragmented space in the cache, ensuring that the cache layout can always be optimized based on the relevance and frequency of use of the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0047] Figure 1 A flow chart of a cache request processing method provided by the present invention;

[0048] Figure 2A schematic diagram of the structure of a cache provided by the present invention;

[0049] Figure 3 A schematic diagram of the structure of a byte request provided by the present invention;

[0050] Figure 4 A schematic diagram of the structure of a cache group provided by the present invention;

[0051] Figure 5 A schematic diagram of a cache access processing flow provided by the present invention;

[0052] Figure 6 A schematic diagram of the structure of a cache request processing device provided by the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0054] The technical solution proposed by the present invention is described in detail below with reference to the accompanying drawings.

[0055] Figure 1 The present invention provides a flow chart of a cache request processing method. Figure 1 As shown, the method includes the following execution steps:

[0056] S101. Merge n block requests into one total request.

[0057] Wherein, n is a positive integer.

[0058] In the present invention, a block request is a cache request for data of a target data block size, and merging multiple block requests into one total request can reduce the number of cache requests to be processed.

[0059] As a possible implementation, the size of the target data block corresponding to the block request can be 32 bytes, that is, S101 merges n block requests into a total request, including: merging 32 consecutive byte requests into one block request; merging 4 block requests into one total request, and the data size corresponding to the total request is 128 bytes.

[0060] In the present invention, a thread request corresponds to 4 bytes, which can also be understood as merging 32 thread requests into one total request.

[0061] It should be noted that, unlike the prior art in which cache requests need to merge 128 consecutive byte requests, the four target data blocks corresponding to the four block requests in the total request in the present invention can be continuous or discontinuous; that is, the merge operation only requires that the bytes corresponding to the 32 byte requests in the block request are continuous in the main memory address.

[0062] S102: Determine whether a target data block corresponding to any block request in the total requests is cache hit.

[0063] In this way, the present invention reduces the processing granularity for determining whether a cache hit occurs from 128 bytes in the prior art to the size of the target data block corresponding to the block request, thereby improving the cache hit rate.

[0064] For example, when the target data block size is 32 bytes, the processing granularity for determining whether a hit occurs is reduced to 32 bytes.

[0065] As a possible implementation, the cache includes at least two cache groups, the cache group includes at least two cache lines, the cache line includes n cache data blocks, the size of the cache data block is the same as the size of the target data block, the cache data block includes a tag and a block offset; the block request includes a tag, a group index and an inter-block offset.

[0066] S102 determines whether a target data block corresponding to any block request in the total requests is cache hit, including:

[0067] Based on the inter-block offset in the block request, determine the target data block mask of the target data block corresponding to the block request; based on the group index in the block request, determine the first cache data block corresponding to the group index in the cache; based on the tag of the first cache data block, determine the second cache data block consistent with the tag in the block request in the first cache data block; based on the block offset of the second cache data block, determine the second cache data block mask of the second cache data block; based on the second cache data block mask, determine whether there is a third cache data block consistent with the target data block mask in the second cache data block; if so, determine that the target data block cache hits, and the cache data block corresponding to the target data block is the third cache data block.

[0068] The corresponding relationship between the block offset of the second cache data block and the second cache data block mask is consistent with the corresponding relationship between the inter-block offset in the block request and the target data block mask.

[0069] For example, in the case of merging four block requests into one total request, the inter-block offset in the block request may include two bits, and the inter-block offsets are 00, 01, 10, and 11, and the corresponding target data block masks are 1000, 0100, 0010, and 0001, respectively.

[0070] That is, first determine in the cache the second cache data block whose group index and tag are consistent with those in the block request, and then compare the second cache data block mask with the target data block mask. If the comparison is consistent, it means that the target data block is in the cache, that is, a cache hit, and the corresponding cache data block is the third cache data block with a consistent mask comparison.

[0071] In order to reduce overhead, the present invention splits the tag into two parts: a public tag and a private tag. The memory area corresponding to the public tag is larger than the memory area corresponding to the private tag.

[0072] The tag in the block request and the tag in the cache data block are composed of a public tag and a private tag. There are at least two cache data blocks with the same public tag in the cache, and at least two cache data blocks with the same public tag have different private tags.

[0073] Based on the tag of the first cache data block, determining in the first cache data block a second cache data block that is consistent with the tag in the block request includes: based on the public tag of the first cache data block, determining in the first cache data block a fourth cache data block that is consistent with the public tag in the block request; based on the private tag of the fourth cache data block, determining in the fourth cache data block a second cache data block that is consistent with the private tag in the block request.

[0074] In this way, by comparing the public tag and the private tag respectively to determine whether the tag of the cached data block is consistent with the tag in the block request, the number of comparisons can be reduced and the access delay of the cache request can be reduced.

[0075] S103: If the target data block cache hits, the cache data corresponding to the target data block is obtained from the cache.

[0076] After acquiring cache data corresponding to the target data that hits the cache, if there are multiple target data blocks that hit the cache, the present invention combines these cache data to form a virtual cache line, which is then sent to the stream multiprocessor.

[0077] S104: If the target data block cache misses, a miss request is sent to the L2 cache, a target cache space is allocated for the target data block in the L1 cache, and corresponding cache data is obtained from the target cache space.

[0078] In the case of a target data block cache miss, the present invention only needs to allocate cache space to the target data block that has not been cached, thereby improving the processing efficiency of cache requests.

[0079] As a possible implementation, the cache data block includes a valid bit, which is used to manage cache space allocation. When the valid bit is 0, it indicates that the cache data block is invalid and can be reallocated, that is, it is a free cache data block; when the valid bit is 1, it indicates that the cache data block is a valid cache data block.

[0080] If the target data block cache misses, a miss request is sent to the L2 cache, a target cache space is allocated for the target data block in the L1 cache, and corresponding cache data is obtained from the target cache space, including: if the target data block cache misses, a miss request is sent to the L2 cache, and it is determined whether there is a free cache data block in the L1 cache that matches the public tag of the target data block, and the value of the valid bit of the free cache data block is 0; if so, the free cache data block is determined as the target cache space of the target data block, and the corresponding cache data is obtained from the target cache data block.

[0081] As a possible implementation method, the cache data block also includes a Not Recently Used (NRU) bit. The NRU bit is used as a cache replacement enable bit, and a Not Recently Used algorithm is used as a replacement strategy. If the target data cache is not hit and the number of free cache data blocks is insufficient, the positions of one or more valid cache data blocks need to be replaced. At this time, a valid cache data block with an NRU value of 0 is selected for replacement.

[0082] The value of the NRU bit is 0 or 1. The value of the NRU bit is 1, indicating that there is a usage record of the cache data block within the first preset time. The value of the NRU bit is 0, indicating that there is no usage record of the cache data block within the first preset time. After determining whether there is a free cache data block matching the public tag of the target data block in the L1 cache, the method also includes: if not, determining the cache data block with the NRU bit value of 0 as the target cache space of the target data block, and obtaining the corresponding cache data from the target cache space.

[0083] As a possible implementation manner, before determining whether a target data block corresponding to any one of the total requests is cache hit, the method further includes:

[0084] The method includes recording an access timestamp of the target data block in an access record table of the target data block; determining whether the target data block is a hot data block based on the access record table of the target data block corresponding to the block request; determining the at least two hot data blocks as hot-associated data blocks when the tags of at least two hot data blocks are the same; and moving at least one of the at least two hot-associated data blocks when a cache hit occurs in the at least two hot-associated data blocks so that the storage locations of the at least two hot-associated data blocks in the cache are less than a preset distance threshold.

[0085] Among them, the hot data blocks are data blocks that are frequently accessed recently.

[0086] By performing the above movement of hot associated data blocks, the fine-grained characteristics of the cache can be fully utilized and the fragmentation space in the cache can be reduced.

[0087] As a possible implementation method, determining whether the target data block is a hot data block based on an access record table of the target data block corresponding to the block request includes: calculating an access time difference between a current access timestamp of the target data block and an access timestamp of a most recent access; determining the number of accesses to the target data block within a second preset time based on the access record table of the target data block; and determining the target data block as a hot data block when the access time difference is less than a preset time difference threshold and the number of accesses is greater than a preset number threshold.

[0088] The present invention proposes an innovative tag-split fine-grained cache design. The cache of the present invention is based on a 128-byte cache line size as a coarse-grained access unit, which is then split into four data blocks (blocks) of 32 bytes each, that is, a cache line is a block group including 4 blocks, thereby achieving fine-grained cache. By splitting the 128-byte cache line into smaller blocks, the cache can store and manage data more accurately. For those situations where only part of the data is needed (less than a complete cache line size), the traditional cache will call in the entire cache line, causing the rest of the space to be idle and wasted. This fine-grained design can store the corresponding blocks on demand, avoiding unnecessary space occupation, and improving the adaptability of the cache space to different data volume requirements, thereby improving overall utilization.

[0089] Traditional caches may often have cache misses due to problems such as low space utilization. Once a cache miss occurs, a new memory request needs to be initiated to a higher-level cache (such as L2 cache) or main memory to obtain data. The present invention improves cache space utilization, allowing more data to be effectively cached, reducing the probability of cache misses, thus avoiding additional memory requests frequently initiated due to misses, and maintaining the number of memory requests relatively stable from the root.

[0090] Exemplarily, the cache is constructed using random access memory (RAM) resources inside a Field-Programmable Gate Array (FPGA). Figure 2 A schematic diagram of a cache structure provided by the present invention, such as Figure 2 As shown, the FPGA RAM used as a cache is divided into 32 cache groups, namely cache group No. 0 ... cache group No. 31, and adopts a 4-way group associative data storage method, that is, the cache includes 4-way cache space, one cache space includes 32 cache lines, cache group No. 0 includes cache line No. 0 in cache line No. 0, cache line No. 0 of cache line No. 1, cache line No. 0 of cache line No. 2 and cache line No. 0 of cache line No. 3, ..., cache group No. 31 includes cache line No. 31 of cache line No. 0, cache line No. 31 of cache line No. 1, cache line No. 31 of cache line No. 2 and cache line No. 31 of cache line No. 3, wherein each cache line includes 4 blocks, which greatly improves the cache hit rate and optimizes the cache space utilization.

[0091] Different from the traditional cache structure, this design does not assign a separate tag to each block. If a separate tag is assigned to each block, it will generate a large storage overhead, and more tag comparisons during cache access will also increase cache access latency. In order to reduce overhead, the present invention splits the traditional tag segment in the cache request into two parts: a high-order public tag and a low-order private tag. The public tag is used to identify a relatively large memory area. Blocks with the same public tag can be mapped to different cache lines, and the private tag can allow blocks with discontinuous memory addresses to be combined and stored in the same cache line, which further improves cache space utilization.

[0092] The present invention proposes a data classification and layout adjustment strategy, which maintains a historical access record table inside the FPGA to record the access timestamp and access frequency of each data block. At each request, the record table is queried according to the current request address to calculate the continuity of the address and the change in access frequency. If the data addresses requested by multiple threads are in a continuous or similar memory area, and the area has been frequently accessed recently, it is marked as a "hot associated data request"; if the requested data addresses are scattered and the corresponding data block has a low access frequency before, it is marked as a "cold independent data request". For the hot associated data corresponding to the hot associated data request, a compact layout method is adopted in the cache to place them in adjacent blocks as much as possible to make full use of the fine-grained characteristics of the cache and reduce the fragmented space in the cache line. For the cold independent data corresponding to the cold independent data request, a more sparse layout can be adopted so that it can be replaced and reallocated more flexibly when needed.

[0093] Figure 3 A schematic diagram of a byte request structure provided by the present invention, such as Figure 3 As shown in the figure, a byte request corresponds to a byte address, which consists of 5 parts, namely a public tag with a width of 12 bits and a private tag with a width of 8 bits; a 5-bit wide group index field, the group index is the group selection in the cache parallel group associative structure, that is, it indicates one of the 32 cache groups; a 5-bit wide block offset field, the block offset indicates the selection of a single byte data in a 32-byte block; a 2-bit wide inter-block offset field, the inter-block offset refers to the selection of a single block in a 128-byte cache line (including a block group of 4 blocks); the byte request is 32 bits in total.

[0094] This example includes 32 cache groups with the same structure. Figure 4 A schematic diagram of the structure of a cache group provided by the present invention, such as Figure 4 As shown in the figure, each cache group contains 4 block groups, each block group is 128 bytes in size, and each block group consists of 4 32-byte blocks; and all blocks in the same block group have the same public tag. In this way, a block group can flexibly split and reassemble 32-byte blocks read from different memory addresses and belonging to multiple 128-byte cache lines for storage.

[0095] Each block includes attributes such as public tag, private tag, block offset, valid bit, and NRU.

[0096] The block offset is used to indicate the position of the block in the block group.

[0097] The valid bit is used to manage cache space allocation. When the valid bit is 0, it means that the block is invalid and can be reallocated; when the valid bit is 1, it means that the block is a valid block.

[0098] In addition, the NRU field is used as the cache replacement enable bit, and the not recently used algorithm is used as the replacement strategy. If the block cache misses and the number of invalid blocks is insufficient, one or more valid blocks need to be replaced. In this case, the block with an NRU value of 0 is selected for replacement.

[0099] Figure 5 A schematic diagram of a cache access processing flow provided by the present invention, such as Figure 5 As shown, the cache access processing flow includes the following steps.

[0100] (1) When executing load / store instructions, the streaming multiprocessor will merge the requests of all threads in the wrap according to the cache line access granularity of 128 bytes. The streaming multiprocessor will query the record table for the current request address and calculate the changes in address continuity and access frequency. At the same time, the streaming multiprocessor will also calculate which block of the 128-byte data in the cache line to be accessed is the target data block corresponding to each block request in the merged cache request (total request). When generating a 4-bit access block mask (target data block mask) for each block to be accessed, the corresponding data category (hot associated data block or cold independent data block) is marked for each block.

[0101] The stream multiprocessor passes the merged cache request, access block mask, and data category information of each block to the tag split fine-grained cache system.

[0102] (2) After receiving a request, the tag-splitting fine-grained cache system finds the corresponding local cache group, that is, the cache group in the cache, based on the group index information in the request.

[0103] The public tag and private tag of the block request are compared with the public tag and private tag corresponding to the cached data block in parallel: for each of the four block groups in a cache group, the public tag of each block group is compared with the public tag in the block request; for each block in the block group, the private tag is compared at the same time.

[0104] During the comparison process, when it is determined that both the public tag and the private tag of a block in the cache match the tag of the current block request, the block offset of the block in the cache line is recorded, and the block mask of the block is determined based on the block offset of the block in the cache line.

[0105] The mapping relationship between the block offset and the block mask of a block is: block offset 00 is mapped to block mask 0001, block offset 01 is mapped to block mask 0010, block offset 10 is mapped to block mask 0100, and block offset 11 is mapped to block mask 1000. After completing the above mask calculation, the original data category of each block (hot associated data block or cold independent data block) is retained at the same time.

[0106] (3) Then, the block mask calculated in step (2) is compared with the access block mask transmitted along with the merged cache request to determine the access status corresponding to the merged cache request. Possible access statuses include: full hit, full miss, and partial hit.

[0107] Specifically, when the public tag, private tag, group index, and access block mask corresponding to the block request are consistent with the block mask and the corresponding public tag, private tag, and group index calculated in step (2), it is determined that the target data block corresponding to the block request is hit.

[0108] (4) If the block required by the block request is already stored in the cache line, the block request hits the tag split fine-grained cache storage. At this time, the data category of the hit block is checked. For hot associated data blocks, they are preferentially moved to the storage area connected to multiple hot associated blocks in the cache. After the block migration operation is completed, the required block data is read from the data cache memory RAM, and the tag split fine-grained cache combines these data to form a virtual cache line, which is then sent to the stream multiprocessor. For cold independent data blocks, if their location does not affect the flexible use of cache space, they can remain in place.

[0109] (5) If the block required by the block request is not found in the cache, a cache miss occurs.

[0110] At this time, the tag split fine-grained cache will allocate a new or use an existing MSHR entry to record this miss, and send the miss request to the L2 cache in sequence. At the same time, cache space is allocated for the missed block, and invalid blocks with the same data category as the missed data block are preferentially selected for replacement. If the number of invalid blocks of the corresponding category is insufficient, then according to the recently unused replacement strategy, blocks with an NRU value of 0 are selected across data categories for replacement.

[0111] (6) When some of the required blocks corresponding to the merged cache request are not in the cache, the cached blocks are considered cache hits and the uncached blocks are considered cache misses. The tag split fine-grained cache system requests the L2 cache to provide uncached blocks on the one hand, and reads the block data required by the cache hit block request from the data cache memory RAM on the other hand. During the processing, the cached and uncached blocks are also operated according to the above-mentioned processing methods for different data categories when hitting and missing, ensuring that the cache layout can always be optimized according to the relevance and frequency of use of the data.

[0112] Corresponding to the above embodiment, the present invention also provides a cache request processing device. Figure 6 A structural diagram of a cache request processing device provided for an embodiment of the present invention, the device may include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, so that the at least one processor can execute a cache request processing method as described in the above embodiment.

[0113] In a possible implementation of the present invention, the aforementioned at least one processor is capable of executing: merging n block requests into a total request, where n is a positive integer; determining whether a target data block corresponding to any block request in the total request is cache hit; if the target data block cache hits, obtaining cache data corresponding to the target data block from the cache; if the target data block cache misses, sending the miss request to the L2 cache, allocating target cache space for the target data block in the L1 cache, and obtaining corresponding cache data from the target cache space.

[0114] In a specific implementation, the present invention can also be provided as a non-volatile computer storage medium, wherein the storage medium is a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores at least one program, each program includes instructions, and when the instructions are executed by the terminal, the terminal executes a cache request processing method as described in the above embodiment.

[0115] In a possible implementation of the present invention, the aforementioned terminal executes, merging n block requests into a total request, where n is a positive integer; determining whether a target data block corresponding to any block request in the total request is cache hit; if the target data block cache hits, obtaining cache data corresponding to the target data block from the cache; if the target data block cache misses, sending the miss request to the L2 cache, allocating target cache space for the target data block in the L1 cache, and obtaining corresponding cache data from the target cache space.

[0116] The various embodiments of the present invention are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0117] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0118] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A cache request processing method, characterized in that: The method comprises: Merge n block requests into one total request, where n is a positive integer; Determine whether a target data block corresponding to any block request in the total requests is cache hit; If the target data block cache hits, then obtaining cache data corresponding to the target data block from the cache; If the target data block cache misses, a miss request is sent to the L2 cache, a target cache space is allocated for the target data block in the L1 cache, and corresponding cache data is obtained from the target cache space; The cache includes at least two cache groups, the cache group includes at least two cache lines, the cache line includes n cache data blocks, the size of the cache data block is the same as the size of the target data block, the cache data block includes a tag and a block offset, the block request includes a tag, a group index and an inter-block offset, and determining whether a target data block corresponding to any block request in the total request is cache hit includes: Determining a target data block mask of a target data block corresponding to the block request based on an inter-block offset in the block request; Based on the group index in the block request, determining in the cache a first cache data block corresponding to the group index; Based on the tag of the first cache data block, determining, in the first cache data block, a second cache data block that is consistent with the tag in the block request; Determining a second cache data block mask of the second cache data block based on the block offset of the second cache data block; Based on the second cache data block mask, determining whether there is a third cache data block consistent with the target data block mask in the second cache data block; If so, it is determined that the target data block is cache hit, and the cache data block corresponding to the target data block is the third cache data block.

2. A cache request processing method according to claim 1, characterized in that: Combine n chunk requests into one total request consisting of: Combine 32 consecutive byte requests into one block request; Combine the 4 chunk requests into one total request.

3. A cache request processing method according to claim 1, characterized in that: The tag in the block request and the tag in the cache data block both consist of a public tag and a private tag. There are at least two cache data blocks with the same public tag in the cache. The at least two cache data blocks with the same public tag have different private tags. Based on the tag of the first cache data block, a second cache data block consistent with the tag in the block request is determined in the first cache data block, including: Based on the public tag of the first cache data block, determining, in the first cache data block, a fourth cache data block that is consistent with the public tag in the block request; Based on the private tag of the fourth cache data block, a second cache data block consistent with the private tag in the block request is determined in the fourth cache data block.

4. A cache request processing method according to claim 3, characterized in that: The cache data block includes a valid bit. If the target data block cache misses, a miss request is sent to the L2 cache, a target cache space is allocated for the target data block in the L1 cache, and corresponding cache data is obtained from the target cache space, including: If the target data block cache misses, a miss request is sent to the L2 cache to determine whether there is a free cache data block in the L1 cache that matches the public tag of the target data block, and the value of the valid bit of the free cache data block is 0; If so, the free cache data block is determined as the target cache space of the target data block, and the corresponding cache data is obtained from the target cache data block.

5. A cache request processing method according to claim 4, characterized in that: The cache data block includes an NRU bit, the value of the NRU bit is 0 or 1, the value of the NRU bit is 1 indicating that the cache data block has a usage record within a first preset time, and the value of the NRU bit is 0 indicating that the cache data block has no usage record within the first preset time. After determining whether there is an idle cache data block matching the public tag of the target data block in the L1 cache, the method further includes: If not, the cache data block with the NRU bit value of 0 is determined as the target cache space of the target data block, and the corresponding cache data is obtained from the target cache space.

6. A cache request processing method according to claim 1, characterized in that: Before determining whether a target data block corresponding to any one of the total requests is cache hit, the method further includes: Recording the access timestamp of the target data block in the access record table of the target data block; Determining whether the target data block is a hot data block based on an access record table of the target data block corresponding to the block request; When the tags of at least two of the hot data blocks are the same, determining the at least two hot data blocks as hot associated data blocks; When a cache hit occurs in the at least two hot associated data blocks, at least one of the at least two hot associated data blocks is moved so that the storage locations of the at least two hot associated data blocks in the cache are smaller than a preset distance threshold.

7. A cache request processing method according to claim 6, characterized in that: Determining whether the target data block is a hot data block based on an access record table of the target data block corresponding to the block request includes: Calculating the access time difference between the current access timestamp of the target data block and the access timestamp of the most recent access; Determining the number of accesses to the target data block within a second preset time based on the access record table of the target data block; When the access time difference is smaller than a preset time difference threshold, and the access times is larger than a preset times threshold, the target data block is determined as a hot data block.

8. A cache request processing device, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, so that the at least one processor can execute a cache request processing method according to any one of claims 1-7.

9. A non-volatile computer storage medium, characterized in that: The storage medium is a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores at least one program, each of which includes instructions, and when the instructions are executed by the terminal, the terminal executes a cache request processing method according to any one of claims 1-7.

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