Data synchronization method, device and system for processor

Abstract

The invention provides a data synchronization method and device for a processor, a processor system, a server, a computer readable storage medium and a computer program product. The data synchronization method for a first processor relates to the first processor and one or more second processors which are connected with each other through a bus. The method comprises the following steps: acquiring data to be synchronized; storing the data in a register of the first processor; and in response to the register receiving the broadcast trigger command, sending a broadcast message including data to the one or more second processors via the bus, so that the one or more second processors acquire the data included in the broadcast message in response to a notification message for the broadcast message when receiving the broadcast message.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and more particularly, to a data synchronization method and device for a processor, a processor system, and a server. Background Art

[0002] The server is the core device in the computer network, responsible for managing and storing devices, controlling network resources, executing network services, etc. For multi-way servers, a server motherboard can accommodate two, four or even more central processing units (CPUs). Generally speaking, each CPU can be configured with one or more management units, which are responsible for managing and controlling the CPU's operations, data, input and output, etc. For example, the CPU's management unit can be implemented using a microcontroller unit (MCU).

[0003] In some cases, the management units of different CPUs on the server motherboard may need to synchronize data in order to better serve the entire server platform. In existing methods, data synchronization is usually performed one-to-one between CPUs, which is inefficient, has a high interaction frequency, a slow synchronization speed, and cannot synchronize data in batches, which cannot meet the needs of real-time data synchronization. Therefore, an efficient data synchronization method for processors is needed. Summary of the invention

[0004] In order to solve the above problems, the present disclosure proposes a data synchronization method and device for a processor, a processor system, a server, a computer-readable storage medium, and a computer program product.

[0005] According to one aspect of an embodiment of the present disclosure, a data synchronization method for a first processor is provided, wherein the first processor is interconnected with one or more second processors via a bus, the method comprising: acquiring data to be synchronized; storing the data in a register of the first processor; and in response to the register receiving a broadcast trigger command, sending a broadcast message including the data to the one or more second processors via the bus, so that when the one or more second processors receive the broadcast message, they acquire the data included in the broadcast message in response to a notification message for the broadcast message.

[0006] According to an example of an embodiment of the present disclosure, the data includes status data indicating an operating status of the first processor.

[0007] According to an example of an embodiment of the present disclosure, the register includes a data send bit, and storing the data in the register of the first processor includes: storing the data in the data send bit of the register for the first processor.

[0008] According to an example of an embodiment of the present disclosure, the register further includes a broadcast message trigger bit, and the broadcast trigger command is used to set the broadcast message trigger bit of the register so that the register outputs the data stored in the data sending bit.

[0009] According to an example of an embodiment of the present disclosure, sending a broadcast message including the data to the one or more second processors via the bus includes: using a Management Component Transport Protocol (MCTP) to send a broadcast message including the data to the one or more second processors via the bus.

[0010] According to an example of an embodiment of the present disclosure, the bus is a bus based on the Peripheral Component Interconnect Express (PCIe) standard.

[0011] According to an example of an embodiment of the present disclosure, the broadcast message also includes one or more of a type field for identifying the message type, a tag field for identifying the purpose of the message, an originator ID field for identifying the identity (ID) of the message originator, a vendor ID field for identifying the processor vendor ID, and a target ID field for identifying the destination of the message.

[0012] According to an example of an embodiment of the present disclosure, the notification message is sent in the form of an interrupt.

[0013] According to another aspect of an embodiment of the present disclosure, a data synchronization method for a second processor is provided, wherein the second processor is interconnected with one or more first processors via a bus, and the method comprises: receiving a message from the one or more first processors via the bus, and storing the message in a register of the second processor; parsing the message to determine the type and purpose of the message; generating a notification message based on determining that the message is a broadcast message for data synchronization; and obtaining, in response to the notification message, from the register the synchronization data from the one or more first processors included in the broadcast message.

[0014] According to an example of an embodiment of the present disclosure, the synchronization data includes status data indicating an operating status of the one or more first processors.

[0015] According to an example of an embodiment of the present disclosure, the register includes a data reception bit, and wherein storing the message in the register of the second processor includes: storing the message in the data reception bit of the register of the second processor.

[0016] According to an example of an embodiment of the present disclosure, obtaining the synchronization data from the one or more first processors included in the broadcast message from the register includes: obtaining the synchronization data included in the broadcast message by traversing the data receiving bits of the register.

[0017] According to an example of an embodiment of the present disclosure, the notification message is sent in the form of an interrupt.

[0018] According to an example of an embodiment of the present disclosure, the message includes one or more of a type field for identifying a message type, a tag field for identifying a message purpose, an initiator ID field for identifying an identity (ID) of a message initiator, a vendor ID field for identifying a processor vendor ID, and a target ID field for identifying a message destination.

[0019] According to an example of an embodiment of the present disclosure, parsing the message to determine the type and purpose of the message includes: reading the type field in the message to determine whether the message is a broadcast message; and reading the tag field in the message to determine whether the message is used for data synchronization.

[0020] According to an example of an embodiment of the present disclosure, the message is sent via a Management Component Transport Protocol (MCTP).

[0021] According to an example of an embodiment of the present disclosure, the bus is a bus based on the Peripheral Component Interconnect Express (PCIe) standard.

[0022] According to another aspect of an embodiment of the present disclosure, a data synchronization method for multiple processors is provided, wherein the multiple processors include a first processor and one or more second processors interconnected via a bus, and the method includes: the first processor obtains data to be synchronized and stores the data in a register of the first processor; in response to the register of the first processor receiving a broadcast trigger command, the first processor sends a broadcast message including the data to the one or more second processors via the bus; after receiving the broadcast message via the bus, the one or more second processors store the broadcast message in the registers of the one or more second processors; the one or more second processors parse the received broadcast message to determine its type and purpose, and generate a notification message based on determining that the received broadcast message is a broadcast message for data synchronization; and in response to the notification message, the one or more second processors obtain the data from the first processor included in the broadcast message from the registers of the one or more second processors.

[0023] According to an example of an embodiment of the present disclosure, the broadcast message adopts Management Component Transport Protocol (MCTP).

[0024] According to an example of an embodiment of the present disclosure, the notification message is sent to the management module of the one or more second processors in the form of an interrupt.

[0025] According to another aspect of an embodiment of the present disclosure, a data synchronization device for a first processor is provided, wherein the first processor is interconnected with one or more second processors via a bus, and the device comprises: a management module configured to obtain data to be synchronized; a transmission control module comprising a register, the transmission control module being configured to receive the data from the management module and store the data in the register; and a communication module configured to send a broadcast message including the data to the one or more second processors via the bus in response to the register receiving a broadcast trigger command, so that the one or more second processors, when receiving the broadcast message, obtain the data included in the broadcast message in response to a notification message for the broadcast message.

[0026] According to another aspect of an embodiment of the present disclosure, a data synchronization device for a second processor is provided, wherein the second processor is interconnected with one or more first processors via a bus, and the device comprises: a communication module, configured to receive a message from the one or more first processors via the bus, parse the message to determine the type and purpose of the message, and generate a notification message based on determining that the message is a broadcast message for data synchronization; a transmission control module, comprising a register, the transmission control module being configured to receive the message from the communication module and store the message in the register; and a management module, configured to receive the notification message and, in response to the notification message, obtain the synchronization data from the one or more first processors included in the broadcast message from the register of the transmission control module.

[0027] According to another aspect of an embodiment of the present disclosure, a processor system is provided, comprising a plurality of processors interconnected via a bus, each of the plurality of processors being configured with a data synchronization device, the data synchronization device being configured to execute the methods described in the above aspects.

[0028] According to another aspect of an embodiment of the present disclosure, a server is provided, comprising the processor system as described in the above aspect.

[0029] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the processor executes the methods described in the above aspects.

[0030] According to another aspect of an embodiment of the present disclosure, a computer program product is provided, which includes computer-readable instructions. When the computer-readable instructions are executed by a processor, the processor executes the methods described in the above aspects.

[0031] By utilizing the data synchronization method and apparatus for processors, processor systems, servers, computer-readable storage media, and computer program products according to various aspects of the embodiments of the present disclosure, one-to-many, many-to-one, and even many-to-many batch data synchronization can be quickly and efficiently completed between multiple processors in the form of broadcast transmission, which greatly improves the data synchronization efficiency compared to the traditional one-to-one data synchronization method; in addition, data synchronization is completed by broadcasting on a bus based on a high-speed serial standard, which greatly improves the synchronization transmission speed compared to traditional data synchronization through a low-speed serial bus, and reduces the interaction time between processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other purposes, features and advantages of the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0033] Figure 1 An example of multiple processors according to an embodiment of the present disclosure is shown.

[0034] Figure 2 A flow chart of a data synchronization method for a first processor according to an embodiment of the present disclosure is shown.

[0035] Figure 3 An example of a data format of a broadcast message according to an embodiment of the present disclosure is shown.

[0036] Figure 4 A flow chart of a data synchronization method for a second processor according to an embodiment of the present disclosure is shown.

[0037] Figure 5 A schematic structural diagram of a data synchronization device for a first processor according to an embodiment of the present disclosure is shown.

[0038] Figure 6A schematic structural diagram of a data synchronization device for a second processor according to an embodiment of the present disclosure is shown.

[0039] Figure 7 An example of a processor system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] As used in the embodiments of the present disclosure, unless the context clearly indicates an exception, the words "a", "an", "a kind of" and / or "the" do not specifically refer to the singular, but may also include the plural. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0042] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0043] In addition, flow charts are used in the present disclosure to illustrate the operations performed by the system according to the embodiments of the present disclosure. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be superimposed on these processes, or one or more operations may be removed from these processes.

[0044] In a multi-way server product, a server motherboard can accommodate two, four or even more central processing units (CPUs), and the management units of these CPUs may need to synchronize data in order to better serve the entire server platform. In existing methods, data synchronization is usually performed one-to-one between CPUs. For example, a data synchronization request can be initiated by the management unit of a certain CPU, and the data can be synchronized to the management units of other CPUs in turn; or a management unit of a certain CPU can be designated to receive data from other CPUs to complete data synchronization. This one-to-one data synchronization method is inefficient, the interaction frequency is too high, and it is inconvenient to use. In addition, the existing data synchronization method usually relies on a low-speed serial port bus, the data transmission rate is low, and the amount of data synchronized at a single time is small, and data cannot be synchronized in batches. The above defects make the existing data synchronization method unable to meet the needs of real-time data synchronization between CPUs.

[0045] The data synchronization method and device for processors proposed in the present disclosure can quickly and efficiently complete one-to-many, many-to-one or even many-to-many batch data synchronization between multiple processors by broadcasting, which greatly improves the data synchronization efficiency compared to the traditional one-to-one data synchronization method.

[0046] The following will describe a data synchronization method and apparatus according to one or more embodiments of the present disclosure with reference to the accompanying drawings, wherein a plurality of processors are involved. These processors may be located on a server motherboard, or in a computing network, and may be connected to each other via a bus, such as Figure 1 shown. Figure 1 An example of a plurality of processors according to an embodiment of the present disclosure is shown, wherein a plurality of processors 102 and a bus 104 connecting the plurality of processors are shown by way of example and not limitation. Each of the plurality of processors 102 may, for example, refer to a central processing unit (CPU), a microcontroller unit (MCU), or any other structure or module having a processing function, and the embodiment of the present disclosure does not impose specific restrictions on this. In some cases, data synchronization is required between the plurality of processors 102, for example, it may be necessary to synchronize the operating status data of different processors to better coordinate the processing of each processor to serve the overall operation of the server or computing network.

[0047] In the following, the first processor and the second processor are mentioned. It should be noted that the first processor and the second processor are only for the purpose of convenience of description and are not intended to be limited to processors of a specific type or function. The first processor and the second processor may be as follows: Figure 1 Any of the processors 102 shown, and the first processor and the second processor may be interchanged.

[0048] Figure 2FIG. 2 is a flow chart of a data synchronization method 200 for a first processor according to an embodiment of the present disclosure. As described above, the method 200 involves a first processor and one or more second processors connected to each other via a bus. The first processor and the one or more second processors may be as follows: Figure 1 Any of the plurality of processors 102 shown.

[0049] Method 200 describes a data synchronization operation for a first processor, wherein the first processor can synchronize its data to one or more second processors. In step S202, data to be synchronized is obtained, and the data can be status data indicating the operating status of the first processor, for example, data indicating the program version currently running on the first processor, operating temperature, operating frequency, operating voltage, power consumption, operating current, static information, etc., and the embodiments of the present disclosure do not impose specific restrictions on this. According to an example of an embodiment of the present disclosure, the first processor can include or be connected to system software such as a management module, and the management module can obtain and store data about the first processor through a hardware sensor, for example.

[0050] In step S204, the data to be synchronized is stored in a register for the first processor. According to an example of an embodiment of the present disclosure, the register for the first processor may include a data transmission bit, a data reception bit, and a broadcast message trigger bit, wherein the data transmission bit is used to store the data content to be sent (e.g., sent by broadcast), the data reception bit is used to store the received data content, and the broadcast message trigger bit can be used to complete the sending of the broadcast message when it is set. Among them, each of the data transmission bit, the data reception bit, and the broadcast message trigger bit can be composed of one or more register units of different bit lengths, for example. When the first processor needs to perform data synchronization, the data to be synchronized can be stored in the data transmission bit of its register to wait for sending.

[0051] In step S206, in response to the register receiving the broadcast trigger command, a broadcast message including the data to be synchronized may be sent to one or more second processors via the bus. The broadcast trigger command may be issued, for example, by a management module or other software module for the first processor, and the broadcast trigger command is used to set the broadcast message trigger bit of the register so that the register outputs the data stored in its data transmission bit for broadcast transmission. For example, the broadcast trigger command may be completed by simply setting the broadcast message trigger bit of the register from "0" to "1", but this is only an example and not a limitation.

[0052] In an example of an embodiment of the present disclosure, a management component transport protocol (MCTP) may be used to send a broadcast message including data to be synchronized to one or more second processors via a bus, but the embodiment of the present disclosure is not limited thereto, and other suitable data transmission protocols may also be used. MCTP is a data link layer protocol that defines a data format for communication on various buses, such as a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB), a system management bus (SMBus), and the like. In this example, the broadcast message including data to be synchronized may be packaged into an MCTP format, such as Figure 3 shown. Figure 3 An example of the data format of a broadcast message according to an embodiment of the present disclosure is shown, wherein the broadcast message may include a data header 302 and data content 304, the data content 304 may include data to be synchronized about the first processor, and the data header 302 may include, for example, a type field for identifying the message type, a tag field for identifying the purpose of the message, an initiator ID field for identifying the identity (ID) of the message initiator, a vendor ID field for identifying the processor vendor ID, a target ID field for identifying the destination of the message, and one or more of the like. Figure 3 Some fields that may be included in the data header of a broadcast message are exemplarily shown in FIG. 1 , but this is merely an example and not a limitation. More or fewer fields may be included in the data header according to design requirements.

[0053] Reference Figure 3 , the type field of the broadcast message can be set to indicate a broadcast message; the tag field can be set to indicate a specific data format, such as a custom data format for inter-processor data synchronization, specifically, for example, the MCTP format. In addition, the initiator ID field of the broadcast message can be set to the processor node ID that sends the broadcast message, but the target address of the data, that is, the target ID field, does not need to be set, and the broadcast message can be automatically broadcast to all processors connected to the bus.

[0054] As discussed above, existing data synchronization methods usually use a low-speed serial bus for one-to-one data synchronization, resulting in low data synchronization efficiency. In the embodiments of the present disclosure, multiple processors are interconnected through a bus, which can be, for example, a bus based on the Peripheral Component Interconnect Express (PCIe) standard or other high-speed serial standards, and the embodiments of the present disclosure do not impose specific restrictions on this. PCIe is a high-speed serial computer expansion bus standard that can use a point-to-point, full-duplex method for differential signal transmission, and has the advantages of high speed, low latency, and flexibility. At present, the fifth-generation PCI high-speed standard PCIe 5.0 further improves the data transmission speed, providing strong support for high-performance computing, big data processing and storage, etc.

[0055] In view of the fact that multiple processors are connected to each other through a bus, when data synchronization is performed between processors, one-to-many data synchronization can be achieved by sending a broadcast message on the bus. Specifically, for example, in step S206 of method 200, in response to the register receiving a broadcast trigger command, a broadcast message including data of the first processor can be packaged into an MCTP format and broadcasted on the bus. For example, the broadcast message can be broadcasted on a bus based on the PCIe standard without interfering with an ordinary PCIe link.

[0056] On the other hand, one or more second processors connected to the bus can receive the broadcast message and obtain data about the first processor from the received broadcast message. For example, after receiving the broadcast message, the one or more second processors can store the received broadcast message in their internal registers and generate a notification message to their management module. The notification message can be sent to the management module in the form of an interrupt, so that the management module interrupts its current task and obtains data about the first processor from the register storing the received broadcast message, thereby completing one-to-many data synchronization from the first processor to the one or more second processors.

[0057] The above describes a data synchronization method for a first processor, which can quickly and efficiently synchronize data to one or more second processors in the form of broadcast transmission, thereby realizing one-to-many batch data synchronization. In addition, the data synchronization method can be completed by broadcast transmission on a bus based on a high-speed serial standard, which greatly improves the synchronization transmission speed and reduces the interaction time between processors compared to traditional data synchronization through a low-speed serial bus.

[0058] Refer to the following Figure 4 A data synchronization method for a second processor according to an embodiment of the present disclosure is described. Figure 4 4 shows a flow chart of a data synchronization method 400 for a second processor according to an embodiment of the present disclosure. The method 400 involves one or more first processors and a second processor connected to each other via a bus. The one or more first processors and the second processor may be as follows: Figure 1 Any of the plurality of processors 102 shown.

[0059] Method 400 describes a data synchronization operation for a second processor, wherein the second processor may receive synchronization data from one or more first processors. In step S402, a message from one or more first processors may be received via a bus and stored in a register for the second processor. The bus may be, for example, a bus based on the Peripheral Component Interconnect Express (PCIe) standard or other high-speed serial standards, which is not specifically limited in the embodiments of the present disclosure. The received message may be, for example, sent via the MCTP protocol, but the embodiments of the present disclosure are not limited thereto, and the message may also be sent using other suitable data transmission protocols.

[0060] The received message may include a data header and data content. The data header may include, for example, one or more of a type field for identifying a message type, a tag field for identifying a message purpose, an initiator ID field for identifying an identity (ID) of a message initiator, a vendor ID field for identifying a processor vendor ID, a target ID field for identifying a message destination, and the like. Figure 3 The data content included in the message may be status data indicating the operating status of one or more first processors, for example, data indicating the program version, operating temperature, operating frequency, operating voltage, power consumption, operating current, static information, etc. currently running on one or more first processors, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0061] According to an example of an embodiment of the present disclosure, a register for a second processor may include a data transmission bit, a data reception bit, and a broadcast message trigger bit, wherein the data transmission bit is used to store data content to be sent (e.g., sent via broadcast), the data reception bit is used to store received data content, and the broadcast message trigger bit can be used to complete the sending of a broadcast message when it is set. After receiving a message from one or more first processors, the second processor can store it in the data reception bit of the register.

[0062] In step S404, the received message may be parsed to determine the type and purpose of the message. For example, the type field of the data header of the message may be read to determine whether the message is a broadcast message, and the tag field of the data header of the message may be read to determine whether the message is used for data synchronization. Furthermore, the received message may also be parsed to preliminarily determine the data content included in the message.

[0063] In step S406, based on determining that the message is a broadcast message for data synchronization, a notification message may be generated, for example, to be sent to a management module included in or connected to the second processor. For example, the notification message may be sent to the management module in the form of an interrupt. Interrupt is an important concept in computer science, which refers to a mechanism in a computer system for pausing a currently executing program and processing more urgent tasks, thereby allowing the system to respond quickly to external events or internal conditions. By sending a notification message for a broadcast message in the form of an interrupt, the management module may interrupt its current task and perform rapid processing in response to the notification message.

[0064] In step S408, in response to the notification message, the synchronization data from one or more first processors included in the broadcast message can be obtained from the register. For example, when the management module for the second processor receives the notification message sent in the form of an interrupt, it can interrupt the current task and obtain the data included in the broadcast message from the register of the second processor. Specifically, when the data receiving bit of the register is composed of multiple register units, the management module can obtain the data included in the broadcast message by traversing each register unit of the data receiving bit of the register. The acquired data is the synchronization data from one or more first processors, which reflects the operating status of the one or more first processors. In other words, the second processor can obtain the synchronization data from one or more first processors by receiving the broadcast message, thereby realizing many-to-one data synchronization from one or more first processors to the second processor.

[0065] The above describes a data synchronization method for a second processor, which can quickly and efficiently receive synchronization data sent in a broadcast form from one or more first processors to achieve one-to-many or many-to-one data synchronization. In addition, the data synchronization method can be completed by broadcasting on a bus based on a high-speed serial standard, which greatly improves the synchronization transmission speed and reduces the interaction time between processors compared to traditional data synchronization through a low-speed serial bus.

[0066] Refer to above Figure 2 and Figure 4 The data synchronization methods 200 and 400 according to the embodiments of the present disclosure are described from the perspectives of sending synchronization data and receiving synchronization data, respectively. It is easy to understand that based on the above-mentioned data synchronization methods 200 and 400, the data synchronization method according to the embodiments of the present disclosure can also be performed simultaneously between multiple first processors and multiple second processors, thereby realizing many-to-many data synchronization, greatly improving the data synchronization efficiency, and is particularly suitable for real-time data synchronization of a server or computing network with multiple processors.

[0067] Refer to the following Figure 5A data synchronization device for a first processor according to an embodiment of the present disclosure is described. Figure 5 FIG. 5 shows a schematic diagram of the structure of a data synchronization device 500 for a first processor according to an embodiment of the present disclosure. Figure 5 As shown, the data synchronization device 500 may include a management module 502, a transmission control module 504, and a communication module 506. In addition to these three modules, the data synchronization device 500 may also include other modules, but since these modules are irrelevant to the content of the present disclosure, the detailed description of their contents is omitted here. The data synchronization device 500 may be included in the first processor, or connected to the first processor, and the embodiment of the present disclosure does not make specific restrictions on this.

[0068] The first processor may be connected to one or more second processors via a bus, and the first processor and the one or more second processors may be Figure 1 Any one of the multiple processors 102 shown. The first processor can synchronize its data to one or more second processors through the data synchronization device 500. Specifically, the management module 502 can obtain the data to be synchronized, and the data can be status data indicating the running status of the first processor, for example, data indicating the program version, operating temperature, operating frequency, operating voltage, power consumption, operating current, static information, etc. currently running on the first processor, and the embodiment of the present disclosure does not specifically limit this. According to an example of an embodiment of the present disclosure, the management module 502 can, for example, obtain and store data about the first processor through a hardware sensor.

[0069] The transmission control module 504 includes a register, and is configured to receive the data to be synchronized from the management module 502 and store it in the register. According to an example of an embodiment of the present disclosure, the register may include a data transmission bit, a data reception bit, and a broadcast message trigger bit, wherein the data transmission bit is used to store the data content to be sent (e.g., sent by broadcast), the data reception bit is used to store the received data content, and the broadcast message trigger bit can be used to complete the sending of the broadcast message when it is set. Among them, each of the data transmission bit, the data reception bit, and the broadcast message trigger bit can be composed of one or more register units of different bit lengths, for example. When the first processor needs to perform data synchronization, the management module 502 can send the data to be synchronized to the transmission control module 504, and the transmission control module 504 stores the data in the data transmission bit of the register to wait for transmission.

[0070] The communication module 506 is configured to send a broadcast message including data to be synchronized to one or more second processors via a bus in response to the register receiving a broadcast trigger command. In the embodiment of the present disclosure, the communication module 506 is a module having at least data sending and receiving functions, and optionally, the communication module 506 may have functions such as data packaging and data parsing, which are not specifically limited in the embodiment of the present disclosure. The broadcast trigger command may be issued, for example, by the management module 502 or other software modules for the first processor, and the broadcast trigger command is used to set the broadcast message trigger bit of the register so that the register outputs the data stored in its data sending bit for broadcast transmission. For example, the broadcast trigger command can complete the sending of the broadcast message by simply setting the broadcast message trigger bit of the register from "0" to "1", but this is only an example and not a limitation.

[0071] In an example of an embodiment of the present disclosure, the communication module 506 may use the Management Component Transport Protocol (MCTP) to send a broadcast message including data to be synchronized to one or more second processors via a bus, but the embodiment of the present disclosure is not limited thereto, and other suitable data transmission protocols may also be used. In this example, the transmission control module 504 may be, for example, an MCTP controller, which may package the data output from the register into a broadcast message in the MCTP format and send it to the communication module 506 for broadcast transmission. The transmission control module 504 is not limited to being an MCTP controller, but may also be other modules with a control function, and the embodiment of the present disclosure does not specifically limit this.

[0072] The broadcast message may include a data header and data content. The data header may include, for example, one or more of a type field for identifying the message type, a tag field for identifying the purpose of the message, an initiator ID field for identifying the identity (ID) of the message initiator, a vendor ID field for identifying the processor vendor ID, and a target ID field for identifying the destination of the message. Figure 3 See Figure 3 , the transmission control module 504 may set the type field of the broadcast message to indicate a broadcast message; and set the tag field to indicate a specific data format, such as a customized data format for inter-processor data synchronization, specifically, for example, the MCTP format. In addition, the transmission control module 504 may set the initiator ID field of the broadcast message to the processor node ID that sends the broadcast message, but may not need to set the target address of the data, i.e., the target ID field, and the broadcast message may be automatically broadcast to all processors connected to the bus.

[0073] In an embodiment of the present disclosure, multiple processors are interconnected through a bus, and the bus can be, for example, a bus based on the peripheral component interconnect high-speed (PCIe) standard or other high-speed serial standards, and the embodiment of the present disclosure does not specifically limit this. In view of the fact that multiple processors are interconnected through a bus, when data synchronization is performed between processors, one-to-many data synchronization can be achieved by sending a broadcast message on the bus. For example, the communication module 506 can send a broadcast message on a data synchronization bus based on the PCIe standard without interfering with an ordinary PCIe link. On the other hand, one or more second registers connected to the bus can receive the broadcast message and obtain data about the first processor from the received broadcast message. For example, after receiving the broadcast message, one or more second registers can generate a notification message to its management module, and the notification message can be sent to the management module in the form of an interrupt, so that it interrupts its current task and obtains data about the first processor from the register storing the received broadcast message, thereby completing one-to-many data synchronization from the first processor to one or more second processors.

[0074] The above describes a data synchronization device for a first processor, which can quickly and efficiently synchronize data to one or more second processors in the form of broadcast transmission, thereby realizing one-to-many batch data synchronization. In addition, the data synchronization device can be completed by broadcast transmission on a bus based on a high-speed serial standard, which greatly improves the synchronization transmission speed and reduces the interaction time between processors compared to traditional data synchronization through a low-speed serial bus.

[0075] Refer to the following Figure 6 A data synchronization device for a second processor according to an embodiment of the present disclosure is described. Figure 6 FIG. 6 is a schematic diagram showing a structure of a data synchronization device 600 for a second processor according to an embodiment of the present disclosure. Figure 6 As shown, the data synchronization device 600 may include a management module 602, a transmission control module 604, and a communication module 606. In addition to these three modules, the data synchronization device 600 may also include other modules, but since these modules are irrelevant to the content of the present disclosure, the detailed description of their contents is omitted here. The data synchronization device 600 may be included in the second processor, or connected to the second processor, and the embodiment of the present disclosure does not make specific restrictions on this.

[0076] The second processor can be connected to one or more first processors via a bus, and the second processor and the one or more first processors can be such as Figure 1 Any of the plurality of processors 102 shown. A second processor may receive synchronization data from one or more first processors via the data synchronization device 600 .

[0077] The communication module 606 may receive a message from one or more first processors via the bus, and store the message in a register included in the transmission control module 604. In the embodiment of the present disclosure, the communication module 606 is a module having at least data sending and receiving functions, and optionally, the communication module 606 may have functions such as data packaging and data parsing, which are not specifically limited in the embodiment of the present disclosure. The bus may be, for example, a bus based on the Peripheral Component Interconnect Express (PCIe) standard or other high-speed serial standards, which are not specifically limited in the embodiment of the present disclosure. The received message may be, for example, sent via the MCTP protocol, but the embodiment of the present disclosure is not limited thereto, and the message may also be sent using other suitable data transmission protocols. The transmission control module 604 may be, for example, an MCTP controller or other module having a control function, which is not specifically limited in the embodiment of the present disclosure.

[0078] The received message may include a data header and data content. The data header may include, for example, one or more of a type field for identifying a message type, a tag field for identifying a message purpose, an initiator ID field for identifying an identity (ID) of a message initiator, a vendor ID field for identifying a processor vendor ID, a target ID field for identifying a message destination, and the like. Figure 3 The data content included in the message may be status data indicating the operating status of one or more first processors, for example, data indicating the program version, operating temperature, operating frequency, operating voltage, power consumption, operating current, static information, etc. currently running on one or more first processors, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0079] According to an example of an embodiment of the present disclosure, the register of the transmission control module 604 may include a data transmission bit, a data reception bit, and a broadcast message trigger bit, wherein the data transmission bit is used to store the data content to be sent (e.g., sent by broadcast), the data reception bit is used to store the received data content, and the broadcast message trigger bit can be used to complete the sending of the broadcast message when it is set. After the communication module 606 receives the message from the one or more first processors, it can be sent and stored in the data reception bit of the register of the transmission control module 604.

[0080] The communication module 606 can also parse the received message to determine the type and purpose of the message. For example, the type field of the data header of the message can be read to determine whether the message is a broadcast message, and the tag field of the data header of the message can be read to determine whether the message is used for data synchronization. Further, the communication module 606 can also parse the received message to preliminarily determine the data content included in the message.

[0081] Based on determining that the message is a broadcast message for data synchronization, the communication module 606 may generate a notification message to send to the management module 602. For example, the communication module 606 may send the notification message to the management module in the form of an interrupt. By sending a notification message for a broadcast message in the form of an interrupt, the management module 602 may interrupt its current task and instead perform a quick process in response to the notification message.

[0082] In response to the notification message, the management module 602 can obtain the synchronization data from the one or more first processors included in the broadcast message from the register of the transmission control module 604. For example, when the management module 602 receives the notification message sent in the form of an interrupt, it can interrupt the current task and obtain the data included in the broadcast message from the register of the transmission control module 604. Specifically, when the data receiving bit of the register is composed of multiple register units, the management module 602 can obtain the data included in the broadcast message by traversing each register unit of the data receiving bit of the register. The acquired data is the synchronization data from the one or more first processors, which indicates the operating status of the one or more first processors. That is to say, the second processor can obtain the synchronization data from the one or more first processors by receiving the broadcast message, thereby realizing many-to-one data synchronization from the one or more first processors to the second processor.

[0083] The above describes a data synchronization device for a second processor, which can quickly and efficiently receive synchronization data sent in a broadcast form from one or more first processors to achieve one-to-many or many-to-one data synchronization. In addition, the data synchronization device can be completed by broadcasting on a bus based on a high-speed serial standard, which greatly improves the synchronization transmission speed and reduces the interaction time between processors compared to traditional data synchronization through a low-speed serial bus.

[0084] The present disclosure also provides a processor system, including multiple processors interconnected by a bus, and the multiple processors can be located on a server motherboard or in a computing network. Each of the multiple processors can be, for example, Figure 1 According to an embodiment of the present disclosure, each of the plurality of processors may be a first processor, and its corresponding data synchronization device may execute the above reference Figure 2 Alternatively, each of the plurality of processors may be a second processor, and its corresponding data synchronization device may execute the data synchronization method 200 described above with reference to Figure 4The data synchronization method 400 for the second processor is described. That is, each processor in the processor system can act as a data synchronization initiator to broadcast synchronization data to one or more other processors, and can also act as a data synchronization receiver to receive the broadcast synchronization data from one or more other processors. Thus, the processor system according to the embodiment of the present disclosure can realize one-to-many, many-to-one and many-to-many batch data synchronization.

[0085] Figure 7 An example of a processor system according to an embodiment of the present disclosure is shown, wherein four processors are shown by way of example and not limitation. It is to be understood that, based on actual needs, the processor system according to an embodiment of the present disclosure may include more or fewer processors. Figure 7 As shown, the processor system 700 may include a first processor 702 and second processors 704, 706 and 708, wherein the first processor 702 broadcasts synchronization data to the second processors 704, 706 and 708. The processors in the processor system may be connected to each other via a bus 710. Figure 7 In the example of FIG. 7 , for convenience of description, only bus connections from the first processor 702 to each of the second processors 704 , 706 , and 708 are exemplarily shown.

[0086] exist Figure 7 In the example, each of the multiple processors is configured with a data synchronization device including a management module, a transmission control module and a communication module. It should be noted that for the sake of simplicity, Figure 7 The modules of the data synchronization device corresponding to each processor in the embodiment are shown as being included inside the processor, but the embodiments of the present disclosure are not limited thereto. According to actual design requirements, one or more of the modules of the data synchronization device for the processor may also be arranged outside the processor. For example, the management module may be arranged outside the processor and communicatively connected to the processor.

[0087] Reference Figure 7At a certain moment, the first processor 702 wants to synchronize data with other processors in the processor system, such as status data indicating the operating status of the first processor. Then the management module 702_1 of the first processor 702 can obtain the data to be synchronized, for example, through the hardware sensor in the processor system to obtain data about the first processor. The management module 702_1 stores the data to be synchronized in a register (not shown) in the transmission control module 702_2, for example, in the data transmission bit of the register, waiting for broadcast transmission. When the register receives a broadcast trigger command, such as a broadcast trigger command from the management module 702_1 or other software modules in the processor system, the broadcast message trigger bit of the register is set, for example, from "0" to "1", and the register outputs the data to be synchronized stored in the message transmission bit. The transmission control module 702_2 can package the data to be synchronized into a broadcast message in a specific format, such as a broadcast message in the MCTP format, and send it to the communication module 702_3 for broadcast transmission.

[0088] The communication module 702_3 can send broadcast messages on the bus 710. As described above, the bus 710 can be, for example, a bus based on the peripheral component interconnect high speed (PCIe) standard or other high-speed serial standards. Through the bus 710, the broadcast message is sent to a plurality of second processors 704, 406 and 708 connected to the bus 710.

[0089] Taking the second processor 704 as an example, when its communication module 704_3 receives a message from the first processor 702 through the bus 710, the message can be stored in the register (e.g., data receiving bit) of the transmission control module 704_2, and the message can be preliminarily parsed to determine the type and purpose of the message. Optionally, the communication module 704_3 can also further parse the message to determine the data content included in the message. For example, the communication module 704_3 can determine whether the message is a broadcast message by reading the type field of the data header of the message, and can read the tag field of the data header of the message to determine whether the message is used for data synchronization. When it is determined that the message is a broadcast message for data synchronization, the communication module 704_3 can send a notification message to the management module 704_1. The notification message can be sent to the management module in the form of an interrupt, so that the management module interrupts its current task and responds to the notification message for rapid processing. In response to the notification message, the management module 704_1 can interrupt its current task and obtain the data included in the broadcast message from the register of the transmission control module management module 704_2.

[0090] Similarly, when the second processors 706 and 708 receive a message from the first processor 702 through the bus 710, they can obtain the data included in the broadcast message after determining that the message is a broadcast message for data synchronization. In this way, a one-to-many fast and efficient batch data synchronization is achieved from the first processor 702 to the plurality of second processors 704, 706 and 708.

[0091] According to an example of an embodiment of the present disclosure, the first processor 702 may also receive synchronization data broadcasted by the second processors 704, 706, and 708, thereby implementing many-to-one batch data synchronization; or, multiple first processors ( Figure 7 Only one is schematically shown in the figure) and synchronization data can be broadcast to multiple second processors, thereby realizing many-to-many batch data synchronization.

[0092] The processor system according to the embodiment of the present disclosure can quickly and efficiently complete one-to-many, many-to-one, or even many-to-many batch data synchronization between multiple processors in the form of broadcast transmission, which greatly improves the data synchronization efficiency compared to the traditional one-to-one data synchronization method. In addition, the processor system can complete data synchronization by broadcasting on a bus based on a high-speed serial standard, which greatly improves the synchronization transmission speed and reduces the interaction time between processors compared to the traditional data synchronization through a low-speed serial bus.

[0093] The present disclosure also provides a server, which may include a reference Figure 7 The server according to the embodiment of the present disclosure may be an independent server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, positioning services, and big data and artificial intelligence platforms, and the embodiment of the present disclosure does not impose specific restrictions on this.

[0094] The embodiments of the present disclosure may also be implemented as a computer-readable storage medium. Computer-readable instructions are stored on a computer-readable storage medium according to an embodiment of the present disclosure. When the computer-readable instructions are executed by a processor, the data synchronization method according to the embodiment of the present disclosure described with reference to the above figures may be executed. The computer-readable storage medium includes, but is not limited to, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0095] According to an embodiment of the present disclosure, a computer program product or a computer program is also provided, the computer program product or the computer program includes computer-readable instructions, and the computer-readable instructions are stored in a computer-readable storage medium. The processor of the computer device can read the computer-readable instructions from the computer-readable storage medium, and the processor executes the computer-readable instructions, so that the computer device executes the data synchronization method described in the above various embodiments.

[0096] The program part of the technology can be considered as a "product" or "manufactured product" in the form of executable code and / or related data, which is participated in or realized by computer-readable media. Tangible and permanent storage media can include any memory or storage used by any computer, processor, or similar device or related module. For example, various semiconductor memories, tape drives, disk drives or any similar devices that can provide storage functions for software.

[0097] All software or parts of it may sometimes be communicated over a network, such as the Internet or other communications network. Such communications can load software from one computer device or processor to another. Therefore, another medium capable of transmitting software elements may also be used as a physical connection between local devices, such as light waves, radio waves, electromagnetic waves, etc., transmitted through cables, optical cables or air. Physical media used to carry carriers, such as cables, wireless connections or optical cables and the like, can also be considered as media that carry software. As used herein, unless limited to tangible "storage" media, other terms referring to computer or machine "readable media" refer to media that participate in the process of executing any instructions by the processor.

[0098] The present application uses specific words to describe the embodiments of the present application. For example, "first / second embodiment", "one embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or multiple times in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0099] In addition, it will be appreciated by those skilled in the art that various aspects of the present application may be illustrated and described by a number of patentable categories or situations, including any new and useful process, machine, product or combination of substances, or any new and useful improvements thereto. Accordingly, various aspects of the present application may be performed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The above hardware or software may all be referred to as "data blocks", "modules", "engines", "units", "components" or "systems". In addition, various aspects of the present application may be represented as a computer product located in one or more computer-readable media, which includes computer-readable program code.

[0100] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined as such herein.

[0101] The above is an explanation of the present invention and should not be considered as a limitation thereof. Although several exemplary embodiments of the present invention have been described, it will be readily appreciated by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. It should be understood that the above is an explanation of the present invention and should not be considered as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present invention is defined by the claims and their equivalents.

Claims

1. A data synchronization method for a first processor, wherein the first processor and one or more second processors are connected to each other via a bus, the method comprising: Get the data to be synchronized; storing the data in a register of the first processor; as well as In response to the register receiving a broadcast trigger command, a broadcast message including the data is sent to the one or more second processors via the bus, so that when the one or more second processors receive the broadcast message, they obtain the data included in the broadcast message in response to a notification message for the broadcast message.

2. The method according to claim 1, wherein: The data includes status data indicative of an operational status of the first processor.

3. The method according to claim 1, wherein: The register includes a data send bit, and wherein storing the data in the register of the first processor includes: The data is stored in the data send bit of the register of the first processor.

4. The method according to claim 1 or 3, wherein: The register further includes a broadcast message trigger bit, and the broadcast trigger command is used to set the broadcast message trigger bit of the register so that the register outputs the data.

5. The method according to claim 1, wherein: The broadcast message also includes one or more of a type field for identifying the message type, a tag field for identifying the purpose of the message, an originator ID field for identifying the identity (ID) of the message originator, a vendor ID field for identifying the processor vendor ID, and a target ID field for identifying the destination of the message.

6. A data synchronization method for a second processor, wherein the second processor is connected to one or more first processors via a bus, the method comprising: receiving a message from the one or more first processors via the bus and storing the message in a register of the second processor; parsing the message to determine the type and purpose of the message; generating a notification message based on determining that the message is a broadcast message for data synchronization; as well as In response to the notification message, the synchronization data from the one or more first processors included in the broadcast message is obtained from the register.

7. The method according to claim 6, wherein: The synchronization data includes status data indicating an operational status of the one or more first processors.

8. The method according to claim 6, wherein: The register includes a data receive bit, and wherein storing the message in the register of the second processor comprises: The message is stored in the data received bit of a register of the second processor.

9. The method according to claim 8, wherein: Acquiring the synchronization data from the one or more first processors included in the broadcast message from the register includes: The synchronization data included in the broadcast message is obtained by traversing the data receiving bit of the register.

10. The method according to claim 6, wherein: The message includes one or more of a type field for identifying the message type, a tag field for identifying the purpose of the message, an initiator ID field for identifying the identity (ID) of the message initiator, a vendor ID field for identifying the processor vendor ID, and a target ID field for identifying the destination of the message.

11. The method according to claim 10, wherein: Parsing the message to determine the type and purpose of the message includes: reading the type field in the message to determine whether the message is a broadcast message; and The tag field in the message is read to determine whether the message is for data synchronization.

12. A data synchronization method for a plurality of processors, the plurality of processors comprising a first processor and one or more second processors interconnected via a bus, the method comprising: The first processor acquires data to be synchronized, and stores the data in a register of the first processor; In response to a register of the first processor receiving a broadcast trigger command, the first processor sending a broadcast message including the data to the one or more second processors via the bus; After receiving the broadcast message via the bus, the one or more second processors store the broadcast message in registers of the one or more second processors; the one or more second processors parsing the received broadcast message to determine its type and purpose, and generating a notification message based on determining that the received broadcast message is a broadcast message for data synchronization; as well as In response to the notification message, the one or more second processors obtain the data from the first processor included in the broadcast message from registers of the one or more second processors.

13. The method according to claim 12, wherein: The broadcast message uses the Management Component Transport Protocol (MCTP).

14. The method according to claim 12, wherein: The notification message is sent to the management module of the one or more second processors in the form of an interrupt.

15. A data synchronization device for a first processor, wherein the first processor and one or more second processors are connected to each other via a bus, the device comprising: A management module, configured to obtain data to be synchronized; a transmission control module, comprising a register, wherein the transmission control module is configured to receive the data from the management module and store the data in the register; as well as The communication module is configured to send a broadcast message including the data to the one or more second processors via the bus in response to the register receiving a broadcast trigger command, so that the one or more second processors, when receiving the broadcast message, obtain the data included in the broadcast message in response to a notification message for the broadcast message.

16. A data synchronization device for a second processor, wherein the second processor is connected to one or more first processors via a bus, the device comprising: a communication module configured to receive a message from the one or more first processors via the bus, parse the message to determine a type and purpose of the message, and generate a notification message based on determining that the message is a broadcast message for data synchronization; a transmission control module, comprising a register, wherein the transmission control module is configured to receive the message from the communication module and store the message in the register; as well as The management module is configured to receive the notification message, and in response to the notification message, obtain the synchronization data from the one or more first processors included in the broadcast message from the register of the transmission control module.

17. A processor system, comprising a plurality of processors interconnected via a bus, each of the plurality of processors being configured with a data synchronization device, the data synchronization device being configured to execute the method according to any one of claims 1 to 14.

18. A server comprising the processor system according to claim 17.

19. A computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor is caused to execute the method according to any one of claims 1 to 14.

20. A computer program product comprising computer readable instructions, which, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 14.

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