Heterogeneous acceleration system, method and device, computing equipment and storage medium

Abstract

The invention relates to the technical field of computers, and discloses a heterogeneous acceleration system, method and device, a computing device and a storage medium, the heterogeneous acceleration system comprises a host end, a plurality of heterogeneous acceleration clusters and a storage device used for storing target data, and the host end is used for sending an acceleration computing request to the heterogeneous acceleration clusters; when any target heterogeneous acceleration device in the heterogeneous acceleration cluster receives an acceleration calculation request, responding to the acceleration calculation request, adopting a preset direct transmission mode, directly reading the target data from the storage device, and performing corresponding calculation processing on the target data to obtain an acceleration calculation result; writing the acceleration calculation result into the target cache device; and the host side directly accesses the target cache device to obtain an acceleration calculation result. The transmission path of the target data is shortened, and the time consumption of the target data in the transmission process is reduced, so that the data transmission delay of the target heterogeneous acceleration equipment is reduced, and a foundation is laid for improving the performance of computing equipment.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a heterogeneous acceleration system, method, apparatus, computing device and storage medium. Background Art

[0002] In today's era of rapid development of information technology, the data processing tasks carried by computing devices such as servers are becoming increasingly heavy, and the amount of data in the database is growing massively. Faced with frequent data reading needs, the traditional method of reading data only on the host side has obvious drawbacks. Therefore, introducing heterogeneous acceleration devices to assist servers in reading database data has become a necessary choice to improve system data throughput and response speed.

[0003] In related technologies, data in the disk is usually first transferred to the file cache on the host side, then to the internal cache of the process, and finally to the heterogeneous acceleration device. The heterogeneous acceleration device performs corresponding acceleration tasks based on the obtained data, and finally feeds back the acceleration task execution results to the host side.

[0004] In general, it can be seen that the entire data transmission path is long, and the data in the disk needs to go through multiple data forwarding before entering the heterogeneous acceleration device. The data transmission process has a large delay. Even if the heterogeneous acceleration device has powerful data processing capabilities, the overall delay is still very prominent, and the acceleration advantage is difficult to fully demonstrate, which seriously restricts the performance of computing devices in high-performance data processing scenarios. Summary of the invention

[0005] The present application provides a heterogeneous acceleration system, method, apparatus, computing device and storage medium to solve the defects of the related art such as large delay in the data transmission process of heterogeneous acceleration devices.

[0006] The first aspect of the present application provides a heterogeneous acceleration system, comprising: a host end, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, wherein the heterogeneous acceleration cluster comprises a plurality of heterogeneous acceleration devices; The host end is used to send an accelerated computing request to the heterogeneous acceleration cluster; Any target heterogeneous acceleration device in the heterogeneous acceleration cluster is used to, upon receiving the accelerated computing request, respond to the accelerated computing request, adopt a preset direct transmission mode, directly read the target data from the storage device, perform corresponding computing processing on the target data, obtain an accelerated computing result, and write the accelerated computing result into a target cache device; The host end is used to directly access the target cache device to obtain the accelerated calculation result.

[0007] In an optional implementation, the target heterogeneous acceleration device includes: A target protocol control module, configured to receive the accelerated computing request sent by the host; wherein the target cache device includes a device memory of a target heterogeneous acceleration device, and the host directly accesses the device memory through the target protocol control module to maintain cache consistency between the host and the target heterogeneous acceleration device; The target protocol control module is connected to a target protocol switch so that the target heterogeneous acceleration device communicates with the host end and the storage device through the target protocol switch.

[0008] In an optional implementation manner, the host end is used to: Get the raw data request entered by the user; In response to the original data request, allocating a virtual address of the target data on the target heterogeneous acceleration device; Determining configuration parameters of the accelerated computing request according to the virtual address and the original data request; An accelerated computing request is generated according to the configuration parameters of the accelerated computing request, and the accelerated computing request is sent to the target heterogeneous acceleration device.

[0009] In an optional implementation manner, the host end is used to: Convert the virtual address into a physical address in the device memory of the heterogeneous accelerator card; Determine a bus address according to the physical address, and use the bus address as the destination address; Determine, according to the original data request, file index information of the file to be accessed and a logical offset value of the target data in the file to be accessed; Determine the source address and data length of the target data in the storage device according to the file index information of the file to be accessed and the logical offset value of the target data in the file to be accessed; Generate a direct storage device access descriptor according to the destination address, source address and data length; Based on the direct storage device access descriptor, an accelerated computing request is generated, so that the target heterogeneous acceleration device responds to the accelerated computing request based on a direct storage device access engine.

[0010] In an optional implementation, the target cache device includes a device memory of a target heterogeneous acceleration device, and the target heterogeneous acceleration device is used to: In response to the accelerated computing request, sending an access start command to the storage device, so that the storage device responds to the access start command and adopts a preset direct transfer mode to move the target data to the peer access space in the device memory according to the destination address; When the accelerated calculation result is obtained, writing the accelerated calculation result into the peer access space; The peer access space in the device memory is exposed on the peer communication bus of the target heterogeneous acceleration device, and the peer access space supports direct access between the host and the storage device.

[0011] In an optional implementation manner, the host end is used to: An interrupt signal fed back by the target heterogeneous acceleration device when the accelerated computing result is obtained is received, and in response to the interrupt signal, a peer access space of the target heterogeneous acceleration device is directly accessed to obtain the accelerated computing result.

[0012] In an optional implementation manner, the storage device is used to: The target data read by the target heterogeneous acceleration device is used as original data that meets the current query condition, and the original data is transmitted to the file cache system of the host end; Wherein, the accelerated calculation result includes current query condition information.

[0013] In an optional implementation, the heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate with each other in a fully connected manner, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate with each other through a target protocol switch.

[0014] In an optional implementation manner, the host end is used to: Obtaining a global heterogeneous acceleration status table; wherein the global heterogeneous acceleration configuration table includes global location information, acceleration unit function, current usage, instruction type, current task execution information and current resource occupancy information of each acceleration unit, and each of the heterogeneous acceleration devices includes multiple acceleration units; According to the accelerated computing requirement represented by the accelerated computing request, screening in the global heterogeneous acceleration state table a candidate heterogeneous acceleration device whose acceleration unit function matches the accelerated computing requirement; According to the global heterogeneous acceleration state table, a target heterogeneous acceleration device is screened from the candidate heterogeneous acceleration devices to send the accelerated computing request to the target heterogeneous acceleration device.

[0015] In an optional implementation manner, the host end is used to: Analyzing the task execution characteristics of the accelerated computing request to obtain the task execution characteristic information of the accelerated computing request; When the task execution characteristic information indicates that the task execution mode of the accelerated computing request is a sequential mode, selecting a plurality of target acceleration units from the candidate heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster; The selected heterogeneous acceleration device including the target acceleration unit is used as the target heterogeneous acceleration device.

[0016] In an optional implementation manner, the host end is used to: In a case where the task execution characteristic information indicates that the task execution mode of the accelerated computing request is a disordered mode, screening a plurality of target acceleration units whose remaining computing resources meet a preset screening condition in the to-be-selected heterogeneous acceleration device; The selected heterogeneous acceleration device including the target acceleration unit is used as the target heterogeneous acceleration device.

[0017] In an optional implementation manner, the host end is further used for: Generate a target token for the target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address start address, a data length, a read / write permission bit, a unique identifier of the heterogeneous acceleration device, a unique identifier of the acceleration unit, and a target priority; According to the unique identifier of the heterogeneous acceleration device, the target token is sent to the corresponding target heterogeneous acceleration device, so that the target heterogeneous acceleration device executes the heterogeneous acceleration task to be executed based on the target token, so as to perform corresponding calculation processing on the target data and obtain an accelerated calculation result.

[0018] In an optional implementation, the target heterogeneous acceleration device is used to: Receiving a target token sent by the host end; When the valid bit of the target token indicates that the token is currently valid, determining the target acceleration unit of the to-be-executed heterogeneous acceleration task and the task type of the to-be-executed heterogeneous acceleration task according to the unique identifier of the acceleration unit in the target token; Determine the permission range of the target acceleration unit according to the physical address starting address, data length and read / write permission bits in the target token; wherein the permission range includes a target read / write range for the target cache device; The execution priority of the target acceleration unit is determined according to the target priority in the target token.

[0019] In an optional implementation manner, the host end is used to: Obtaining the number of waiting cycles of each acceleration unit to be selected in the heterogeneous acceleration device to be selected; Determine the time priority of the acceleration unit to be selected according to the number of waiting cycles of the acceleration unit to be selected; obtain the task priority of the heterogeneous acceleration task to be executed corresponding to the acceleration unit to be selected; The target priority is determined according to the time priority and task priority of the acceleration unit to be selected.

[0020] In an optional implementation, a target communication interface is provided between the host end and each of the heterogeneous acceleration devices, the accelerated computing request includes a database query statement, and the target communication interface is used to: Performing semantic analysis on the database query statement to obtain a semantic analysis result; Extracting target action instructions from the database query statement according to the semantic analysis result; According to the target action instruction, converting the database query statement into a heterogeneous acceleration device general statement, so as to input the heterogeneous acceleration device general statement into the target heterogeneous acceleration device; The target action instructions include at least data query instructions, data insertion instructions, data update instructions and data deletion instructions.

[0021] A second aspect of the present application provides a heterogeneous acceleration method, which is applied to a host side and includes: Sending an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read target data from a storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode, wherein the storage device is used to store the target data, and performing corresponding computing processing on the target data to obtain an accelerated computing result, and writing the accelerated computing result into a target cache device; When it is determined that the heterogeneous acceleration device has written the accelerated computing result into the target cache device, the target cache device is directly accessed to obtain the accelerated computing result.

[0022] A third aspect of the present application provides a heterogeneous acceleration method, which is applied to a target heterogeneous acceleration device, and the method includes: Receive the accelerated computing request sent by the host; In response to the accelerated computing request, directly reading the target data from the storage device using a preset direct transmission mode; wherein the storage device is used to store the target data; Performing corresponding calculation processing on the target data to obtain an accelerated calculation result, and writing the accelerated calculation result into a target cache device; An interrupt request is sent to the host end to instruct the host end to directly access the target cache device so that the host end obtains the accelerated calculation result.

[0023] A fourth aspect of the present application provides a heterogeneous acceleration device, which is applied to a host side and includes: The request acceleration module is used to send an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read the target data from the storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode, and the storage device is used to store the target data, and perform corresponding computing processing on the target data to obtain an accelerated computing result, and write the accelerated computing result into a target cache device; The reading module is used to directly access the target cache device to obtain the accelerated computing result when it is determined that the heterogeneous acceleration device has written the accelerated computing result into the target cache device.

[0024] A fifth aspect of the present application provides a heterogeneous acceleration device, which is applied to a target heterogeneous acceleration device, and includes: A receiving module, used for receiving an accelerated computing request sent by a host; A data reading module, configured to respond to the accelerated computing request and directly read the target data from the storage device using a preset direct transmission mode; wherein the storage device is used to store the target data; An accelerated computing module, used to perform corresponding computing processing on the target data, obtain an accelerated computing result, and write the accelerated computing result into a target cache device; The sending module is used to send an interrupt request to the host end to instruct the host end to directly access the target cache device so that the host end can obtain the accelerated calculation result.

[0025] A sixth aspect of the present application provides a computing device, comprising: a heterogeneous acceleration system as described in the first aspect and various possible designs of the first aspect.

[0026] The seventh aspect of the present application provides a non-volatile computer-readable storage medium, in which computer execution instructions are stored. When a processor executes the computer execution instructions, the method described in the second aspect and various possible designs of the second aspect or the method described in the third aspect and various possible designs of the third aspect are implemented.

[0027] The eighth aspect of the present application provides a computer program product, including computer instructions, which are used to enable a computer to execute the method described in the second aspect and various possible designs of the second aspect or the method described in the third aspect and various possible designs of the third aspect.

[0028] The technical solution of this application has the following advantages: The present application provides a heterogeneous acceleration system, method, apparatus, computing device and storage medium, the system comprising: a host end, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, the heterogeneous acceleration cluster comprising a plurality of heterogeneous acceleration devices; the host end is used to send an accelerated computing request to the heterogeneous acceleration cluster; any target heterogeneous acceleration device in the heterogeneous acceleration cluster is used to respond to the accelerated computing request in the case of receiving the accelerated computing request, adopt a preset direct transmission mode, directly read the target data from the storage device, and perform corresponding computing processing on the target data to obtain the accelerated computing result, and write the accelerated computing result into the target cache device; the host end is used to directly access the target cache device to obtain the accelerated computing result. In the system provided by the above scheme, the target heterogeneous acceleration device can directly obtain the target data from the storage device by direct data transmission, which greatly shortens the transmission path of the target data and reduces the time consumption of the target data during the transmission process, thereby reducing the data transmission delay of the target heterogeneous acceleration device, laying a foundation for improving the performance of the computing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the following is a brief introduction to the drawings required for use in the embodiments or the related technical descriptions. Obviously, the drawings described below are some embodiments of the present application, and a person skilled in the art can also obtain other drawings based on these drawings.

[0030] Figure 1 A flowchart of a heterogeneous acceleration method for traditional database query services; Figure 2 A schematic diagram of the interaction process of the heterogeneous acceleration system provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a heterogeneous acceleration system provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a heterogeneous acceleration device provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of another heterogeneous acceleration system provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of the target token provided in the embodiment of the present application; Figure 7 A schematic diagram of a heterogeneous acceleration method provided in an embodiment of the present application; Figure 8 A schematic diagram of a process flow of another heterogeneous acceleration method provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a heterogeneous acceleration device provided in an embodiment of the present application; Fig.10 A schematic diagram of the structure of another heterogeneous acceleration device provided in an embodiment of the present application; Fig.11 A schematic diagram of the structure of a computing device provided in an embodiment of the present application.

[0031] The above drawings have shown clear embodiments of the present application, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the following embodiments, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0034] In related technologies, with the continuous development of technologies such as mobile Internet, artificial intelligence, big data analysis, and scientific computing, the amount of data is growing exponentially, and the demand for data processing and analysis is also increasing. In this context, traditional database systems that only use central processing units (CPUs) as core computing components are facing huge challenges. Their ability to process massive amounts of data, ensure data real-time, and cope with diverse workloads is quite insufficient.

[0035] Database heterogeneous acceleration, which uses heterogeneous acceleration devices such as Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), and dedicated processors to improve the running speed, has thus come into being. It makes full use of different types of hardware resources, such as CPU, GPU, FPGA, dedicated processors, etc., and combines software and hardware optimization technologies to improve the performance and efficiency of database systems. On the one hand, dedicated hardware acceleration through parallel processing and pipeline; on the other hand, software heterogeneous acceleration can significantly improve the computing speed and storage efficiency of the database by means of database engine customization, query optimization technology, and data compression algorithms. It is worth mentioning that in the existing heterogeneous computing architecture, when page data is directly accessed from the host CPU side to the hardware acceleration device, it is first transferred from the disk to the file cache on the host side, then read into the process internal cache, and finally transferred to the FPGA. The transmission path is long and the number of copies is large. The data transmission is forwarded multiple times, resulting in low efficiency.

[0036] Among them, Figure 1 As shown in FIG. 1 , a flow chart of a heterogeneous acceleration method for a traditional database query service is shown. The flow chart is as follows: the host first starts DMA transmission from the host side to read the target file page from the disk to the file system cache; the host side applies for a pin page (physical memory page) in the database application and copies data from the file system cache to the database pin page. The host side starts DMA transmission to transmit the database pin page content to the heterogeneous acceleration device so that the heterogeneous acceleration device obtains the database page. After the heterogeneous acceleration device obtains the database page, it starts parallel computing, performs filtering calculation on the page, finds the row records matching the filtering conditions, and obtains the matching results. Then, the row records matching the filtering conditions are extracted, and projection calculation is performed to extract the disassembly results from the matching results, that is, the target retrieval fields are assembled into query results. After obtaining the query results, the query results are sent to the host side memory so that the host side obtains the query results. In this process, since multiple transmissions are involved, a large transmission delay and a high CPU load will be generated, and a large amount of host side memory will also be required.

[0037] In view of the above problems, the embodiments of the present application provide a heterogeneous acceleration system, method, apparatus, computing device and storage medium, the system comprising: a host end, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, the heterogeneous acceleration cluster comprising a plurality of heterogeneous acceleration devices; the host end is used to send an accelerated computing request to the heterogeneous acceleration cluster; any target heterogeneous acceleration device in the heterogeneous acceleration cluster is used to respond to the accelerated computing request in the case of receiving the accelerated computing request, adopt a preset direct transmission mode, directly read the target data from the storage device, and perform corresponding computing processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device; the host end is used to directly access the target cache device to obtain the accelerated computing result. In the system provided by the above scheme, the target heterogeneous acceleration device can directly obtain the target data from the storage device by direct data transmission, which greatly shortens the transmission path of the target data and reduces the time consumption of the target data during the transmission process, thereby reducing the data transmission delay of the target heterogeneous acceleration device, laying a foundation for improving the performance of the computing device.

[0038] The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0039] The embodiment of the present application provides a heterogeneous acceleration system for reducing the data transmission delay from target data to a heterogeneous acceleration device when accelerating a host-side computing task based on the heterogeneous acceleration device.

[0040] like Figure 2 As shown, it is a schematic diagram of the interaction process of the heterogeneous acceleration system provided in an embodiment of the present application. The system includes: a host side, a plurality of heterogeneous acceleration clusters and a storage device for storing target data. The heterogeneous acceleration cluster includes a plurality of heterogeneous acceleration devices.

[0041] Among them, the host side is used to send an accelerated computing request to the heterogeneous acceleration cluster; any target heterogeneous acceleration device in the heterogeneous acceleration cluster is used to respond to the accelerated computing request when receiving the accelerated computing request, adopt a preset direct transmission mode, directly read the target data from the storage device, and perform corresponding calculation processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device; the host side is used to directly access the target cache device to obtain the accelerated computing result.

[0042] The target cache device includes the device memory of the target heterogeneous acceleration device, the storage device, and the system memory of the host.

[0043] It should be noted that the host side includes the CPU, etc. The host side, as the control center of the system, is responsible for sending accelerated computing requests to the heterogeneous acceleration cluster. At the beginning of the data processing process, the host side receives the computing task instructions from the user or the upper-layer application, converts them into accelerated computing requests, and accurately sends them to the heterogeneous acceleration cluster. In addition, the host side also has the ability to directly access the memory of the heterogeneous acceleration device. After the target heterogeneous acceleration device completes the calculation, the host side can directly obtain the accelerated computing results stored in the device memory for subsequent data processing, analysis or direct output to the corresponding user.

[0044] It should be further explained that the heterogeneous acceleration cluster is composed of multiple heterogeneous acceleration devices, and the types of heterogeneous acceleration devices are diverse, such as GPU, FPGA, etc., each of which is good at different types of computing tasks. When a target heterogeneous acceleration device in the heterogeneous acceleration cluster receives an accelerated computing request from the host, it responds quickly. The preset direct transmission mode is adopted to bypass the intermediate links such as host memory that may be passed in traditional data transmission, and the target data is directly read from the storage device. This direct transmission mode greatly reduces the data transmission path and reduces the delay and overhead of data during transmission. After reading the target data, the target heterogeneous acceleration device uses its own computing resources to perform corresponding calculations on the data according to the task requirements, such as complex mathematical operations. After the calculation is completed, the accelerated calculation results are written into its own device memory and wait for the host to read.

[0045] Based on the above embodiments, Figure 3 A schematic diagram of a heterogeneous acceleration system provided in an embodiment of the present application is provided. As an implementable method, in one embodiment, a target heterogeneous acceleration device includes: The target protocol control module is used to receive the accelerated computing request sent by the host side; wherein the host side directly accesses the device memory (DRAM) through the target protocol control module to maintain cache consistency between the host side and the target heterogeneous acceleration device.

[0046] The target protocol control module (CXL control module) is connected to the target protocol switch so that the target heterogeneous acceleration device can communicate with the host and storage device through the target protocol switch. The device memory of the target heterogeneous acceleration device is the dynamic random access memory (DRAM).

[0047] It should be noted that the target protocol adopted in the embodiment of the present application is an open high-speed interconnection standard (Compute Express Link, CXL for short) protocol. In the related art, the host-side CPU and the heterogeneous acceleration device are mainly connected through the traditional PCIe bus. In this case, the memory of the heterogeneous acceleration device and the CPU addressing space are not uniformly addressed, which results in the CPU being unable to directly access the memory of the acceleration device at a byte granularity. At the same time, the PCIe bus does not have a cache consistency feature. When the heterogeneous acceleration device modifies the memory device, the CPU host side cannot perceive the data modification. When data is transmitted between the host side and the acceleration card, it is necessary to first flush the respective caches into the memory, and then start the DMA transmission. Such a transmission process has a large delay. Cache consistency buses such as CXL, OpenCAPI, and Cache Coherent Interconnect eXtension (CCIX for short) can solve the above problems. The acceleration card side memory (device memory) and the host side memory are uniformly addressed, and the cache consistency is maintained by hardware, so that the CPU can access the acceleration card memory like accessing local memory.

[0048] Based on the above embodiments, as an implementable method, in one embodiment, the host side is used to obtain the original data request input by the user; in response to the original data request, the virtual address of the target data on the target heterogeneous acceleration device is allocated; according to the virtual address and the original data request, the configuration parameters of the accelerated computing request are determined; according to the configuration parameters of the accelerated computing request, the accelerated computing request is generated, and the accelerated computing request is sent to the target heterogeneous acceleration device.

[0049] Among them, the original data request input by the user includes a data query request, etc. The virtual address is obtained by the application layer through an address mapping (memory map, abbreviated as: mmap) function to obtain a cache space.

[0050] Specifically, first, the user initiates a request to read the file "file name" through the application layer; the host side obtains the file meta information according to the file name in the kernel file system layer, and the file meta information at least includes the file index information of the file to be accessed in the storage device; initiates a DMA operation and saves the file meta information (Inode) to the host memory; calculates the offset of the file data block in the disk (storage device) through the file meta information (inode) and the access address carried by the original data request; then fills in the DMA descriptor to obtain the configuration parameters of the accelerated computing request, and generates a corresponding accelerated computing request to configure the source address on the disk and the destination address on the FPGA (target heterogeneous acceleration device) memory device, so that the target heterogeneous acceleration device starts the disk controller to initiate the corresponding CXL P2P-DMA operation and start moving data to cache the target data to the device memory of the target heterogeneous acceleration device.

[0051] Among them, P2P stands for peer-to-peer network, that is, an end-to-end transmission method of database files. The data page (target data) of the target file can be directly transmitted end-to-end to the memory device of the heterogeneous acceleration device.

[0052] Specifically, in one embodiment, the host side can convert the virtual address into a physical address in the device memory of the heterogeneous acceleration card; determine the bus address based on the physical address, and use the bus address as the destination address; determine the file index information of the file to be accessed and the logical offset value of the target data in the file to be accessed based on the original data request; determine the source address and data length of the target data in the storage device based on the file index information of the file to be accessed and the logical offset value of the target data in the file to be accessed; generate a direct storage device access descriptor based on the destination address, the source address and the data length; and generate an accelerated computing request based on the direct storage device access descriptor, so that the target heterogeneous acceleration device responds to the accelerated computing request based on the direct storage device access engine.

[0053] It should be noted that the heterogeneous acceleration system provided in the embodiment of the present application adopts the x86 PCIe architecture. In this architecture, when the CPU executes a program instruction, it first issues a virtual address for memory read and write access, and then the memory management unit (Memory Management Unit, MMU for short) converts the virtual address into a physical address. The MMU maintains a mapping table between virtual addresses and physical addresses. The host sends the virtual address to the MMU, and the MMU searches and returns the corresponding physical address based on the internal mapping table. This physical address determines the actual storage location of the target data in the memory of the heterogeneous acceleration card device. If the data accessed by the physical address is in the Cache (cache memory), it is read directly from the Cache; if it is not in the Cache, the physical address is converted to a bus address through the Host Bridge in the Root Complex. The Host Bridge serves as a bridge between the CPU and the system bus and is responsible for converting the physical address into a bus address format. In the PCIe bus environment, Host Bridge converts the physical address into a bus address that meets the PCIe bus transmission requirements according to the PCIe bus protocol specification. This bus address is used for subsequent addressing of data transmission on the system bus to access the device memory space based on the bus address.

[0054] Specifically, after obtaining the bus address, the bus address is used as the destination address. The host side parses the original data request, extracts the relevant information of the file to be accessed, and determines the file index information of the file to be accessed and the logical offset value of the target data in the file to be accessed. For the file access request in the file system, the file index information includes the inode number (index number) of the file to be accessed, and the various attributes and storage location information of the file can be obtained in the file system metadata through the index number. The logical offset value indicates the relative position of the target data in the file. The host side searches for the corresponding file metadata in the file system based on the file index information of the file to be accessed. The source address of the target data on the storage device is determined through the file metadata and the logical offset value of the target data. Specifically, the distribution of the data blocks in the file to be accessed on the storage device can be determined based on the file index information, and then the starting address of the data block where the target data is located can be calculated based on the logical offset value, and it is used as the source address. At the same time, according to the data volume requirement in the original data request, the length of the target data to be read or operated is determined.

[0055] Specifically, after the host collects information such as the destination address (i.e., bus address), source address (address of the target data in the storage device), and data length, it generates a direct storage device access descriptor (DMA descriptor) in accordance with the format requirements of the direct storage device access protocol. The host integrates the direct storage device access descriptor with other relevant control information to generate an accelerated computing request. Relevant control information may include the type and priority of the computing task. The generated accelerated computing request is sent to the target heterogeneous acceleration device. After receiving the request, the target heterogeneous acceleration device parses the direct storage device access descriptor therein, and through the direct storage device access engine, reads the target data directly from the storage device based on the information in the descriptor, and then performs corresponding computing processing.

[0056] For example, taking the file name of the file to be accessed as "1.txt", the software execution method for reading the "1.txt" file from the disk SSD to the FPGA_DDR (device) is as follows: (1) The application layer obtains the virtual address (VA) of a buffer through the mmap function.

[0057] (2) The application layer initiates a read operation read(file, buffer, count) based on the above virtual address (VA).

[0058] (3) Call the vfs_read(buffer,file,offset,count) interface function at the kernel layer. vfs_read will pass in four important parameters: the virtual address VA of the cache (buffer), the file index (file_inode), the offset value of the file to be read (offset), and the number of bytes read (count). The number of bytes read is also called the data length. There are two main functions in the file system, namely, to complete the allocation of physical cache for the virtual address and to find the offset address of the target data on the disk in the file system.

[0059] (4) Based on the buffer (VA) parameter, the system call will further call the FPGA memory registration method to map the user-allocated virtual memory to the physical address of the FPGA memory. Then, get_user_page is called to obtain a page, and page_to_phys() is called to obtain the physical address PA value. Finally, the dma_map_single() function obtains the bus address BA value and fills BA into the destination address of the DMA descriptor.

[0060] (5) Based on the file parameter (file parameter), the file index inode is obtained at the file system layer, and then the inode information is saved to the system memory on the host side. ext4_get_block is called to obtain the physical block corresponding to the logical offset, and then blk_offset is finally obtained in combination with offset. blk_offset is used as the source address of the DMA descriptor; Count is used as the length of the DMA descriptor. At this point, several key parameters required by the function have been obtained.

[0061] (6) Finally, the DMA engine initiates P2P-DMA transmission to complete the data transfer.

[0062] Among them, the P2P-DMA driver is first loaded after the heterogeneous acceleration device is powered on, so that the user state can recognize this memory and then operate on this memory space. When the application executes the relevant code and encounters FPGA_DDR memory access, it will call the relevant interface function to realize direct access to the memory device.

[0063] The conversion process from virtual address to bus address can be realized by adding heterogeneous rapid device memory area nodes through host registration. The specific implementation process is as follows: (1) MMU performs VA->PA mapping to access heterogeneous acceleration devices. When a storage device requests memory, it needs to obtain the virtual address of the page in kernel state. Therefore, it is necessary to construct a mapping between the physical address and virtual address of the device memory in the driver. This operation is implemented by filling the kernel state MMU page table. The mapping is a fixed linear mapping. The kernel-related address conversion application programming interface (API) function such as virt_to_phy can directly realize the mapping between virtual addresses and physical addresses when performing linear address conversion.

[0064] (2) The OS layer (operating system layer) requires struct page to manage the memory of heterogeneous acceleration devices. In the Linux operating system, the memory subsystem describes the physical memory in the system through struct page, and applies for and releases the required memory pages through functions such as get_free_pages and kfree_pages. When the system is started, the memory subsystem has not yet created a struct page array for managing the FPGA physical memory. Through the devm_memremap_pages function, a page array is applied for and added to the device_zone of the memory subsystem. In the driver, a structpage array of the FPGA physical memory page is created as a device zone (DEVICE_ZONE) and added to the kernel zone. At the same time, a mapping between the physical address and virtual address of the kernel-mode device zone memory page is created to support the memory general address conversion function. When the disk device performs P2P transmission, it only needs to add the device zone mark when allocating the destination address memory page to allocate the physical page from the FPGA physical memory space, thereby realizing direct memory access from the disk to the device memory of the heterogeneous acceleration device in the software.

[0065] (3) The address space access mapped to the user-mode process by mmap is divided into two modes: user mode and kernel mode. When the process is in user mode, it can only access the memory area of ​​the user space. When it is in kernel mode, it is accessed through the kernel mode page table. Although the kernel mode can allocate the device's memory page table for access by adding the page array of the memory device to the kernel zone as the device_zon ​​and mapping the physical address to the virtual address, the user mode still cannot access the device memory. For this reason, in the Linux operating system, the memory subsystem uses mmap memory mapping technology to map the kernel mode memory to the user mode, so that the user process can also access the memory of the FPGA device.

[0066] Accordingly, in one embodiment, the target heterogeneous acceleration device sends an access start command to the storage device in response to the accelerated computing request, so that the storage device responds to the access start command, adopts a preset direct transfer mode, and moves the target data to the peer access space in the device memory according to the destination address; when the accelerated computing result is obtained, the accelerated computing result is written to the peer access space.

[0067] The access start command includes a DMA start command, and the peer access space in the device memory is exposed on the peer communication bus of the target heterogeneous acceleration device. The peer access space supports direct access between the host and the storage device.

[0068] Specifically, in the hardware implementation part, in order to implement CXL P2P DMA, the target heterogeneous acceleration device will expose a part of the local memory segment on the base address register space (Base Address Register, referred to as BAR). The CXL device (target heterogeneous acceleration device) exposes its control registers and internal memory blocks on the bus through BAR so that they can be accessed by other CXL devices (storage devices and host). BAR stores the bus address area (peer access space) where device registers and memory can be accessed. By exposing internal memory through BAR, the device can choose to expose its internal memory through BAR so that the CPU or other CXL devices can directly access this part of memory. The following details how to expose this relatively large memory space (peer access space) in FPGA logic.

[0069] The FPGA logic is implemented using the DMA basic function core, which has the following three functions: (1) Data to AXI Lite Master Interface: A control interface based on the AXI-Lite bus, which can be used to read and write registers of the IP core inside the accelerator card; (2) Data to DMA Interface: Data is moved between the host memory and the FPGA memory through DMA. This function is used in the DMA architecture (non-P2P). (3) Data to DMA Bypass Interface: Supports data transmission bypassing DMA Engine (Host DMABypass), which is the function used in the embodiment of the present application. Through this interface, it is connected to the DDR (device memory) on the FPGA side. DMA is initiated by the disk on the other end. The FPGA has the function related to PCIe protocol conversion. In order to enable the host side to access the DDR space on the FPGA acceleration card, the data after passing through the IP core is converted into an interface of the AXI-MM protocol, and the interface is directly connected to the memory controller IP (Mig) of the AXI-S interface. The host can then access the DDR on the FPGA side to read the accelerated calculation results.

[0070] Among them, Figure 4As shown, it is a structural diagram of the heterogeneous acceleration device provided in the embodiment of the present application. The CXL control module is the target protocol control module, which is an important interface module of the entire system and is connected to other components through specific lines. It is responsible for receiving instructions and data requests from the host, and passing relevant information from the host to the internal module. At the same time, it can also feed back the results or status information after internal processing of the FPGA to the host. It is the key hub for the entire system to communicate and interact with the external host, ensuring the accurate transmission and interaction of data and instructions between the host and the FPGA system. The heterogeneous acceleration device completes protocol parsing, response, and related control operations in the CXL control module. At the same time, the module is also extended to connect to the CXL control modules in each FPGA in the FPGA cluster, and the cache consistency between the FPGA and the CPU is ensured through the CXL protocol.

[0071] DMA (Direct Memory Access) is used to achieve direct data transfer between different storage areas without frequent CPU intervention, which greatly improves the efficiency of data transfer. Data can be transferred directly from the host memory to the FPGA device memory, or data can be quickly moved between different memory areas inside the FPGA. The DMA Bypass and other symbols in the figure indicate that it may support multiple data transfer modes to adapt to different application scenarios and data transfer requirements. In some cases with high real-time requirements, specific DMA modes can be used to optimize the data transfer path and reduce latency.

[0072] The bus cross-switch module connects multiple modules in the system, such as DMA, memory controller, control management module, and accelerated computing module. According to the system requirements and the current task status, the bus connection between each module is dynamically switched to ensure that data can be transmitted to the corresponding module at the right time and through the right path, avoiding data transmission conflicts and improving the overall performance and resource utilization of the system. By properly configuring the bus connection, it can optimize the flow of data in the system. When the accelerated computing module needs to read a large amount of data from the memory, the bus cross-switch can quickly establish a direct data channel from the memory controller to the accelerated computing module, reducing the intermediate links of data transmission and increasing the data transmission speed.

[0073] The control management module is responsible for the global control and coordination of the entire FPGA system. It receives instructions from the host and the status information of each module in the system, and formulates the system's operation strategy and task scheduling plan based on this information. When the host sends an accelerated computing request, the control management module reasonably allocates resources and schedules each module to work together according to the current system resource usage, such as free space in the memory, load of the accelerated computing module, etc., to ensure that the task can be executed efficiently and orderly. Real-time monitoring of the working status of each module in the system, including whether the module is running normally, whether there are errors or abnormal conditions, etc. Once a problem is found, take appropriate measures to deal with it in a timely manner, such as restarting the faulty module, adjusting task allocation, etc., to ensure the stability and reliability of the system. The functional acceleration module includes multiple acceleration units for performing accelerated computing tasks, which significantly improves the computing speed and efficiency by quickly processing the input data.

[0074] The memory controller is responsible for managing the FPGA device memory, including operations such as memory allocation, recycling, and address mapping. When the system needs to use memory to store data or programs, the memory controller allocates the corresponding memory space according to the request and records the memory usage for subsequent management and recycling. At the same time, it is also responsible for converting virtual addresses into physical addresses to ensure that data can be accurately stored and read to the correct location of the memory. Control the read and write operations of data in the memory, and work with the bus cross switch and other modules to ensure that data can be written to or read from the memory quickly and accurately. For example, when the accelerated computing module needs to read data in the memory for calculation, the memory controller will read the corresponding data from the memory and transmit it to the accelerated computing module according to the scheduling of the bus cross switch; when the calculation results need to be stored in the memory, the memory controller will write the results to the specified memory location.

[0075] FPGA device memory is a storage area inside the FPGA, which is used to store various data required during the operation of the system, including input data (target data), intermediate calculation results, and final output results (accelerated calculation results). For example, in a data processing task, the data transmitted from the host side will first be stored in the FPGA device memory for the accelerated calculation module to read and process; the intermediate results generated by the accelerated calculation module during the calculation process will also be temporarily stored here until the calculation is completed, and the final results will also be stored in the memory, waiting for the host side to read or further process. In some cases, the FPGA device memory can also act as a cache, caching some frequently used data or calculation results to reduce the number of accesses to external storage devices (such as solid state drives (SSDs)) and improve the overall performance of the system. For example, for some repeatedly used intermediate calculation results, storing them in the FPGA device memory can avoid repeated calculations and speed up the processing of subsequent tasks.

[0076] Specifically, after passing through the CXL control module, the valid data (target data) is transmitted by direct memory access (DMA) through the DMA module that supports the internal Advanced eXtensible Interface (AXI) bus. Since the AXI bus has a master-slave mode, M in the figure represents the master mode interface and S represents the slave mode interface. The memory, accelerated computing module, and control management module are interconnected through a bus cross switch.

[0077] Accordingly, in one embodiment, the host receives an interrupt signal fed back by the target heterogeneous acceleration device when obtaining the accelerated computing result, and in response to the interrupt signal, directly accesses the peer access space of the target heterogeneous acceleration device to obtain the accelerated computing result.

[0078] Specifically, the embodiment of the present application sets up a CXL Bar space (peer access space) in the device memory for P2P transmission. Starting from address 0, the memory space to 8G is accessible to the host or SSD, and no address conversion is required in the FPGA. When the host side constructs the DMA descriptor, it only needs to map the address of the FPGA-DDR to the corresponding address space. After receiving the DMA start command, the storage device SSD uses its DMA engine to move the data to the FPGA-DDR. Other acceleration IP cores inside the FPGA can read the data to be calculated (target data) from the same address space and complete the acceleration. After the calculation is completed, the host side is notified through an interrupt, that is, the interrupt signal is fed back to the host side. The host side responds to the interrupt signal and notifies the FPGA to initiate a DMA operation, and the calculated results are directly moved to the host memory. It can also notify the DMA engine of the SSD to move the target data and the accelerated calculation results back to the SSD for storage. So far, through the above-mentioned software and hardware design, the end-to-end DMA transmission of files from the SSD to the FPGA_DDR is realized.

[0079] Based on the above embodiments, Figure 5 A structural diagram of another heterogeneous acceleration system provided for an embodiment of the present application, as an implementable method, in one embodiment, a storage device is used to use the target data read by the target heterogeneous acceleration device as the original data that meets the current query conditions, and transmit the original data to the file cache system on the host side.

[0080] The accelerated calculation results include the current query condition information. Figure 5 The heterogeneous acceleration system shown adopts an architecture mode that combines CPU and FPGA heterogeneous device clusters. Multiple FPGA clusters are connected to storage devices and CPU hosts through switching chips that support the CXL heterogeneous cache consistency protocol. Inside the FPGA cluster, each component is interconnected in a fully connected manner, and the number of FPGAs can be flexibly configured according to actual needs. Figure 5 Take a cluster consisting of four FPGAs (heterogeneous acceleration cluster) as an example. In terms of data transmission, the P2P (storage to heterogeneous acceleration device) direct transmission mode is used, and the application controls the data to be directly transmitted from the storage device to the FPGA cluster.

[0081] Specifically, in one embodiment, heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate with each other in a fully connected manner, and heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate with each other through a target protocol switch.

[0082] Specifically, the CPU host runs database software, which is responsible for receiving user query requests and data operation instructions, processing and analyzing data, and returning the results to users or other applications. The database software interacts with the database enhanced file system layer through the host interface to transfer data and instructions. The database enhanced file system layer reads and writes files through the Portable Operating System Interface (POSIX) file system interface. The database enhanced file system layer includes a file cache system for storing original data provided by storage devices such as disks. The device data cache and computing unit management are responsible for managing the data cache of devices (such as FPGA accelerator cards) and coordinating the work of computing units (computing modules in FPGAs) to ensure efficient transmission and processing of data between devices and hosts. The database enhanced file system layer links to the original file system layer. The original file system layer includes a file system interface and a metadata management module. The file system interface provides the underlying file system operation interface and is responsible for interacting with the actual storage device to implement basic operations such as file storage, reading, and writing. The metadata management module is responsible for managing the metadata of files, such as the name, size, creation time, modification time, access rights, and other information of the file, to ensure that the file system can accurately locate and manage files. The host side is connected to the storage device and heterogeneous acceleration cluster through the file system interface through the CXL switch chip (target protocol switch) to achieve data storage and reading.

[0083] Among them, the CXL switch chip (CXL switch) serves as the data exchange hub in the system, connecting the host, storage devices and multiple FPGA acceleration cards (heterogeneous acceleration cards) to achieve high-speed data transmission and exchange between them. CXL is a high-speed interconnect technology that can provide a high-bandwidth, low-latency data transmission channel to meet the requirements of data transmission performance in heterogeneous acceleration systems. It is connected to the original file system, storage devices and multiple FPGA acceleration cards on the host side to form a data transmission network to ensure efficient data communication between various components.

[0084] Specifically, after obtaining the accelerated calculation results and the original data, the host side can perform corresponding analysis on the original data based on the current query condition information in the accelerated calculation results, such as verifying the accuracy of the accelerated results.

[0085] On the basis of the above embodiments, as an implementable method, in one embodiment, the host side is used to obtain a global heterogeneous acceleration status table; wherein the global heterogeneous acceleration configuration table includes the global location information, acceleration unit function, current usage, instruction type, current task execution information and current resource occupancy information of each acceleration unit, and each heterogeneous acceleration device includes multiple acceleration units; according to the accelerated computing requirements represented by the accelerated computing request, the selected heterogeneous acceleration devices whose acceleration unit functions match the accelerated computing requirements are screened in the global heterogeneous acceleration status table; according to the global heterogeneous acceleration status table, the target heterogeneous acceleration device is screened among the selected heterogeneous acceleration devices to send the accelerated computing request to the target heterogeneous acceleration device.

[0086] Among them, an exemplary global heterogeneous acceleration state table 1 is as follows: Table 1

[0087] Among them, the acceleration unit coordinates are the global position information, the current task execution information includes the assigned task ID / execution sequence number, the assigned task ID is the unique identifier of the currently executed task, the execution sequence number indicates which subtask is currently being executed in the currently executed task, and the currently executed task is composed of multiple subtasks. The resource allocation status on the card is the current resource occupancy information.

[0088] Specifically, the host side calculates a comprehensive load index for each candidate heterogeneous acceleration device according to its current usage, current task execution information and current resource occupancy information. This index can be a weighted average, taking into account factors such as the busyness of the device and the remaining resources. For example, the busyness of the device can be weighted according to the number of tasks being processed and the complexity of the tasks, and the remaining resources are weighted according to the free space of the memory, the idle ratio of computing resources, etc. In order to obtain the comprehensive load index of each candidate acceleration unit in the candidate heterogeneous acceleration device, finally according to the preset load balancing strategy, the target acceleration unit is selected from these candidate acceleration units, and then the candidate heterogeneous acceleration device containing the target acceleration unit is used as the target heterogeneous acceleration device. So that the system can allocate computing tasks more intelligently, make full use of the resources of heterogeneous acceleration devices, improve the overall performance and efficiency of the system, and ensure the timely processing of tasks and the stable operation of the system.

[0089] Specifically, in one embodiment, the host side can analyze the task execution characteristics of the accelerated computing request to obtain the task execution characteristic information of the accelerated computing request; when the task execution characteristic information indicates that the task execution mode of the accelerated computing request is a sequential mode, a number of target acceleration units are selected from the candidate heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster; and the candidate heterogeneous acceleration device including the target acceleration unit is used as the target heterogeneous acceleration device.

[0090] It should be noted that in the heterogeneous acceleration system provided in the embodiment of the present application, the heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate with each other in a fully connected manner, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate with each other through a target protocol switch. In the case where the task execution mode of the accelerated computing request is a sequential mode, since in the sequential mode, the acceleration unit executed later needs to use the intermediate result obtained by the acceleration unit executed before as input, in order to reduce the delay in the transmission of the intermediate result between the acceleration units, the embodiment of the present application will select several target acceleration units from the candidate heterogeneous acceleration devices in the same heterogeneous acceleration cluster to avoid cross-cluster communication during the task execution process, so as to further improve the efficiency of heterogeneous acceleration.

[0091] Accordingly, in one embodiment, when the task execution characteristic information indicates that the task execution mode of the accelerated computing request is a disordered mode, the host side may select several target acceleration units whose remaining computing resources meet preset screening conditions in the candidate heterogeneous acceleration devices; and use the candidate heterogeneous acceleration device including the target acceleration unit as the target heterogeneous acceleration device.

[0092] It should be noted that when the task execution mode of the accelerated computing request is the out-of-order mode, since each target acceleration unit runs independently during the execution of the tasks to be executed in the out-of-order mode and does not need to interact, several target acceleration units whose remaining computing resources meet the preset screening conditions can be screened from the selected heterogeneous acceleration devices, and then the selected heterogeneous acceleration device including the target acceleration unit can be used as the target heterogeneous acceleration device.

[0093] Specifically, in practical applications, several acceleration units with the most remaining computing resources may be used as several target acceleration units whose remaining computing resources meet preset screening conditions.

[0094] Specifically, in one embodiment, the host side can also be used to generate a target token for a target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address starting address, a data length, a read / write permission bit, a unique identifier of the heterogeneous acceleration device, a unique identifier of the acceleration unit, and a target priority; according to the unique identifier of the heterogeneous acceleration device, the target token is sent to the corresponding target heterogeneous acceleration device, so that the target heterogeneous acceleration device executes the heterogeneous acceleration task to be executed based on the target token, so as to perform corresponding calculation processing on the target data and obtain an accelerated calculation result.

[0095] It should be noted that the heterogeneous acceleration system provided in the embodiment of the present application is in a multi-card environment in a heterogeneous acceleration cluster. The target token is a mechanism for coordinating and controlling resource access and task execution order between multiple FPGA cards. It is similar to a permission identifier. Only the FPGA card (target heterogeneous acceleration device) that obtains the target token can perform specific operations or access shared resources, thereby avoiding conflicts and disordered competition between multiple cards. Among them, shared resources include device memory.

[0096] Among them, Figure 6 As shown, it is a schematic diagram of the structure of the target token provided in the embodiment of the present application. The target token includes a valid bit (1 bit), a physical address start address (64 bits), a data length (16 bits), a read and write permission bit (1 bit), a unique identifier of a heterogeneous acceleration device (8 bits), a unique identifier of an acceleration unit (16 bits), and a target priority (8 bits). The unique identifier of a heterogeneous acceleration device is the FPGA number, and the unique identifier of an acceleration unit is the acceleration unit ID.

[0097] Accordingly, in one embodiment, the target heterogeneous acceleration device is used to receive a target token sent by the host; when the valid bit of the target token indicates that the token is currently valid, the target acceleration unit of the heterogeneous acceleration task to be executed and the task type of the heterogeneous acceleration task to be executed are determined according to the unique identifier of the acceleration unit in the target token; the permission range of the target acceleration unit is determined according to the physical address starting address, data length and read and write permission bits in the target token; wherein the permission range includes a target read and write range of the device memory; and the execution priority of the target acceleration unit is determined according to the target priority in the target token.

[0098] Specifically, when an FPGA card obtains a target token, it first checks the scope of permissions corresponding to the token. The token specifies the storage area that the card can access and the types of tasks that can be executed (such as full table scan module, sorting module, regular expression module, hash connection module, etc.). According to the permissions granted by the target token, the FPGA card loads the corresponding target data from the local memory (device memory) (if the task data is not yet ready, it needs to wait for the data transfer to be completed) and processes the target data according to the predetermined task logic. During the processing, the validity of the token is continuously monitored, because the control management module on the card will decide to recycle the token in advance and reallocate it according to the global situation. Once the task is completed, the FPGA card will perform the corresponding subsequent operations according to the system requirements, store the execution results to the specified location, and then return the target token to the control management module.

[0099] In the field of database acceleration, when multiple FPGA cards are used to process large-scale data, token execution can reasonably allocate access rights to each card for acceleration units and input data, ensuring that each card performs calculations in the correct order and with the correct permissions, avoiding data conflicts and repeated calculations, and also avoiding performance degradation or system crashes caused by resource competition. The FPGA multi-card token execution method provides effective resource coordination and task execution guarantees for multi-card FPGA systems in various application scenarios through reasonable token generation, allocation, and token-based task execution processes, thereby improving system performance and stability.

[0100] Accordingly, in one embodiment, the host side is used to obtain the number of waiting cycles of each acceleration unit to be selected in the heterogeneous acceleration device to be selected; determine the time priority of the acceleration unit to be selected according to the number of waiting cycles of the acceleration unit to be selected; obtain the task priority of the heterogeneous acceleration task to be executed corresponding to the acceleration unit to be selected; and determine the target priority according to the time priority and task priority of the acceleration unit to be selected.

[0101] Specifically, for the determination rule of target priority, the rule includes a time interval rotation allocation strategy and a task priority allocation strategy. The time level is represented by 8 bits, and waiting for a time period accumulates 1 (the upper four bits represent the waiting level 0-15 levels), and the weight is set to 25%; the task priority is set to 0-15 levels, the larger the number, the higher the priority, and the weight is set to 75%. The task priority is set according to the user's execution requirements for the task to be executed, and the embodiment of this application is not limited. Finally, the target priority is determined according to the time priority and task priority of the selected acceleration unit, and the target token is calculated and distributed to the heterogeneous acceleration device to which the selected acceleration unit belongs with the highest score. Global coordination and management are achieved through tokens, and precise control can be performed according to predetermined strategies.

[0102] The embodiment of the present application proposes a token method to coordinate each card to perform different tasks according to specific task processes and priorities. The FPGA group in the cluster can configure the core acceleration function IP (acceleration unit) according to needs, such as data filtering, full table scanning, regular expressions, sorting, hash connection, etc., and also covers the management module of the computing unit in the FPGA. The system can adapt to the new system scale, increase or decrease the number of FPGA cards, and maintain stable operation of the system by appropriately adjusting the token generation and allocation mechanism.

[0103] On the basis of the above embodiments, as an implementable method, in one embodiment, a target communication interface is provided between the host side and each heterogeneous acceleration device, the accelerated computing request includes a database query statement, and the target communication interface is used to perform semantic analysis on the database query statement to obtain a semantic analysis result; according to the semantic analysis result, a target action instruction is extracted from the database query statement; according to the target action instruction, the database query statement is converted into a general statement of the heterogeneous acceleration device, so as to input the general statement of the heterogeneous acceleration device into the target heterogeneous acceleration device.

[0104] The target action instructions include at least data query instructions, data insertion instructions, data update instructions and data deletion instructions.

[0105] It should be noted that database query statements are usually generated by users or applications to obtain and operate data from the database. Database query statements have different grammatical structures and expressions, and directly sending them to heterogeneous acceleration devices may not be correctly understood and executed.

[0106] Specifically, the target communication interface uses relevant semantic analysis techniques and algorithms to parse database query statements to analyze keywords, operators, table names, field names and other elements in the statements, determine the database operation type, data range, conditions and other information involved in the statements, and obtain semantic analysis results. Based on the semantic analysis results, the corresponding target action instructions are accurately extracted from the database query statements.

[0107] Specifically, heterogeneous acceleration devices generally have their own specific instruction sets and data processing methods, which may be incompatible with the database query statements sent by the host. Therefore, the database query statements are converted into common statements for heterogeneous acceleration devices so that the heterogeneous acceleration devices can understand and execute them. Statement conversion involves the adjustment of grammatical structure, conversion of data formats, mapping of operators, etc. For example, certain functions or operators in database query statements can be converted into equivalent forms that can be recognized and executed by heterogeneous acceleration devices, while ensuring that the converted statements can accurately implement the functions and intentions of the original statements.

[0108] Specifically, the target communication interface is located between the host software and the FPGA hardware, and is responsible for defining clear interaction rules and data formats. On the one hand, it receives operation requests from the host database application, and on the other hand, it sends the converted FPGA-understandable instructions (common statements for heterogeneous acceleration devices) to the FPGA hardware, and receives the results and original data processed by the FPGA and feeds them back to the host software.

[0109] Among them, the instruction conversion module is one of the core parts of the target communication interface, which is responsible for parsing various query statements (such as SQL statements) and operation instructions (such as insert, delete, update, etc.) from the host database, and converting them into specific format instructions that the FPGA can understand according to predefined mapping rules (corresponding processing of the instruction parsing module in the FPGA). The embodiment of the present application uses a custom binary format for data encapsulation. For database query statements, they are split and encoded according to specific fields. The keywords (SELECT, FROM, WHERE, etc.), table names, column names, conditional values, etc. in the SQL statement are represented by 8-bit binary codes, and combined into a complete query instruction in a certain order and sent to the FPGA. For the returned results, the FPGA is also encapsulated in the specified format, and information such as row identifiers and result status identifiers are added so that the host software can accurately parse them. Among them, the current query condition information includes a row identifier and a result status identifier, and the result status identifier represents whether the query is hit.

[0110] The details are as follows: Instructions are defined for operations such as data query (SELECT), data insertion (INSERT), data update (UPDATE), and data deletion (DELETE). The operation code is represented by 2 bits, with the SELECT format being "00", the INSERT format being "01", the UPDATE format being "10", and the DELETE format being "11".

[0111] The format of the data query instruction includes the operation code "00" (indicating a query operation), the table identifier (16 bits, 8 bits representing the database table to be queried, and 8 bits representing the connected database table), the column identifier (8-bit digital representation, corresponding to the column number), the condition judgment and filtering keywords (WHERE corresponds to "00" to specify the filtering conditions; GROUP BY corresponds to "01" to indicate grouped queries; ORDER BY corresponds to "10" to indicate sorting the query results; HAVING corresponds to "11" to indicate further filtering the grouped results after the grouping operation), the condition expression value (used to specify the query conditions) and the additional field identifier (COUNT corresponds to "0000", SUM corresponds to "0001", AVG corresponds to "0010", MIN corresponds to "0011", and MAX corresponds to "0100"), etc. After receiving such an instruction, the FPGA can clearly know the specific query task to be executed.

[0112] Data insertion instruction: Its format includes the operation code "01" (indicating an insert operation), table identifier (8 bits representing the corresponding database table to be queried), column identifier (8 bits representing the corresponding column number), and column value (64 bits representing the corresponding numerical value).

[0113] Data update instruction: Its format includes the operation code "10" (indicating an update operation), table identifier (8 bits, 8 bits representing the corresponding database table to be queried), column identifier (8 bits representing the corresponding column number), column value (64 bits representing the corresponding numerical value), condition judgment and filtering keywords (WHERE corresponds to "00" to specify the filtering conditions), and condition expression value (used to specify the query conditions).

[0114] Data deletion instruction: Its format includes the operation code "11" (indicating a delete operation), table identifier (8 bits, 8 bits representing the corresponding database table to be queried), condition judgment and filtering keywords (WHERE corresponds to "00" to specify the filtering conditions): condition expression value (used to specify the query conditions).

[0115] Furthermore, after the target heterogeneous acceleration device completes the accelerated calculation, the calculation results are fed back to the host by the FPGA in the FPGA cluster connected to the host. The calculation results include the location information of the data that meets the query conditions, such as page number, row number, etc. On the host side, the original data page where the row data that meets the query conditions is located is transmitted from the storage device to the host side through the traditional transmission path to be used as a data cache. The converted, FPGA-understandable instructions are sent to the FPGA hardware through a custom callback module. After the acceleration is completed, the calculation results are returned to the callback module for processing, thereby realizing customized control of the interaction process between the database and the FPGA.

[0116] For the heterogeneous acceleration system provided in the embodiment of the present application, the communication between the storage device, the host side and the heterogeneous acceleration device adopts the CXL protocol, and a new data transmission mode is constructed based on the unified memory addressing and direct access characteristics of the CXL technology. In this mode, byte-granular data access with cache consistency can be ensured. Traditional data transmission usually goes through multiple levels of caching, copying, and complex bus transmission protocol conversion. The process is not only cumbersome, but also prone to data delays and inconsistency problems. The CXL technology directly breaks this barrier and establishes a direct channel between the data source and the target storage through a peer-to-end transmission method.

[0117] From the perspective of database file transfer, in the past, data had to be transferred multiple times in the file system cache, application layer pages, etc., and then transferred to heterogeneous acceleration devices through DMA and other methods. This process involves many links, each of which may introduce delays and consume a lot of system resources. Using the peer-to-peer end-to-end transmission achieved by CXL technology, database files can be directly transferred from the storage source to the acceleration card memory and host memory, skipping unnecessary intermediate transfer links.

[0118] In terms of byte-granularity data access to ensure cache consistency, CXL allows the CPU to operate on both host memory and accelerator card memory as if in a unified memory space. This means that data interaction between different devices does not require complex data format conversion and synchronization operations, greatly improving data processing efficiency. At the same time, the advantage of greatly reducing access paths directly leads to reduced latency. Data does not need to be transmitted in a roundabout way between multiple levels of cache and devices, but flows directly along the optimized end-to-end path, thereby meeting the needs of modern database systems for efficient data processing and low-latency response. This method opens up a new path for data transmission under heterogeneous computing architectures, and is expected to play an important role in database management, big data processing and other fields, and improve the performance and reliability of the overall system.

[0119] The system provided in the embodiment of the present application supports hardware acceleration modules for more computationally intensive operations. Due to the limitation of FPGA resources, the fixed-mode micro-architecture used in the related art will result in low performance and resource utilization in different application scenarios of the database. In the field of heterogeneous computing, resource pooling technology provides a new idea for improving performance. This configurable architecture can adapt to diversified application requirements. When facing different data processing scenarios, efficient use of resources can be achieved by flexibly adjusting the configuration of the acceleration function in the FPGA.

[0120] The embodiment of the present application proposes a system that supports multi-FPGA database acceleration, aiming to significantly improve database performance by using multiple field programmable gate arrays (FPGAs). The specific method is to cluster the FPGAs and use token pipelining within the cluster to achieve pooling of acceleration modules. In the data processing flow, clustered FPGAs work together. For example, in the data filtering link, a reasonably configured FPGA can quickly filter out qualified data and reduce unnecessary data transmission and processing. The token pipelining mode ensures the orderly processing of data within the cluster and improves processing efficiency.

[0121] By pooling the acceleration modules, each FPGA can be flexibly optimized and configured according to different database application scenarios to improve overall performance. In different scenarios, such as in transaction databases with high requirements for data encryption and decryption, sorting and aggregation operations are also more frequent when processing order data. The configurable FPGA acceleration architecture can reasonably allocate FPGA resources according to the characteristics of these scenarios, with one part used for encryption and decryption and the other part for operations such as sorting and aggregation, thereby improving the performance of the entire database system in this scenario and meeting business needs.

[0122] The heterogeneous acceleration system provided by the embodiment of the present application includes: a host end, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, wherein the heterogeneous acceleration cluster includes a plurality of heterogeneous acceleration devices; the host end is used to send an accelerated computing request to the heterogeneous acceleration cluster; any target heterogeneous acceleration device in the heterogeneous acceleration cluster is used to respond to the accelerated computing request in the case of receiving the accelerated computing request, adopt a preset direct transmission mode, directly read the target data from the storage device, and perform corresponding calculation processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device; the host end is used to directly access the target cache device to obtain the accelerated computing result. In the system provided by the above scheme, the target heterogeneous acceleration device can directly obtain the target data from the storage device by direct data transmission, so that the database file page can be directly transferred from the disk to the FPGA without forwarding through the CPU, which greatly shortens the transmission path of the target data and reduces the time consumption of the target data during the transmission process, thereby reducing the data transmission delay of the target heterogeneous acceleration device, and laying a foundation for improving the performance of the computing device. In addition, by connecting with the host and the storage device through the CXL Switch, the consistency and scalability of the data on the heterogeneous device are guaranteed. Inside the FPGA cluster, each component is interconnected in a fully connected manner, which reduces the communication delay within the cluster, and the number of FPGAs in the cluster can be flexibly configured according to actual needs. In addition, the control method adopts a token method to coordinate each card to perform different tasks according to specific task processes and priorities, so that the FPGA group in the cluster can configure different core acceleration IPs according to needs. In addition, clear interaction rules and data formats are defined, and operation requests from host database applications are received. After conversion, they are converted into FPGA-understandable instructions and sent to the FPGA hardware, and the calculation results after FPGA processing are fed back to the host system through the FPGA cluster. The original data page (original data) where the row data that meets the conditions is located is directly transmitted back to the host side through the storage device to be used as a data cache.

[0123] The embodiment of the present application provides a heterogeneous acceleration method for reducing the data transmission delay from target data to a heterogeneous acceleration device when accelerating a host computing task based on a heterogeneous acceleration device. The execution subject of the embodiment of the present application is the host end in the heterogeneous acceleration system provided in the above embodiment.

[0124] like Figure 7 FIG. 1 is a flow chart of a heterogeneous acceleration method provided in an embodiment of the present application, the method comprising: Step 701, sending an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read the target data from the storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode, the storage device is used to store the target data, and perform corresponding computing processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device.

[0125] Step 702: When it is determined that the heterogeneous acceleration device has written the accelerated computing result into the target cache device, directly access the target cache device to obtain the accelerated computing result.

[0126] Regarding the heterogeneous acceleration method in this embodiment, the specific implementation of each step has been described in detail in the embodiment of the heterogeneous acceleration system, and will not be elaborated here.

[0127] The heterogeneous acceleration method provided in the embodiment of the present application is applied to the host side in the heterogeneous acceleration system provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0128] The embodiment of the present application provides a heterogeneous acceleration method for reducing the data transmission delay from target data to a heterogeneous acceleration device when accelerating a computing task on a host side based on a heterogeneous acceleration device. The subject of the embodiment of the present application is a target heterogeneous acceleration device in the heterogeneous acceleration system provided in the above embodiment.

[0129] like Figure 8 FIG. 1 is a flow chart of another heterogeneous acceleration method provided in an embodiment of the present application, the method comprising: Step 801, receiving an accelerated computing request sent by a host.

[0130] Step 802, in response to the accelerated computing request, adopt a preset direct transmission mode to directly read the target data from the storage device; wherein the storage device is used to store the target data.

[0131] Step 803, perform corresponding calculation processing on the target data to obtain an accelerated calculation result, and write the accelerated calculation result into the target cache device.

[0132] Step 804: Send an interrupt request to the host side to instruct the host side to directly access the target cache device so that the host side can obtain the accelerated calculation result.

[0133] Regarding the heterogeneous acceleration method in this embodiment, the specific implementation of each step has been described in detail in the embodiment of the heterogeneous acceleration system, and will not be elaborated here.

[0134] The heterogeneous acceleration method provided in the embodiment of the present application is applied to the target heterogeneous acceleration device in the heterogeneous acceleration system provided in the above embodiment. The implementation method and principle are the same and will not be repeated here.

[0135] An embodiment of the present application provides a heterogeneous acceleration device for executing the heterogeneous acceleration method provided in the above embodiment.

[0136] like Fig. 9 , which is a schematic diagram of the structure of a heterogeneous acceleration device provided in an embodiment of the present application. The heterogeneous acceleration device 90 includes: a request acceleration module 901 and a reading module 902 .

[0137] Among them, the request acceleration module is used to send an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read the target data from the storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode. The storage device is used to store the target data and perform corresponding calculation processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device; the reading module is used to directly access the target cache device to obtain the accelerated computing result when it is determined that the heterogeneous acceleration device has written the accelerated computing result to the target cache device.

[0138] Regarding the heterogeneous acceleration device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0139] The heterogeneous acceleration device provided in the embodiment of the present application is used to execute the heterogeneous acceleration method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0140] An embodiment of the present application provides a heterogeneous acceleration device for executing the heterogeneous acceleration method provided in the above embodiment.

[0141] like Fig.10 , which is a schematic diagram of the structure of another heterogeneous acceleration device provided in an embodiment of the present application. The heterogeneous acceleration device 100 comprises: a receiving module 1001 , a data reading module 1002 , an accelerated calculation module 1003 and a sending module 1004 .

[0142] Among them, the receiving module is used to receive the accelerated computing request sent by the host side; the data reading module is used to respond to the accelerated computing request and adopt a preset direct transmission mode to directly read the target data from the storage device; wherein the storage device is used to store the target data; the accelerated computing module is used to perform corresponding calculation processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device; the sending module is used to send an interrupt request to the host side to instruct the host side to directly access the target cache device so that the host side can obtain the accelerated computing result.

[0143] Regarding the heterogeneous acceleration device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0144] The heterogeneous acceleration device provided in the embodiment of the present application is used to execute the heterogeneous acceleration method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0145] An embodiment of the present application provides a computing device for deploying the heterogeneous acceleration system provided by the above embodiment.

[0146] like Fig.11 FIG. 1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. The computing device includes: a heterogeneous acceleration system provided in the above embodiment.

[0147] The computing device may be a server or the like.

[0148] The electronic device provided in the embodiment of the present application is used to deploy the heterogeneous acceleration system provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0149] An embodiment of the present application provides a non-volatile computer-readable storage medium, in which computer execution instructions are stored. When a processor executes the computer execution instructions, the heterogeneous acceleration method provided in any of the above embodiments is implemented.

[0150] The storage medium containing computer executable instructions provided in the embodiments of the present application can be used to store computer executable instructions of the heterogeneous acceleration method provided in the aforementioned embodiments. The implementation method and principle are the same and will not be repeated here.

[0151] An embodiment of the present application provides a computer program product, including computer instructions, which are used to enable a computer to execute the heterogeneous acceleration method provided in the aforementioned embodiment.

[0152] The embodiments of the present application provide a computer program product that can be used to execute computer instructions of the heterogeneous acceleration method provided in the aforementioned embodiments. The implementation method and principle are the same and will not be repeated here.

[0153] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0154] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0156] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0157] A part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0158] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0159] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some or all of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A heterogeneous acceleration system, characterized in that: include: A host side, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, wherein the heterogeneous acceleration cluster includes a plurality of heterogeneous acceleration devices; The host end is used to send an accelerated computing request to the heterogeneous acceleration cluster; Any target heterogeneous acceleration device in the heterogeneous acceleration cluster is used to, upon receiving the accelerated computing request, respond to the accelerated computing request, adopt a preset direct transmission mode, directly read the target data from the storage device, perform corresponding computing processing on the target data, obtain an accelerated computing result, and write the accelerated computing result into a target cache device; The host end is used to directly access the target cache device to obtain the accelerated calculation result.

2. The system according to claim 1, characterized in that The target heterogeneous acceleration device includes: A target protocol control module, configured to receive the accelerated computing request sent by the host; wherein the target cache device includes a device memory of a target heterogeneous acceleration device, and the host directly accesses the device memory through the target protocol control module to maintain cache consistency between the host and the target heterogeneous acceleration device; The target protocol control module is connected to a target protocol switch so that the target heterogeneous acceleration device communicates with the host end and the storage device through the target protocol switch.

3. The system according to claim 1, characterized in that The host side is used for: Get the raw data request entered by the user; In response to the original data request, allocating a virtual address of the target data on the target heterogeneous acceleration device; Determining configuration parameters of the accelerated computing request according to the virtual address and the original data request; An accelerated computing request is generated according to the configuration parameters of the accelerated computing request, and the accelerated computing request is sent to the target heterogeneous acceleration device.

4. The system according to claim 3, characterized in that The host side is used for: Convert the virtual address into a physical address in the device memory of the heterogeneous accelerator card; Determine a bus address according to the physical address, and use the bus address as the destination address; Determine, according to the original data request, file index information of the file to be accessed and a logical offset value of the target data in the file to be accessed; Determine the source address and data length of the target data in the storage device according to the file index information of the file to be accessed and the logical offset value of the target data in the file to be accessed; Generate a direct storage device access descriptor according to the destination address, source address and data length; Based on the direct storage device access descriptor, an accelerated computing request is generated, so that the target heterogeneous acceleration device responds to the accelerated computing request based on a direct storage device access engine.

5. The system according to claim 4, characterized in that The target cache device includes a device memory of a target heterogeneous acceleration device, and the target heterogeneous acceleration device is used to: In response to the accelerated computing request, sending an access start command to the storage device, so that the storage device responds to the access start command and adopts a preset direct transfer mode to move the target data to the peer access space in the device memory according to the destination address; When the accelerated calculation result is obtained, writing the accelerated calculation result into the peer access space; The peer access space in the device memory is exposed on the peer communication bus of the target heterogeneous acceleration device, and the peer access space supports direct access between the host and the storage device.

6. The system according to claim 5, characterized in that The host side is used for: An interrupt signal fed back by the target heterogeneous acceleration device when the accelerated computing result is obtained is received, and in response to the interrupt signal, a peer access space of the target heterogeneous acceleration device is directly accessed to obtain the accelerated computing result.

7. The system according to claim 1, characterized in that The storage device is used for: The target data read by the target heterogeneous acceleration device is used as original data that meets the current query condition, and the original data is transmitted to the file cache system of the host end; Wherein, the accelerated calculation result includes current query condition information.

8. The system according to claim 1, characterized in that The heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate with each other in a fully connected manner, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate with each other through a target protocol switch.

9. The system according to claim 1, characterized in that The host side is used for: Obtaining a global heterogeneous acceleration status table; wherein the global heterogeneous acceleration configuration table includes global location information, acceleration unit function, current usage, instruction type, current task execution information and current resource occupancy information of each acceleration unit, and each of the heterogeneous acceleration devices includes multiple acceleration units; According to the accelerated computing requirement represented by the accelerated computing request, screening in the global heterogeneous acceleration state table a candidate heterogeneous acceleration device whose acceleration unit function matches the accelerated computing requirement; According to the global heterogeneous acceleration state table, a target heterogeneous acceleration device is screened from the candidate heterogeneous acceleration devices to send the accelerated computing request to the target heterogeneous acceleration device.

10. The system according to claim 9, characterized in that The host side is used for: Analyzing the task execution characteristics of the accelerated computing request to obtain the task execution characteristic information of the accelerated computing request; When the task execution characteristic information indicates that the task execution mode of the accelerated computing request is a sequential mode, selecting a plurality of target acceleration units from the candidate heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster; The selected heterogeneous acceleration device including the target acceleration unit is used as the target heterogeneous acceleration device.

11. The system according to claim 10, characterized in that The host side is used for: When the task execution characteristic information indicates that the task execution mode of the accelerated computing request is a disordered mode, selecting a plurality of target acceleration units whose remaining computing resources meet a preset screening condition in the to-be-selected heterogeneous acceleration device; The selected heterogeneous acceleration device including the target acceleration unit is used as the target heterogeneous acceleration device.

12. The system according to claim 9, characterized in that The host side is also used for: Generate a target token for the target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address start address, a data length, a read / write permission bit, a unique identifier of the heterogeneous acceleration device, a unique identifier of the acceleration unit, and a target priority; According to the unique identifier of the heterogeneous acceleration device, the target token is sent to the corresponding target heterogeneous acceleration device, so that the target heterogeneous acceleration device executes the heterogeneous acceleration task to be executed based on the target token, so as to perform corresponding calculation processing on the target data and obtain an accelerated calculation result.

13. The system according to claim 12, characterized in that The target heterogeneous acceleration device is used for: Receiving a target token sent by the host end; When the valid bit of the target token indicates that the token is currently valid, determining the target acceleration unit of the to-be-executed heterogeneous acceleration task and the task type of the to-be-executed heterogeneous acceleration task according to the unique identifier of the acceleration unit in the target token; Determine the permission range of the target acceleration unit according to the physical address starting address, data length and read / write permission bits in the target token; wherein the permission range includes a target read / write range for the target cache device; The execution priority of the target acceleration unit is determined according to the target priority in the target token.

14. The system according to claim 12, characterized in that The host side is used for: Obtaining the number of waiting cycles of each acceleration unit to be selected in the heterogeneous acceleration device to be selected; Determining the time priority of the acceleration unit to be selected according to the number of waiting cycles of the acceleration unit to be selected; Obtaining the task priority of the to-be-executed heterogeneous acceleration task corresponding to the to-be-selected acceleration unit; The target priority is determined according to the time priority and task priority of the acceleration unit to be selected.

15. The system according to claim 1, characterized in that A target communication interface is provided between the host end and each of the heterogeneous acceleration devices, the accelerated computing request includes a database query statement, and the target communication interface is used to: Performing semantic analysis on the database query statement to obtain a semantic analysis result; Extracting target action instructions from the database query statement according to the semantic analysis result; According to the target action instruction, converting the database query statement into a heterogeneous acceleration device general statement, so as to input the heterogeneous acceleration device general statement into the target heterogeneous acceleration device; The target action instructions include at least data query instructions, data insertion instructions, data update instructions and data deletion instructions.

16. A heterogeneous acceleration method, characterized in that: The method is applied to a host side, and the method comprises: Sending an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read target data from a storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode, wherein the storage device is used to store the target data, and performing corresponding computing processing on the target data to obtain an accelerated computing result, and writing the accelerated computing result into a target cache device; When it is determined that the heterogeneous acceleration device has written the accelerated computing result into the target cache device, the target cache device is directly accessed to obtain the accelerated computing result.

17. A heterogeneous acceleration method, characterized in that: The method is applied to a target heterogeneous acceleration device, and the method includes: Receive the accelerated computing request sent by the host; In response to the accelerated computing request, a preset direct transmission mode is adopted to directly read the target data from the storage device; wherein the storage device is used to store the target data; Performing corresponding calculation processing on the target data to obtain an accelerated calculation result, and writing the accelerated calculation result into a target cache device; An interrupt request is sent to the host end to instruct the host end to directly access the target cache device so that the host end obtains the accelerated calculation result.

18. A heterogeneous acceleration device, characterized in that: The device is applied to a host side, and the device comprises: The request acceleration module is used to send an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read the target data from the storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode, and the storage device is used to store the target data, and perform corresponding computing processing on the target data to obtain the accelerated computing result, and write the accelerated computing result into the target cache device; The reading module is used to directly access the target cache device to obtain the accelerated computing result when it is determined that the heterogeneous acceleration device has written the accelerated computing result into the target cache device.

19. A heterogeneous acceleration device, characterized in that: The device is applied to a target heterogeneous acceleration device, and the device includes: A receiving module, used for receiving an accelerated computing request sent by a host; A data reading module, configured to respond to the accelerated computing request and directly read the target data from the storage device using a preset direct transmission mode; wherein the storage device is used to store the target data; An accelerated computing module, used to perform corresponding computing processing on the target data, obtain an accelerated computing result, and write the accelerated computing result into a target cache device; The sending module is used to send an interrupt request to the host end to instruct the host end to directly access the target cache device so that the host end can obtain the accelerated calculation result.

20. A computing device, characterized in that include: A heterogeneous acceleration system as claimed in any one of claims 1 to 15.

21. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the method according to claim 16 or 17 is implemented.

22. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the method according to claim 16 or 17.

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