An integrated sensing, storage, and computing macrocell circuit, system, and digital-to-analog conversion method

Abstract

The present application discloses a sense-in-memory computing integrated macrocell circuit, system and digital-to-analog conversion method. The digital-to-analog conversion method includes the steps of: setting weight coefficients; writing weight signals to the analog memory computing unit according to the weight coefficients through the iSC bus, with each bit of the digital signal corresponding to a weight signal; the tag module reads the digital signal from the iSC bus and sequentially obtains each bit of the digital signal; and performing digital-to-analog conversion calculation, with the formula: DREGn * weight signal; after the conversion calculation of all bits of the digital signal is completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal, so as to enable efficient parallel conversion of analog domain signals and digital domain signals.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits and signal processing, and in particular to a sensing-in-memory integrated macrocell circuit, system, and digital-to-analog conversion method. Background Art

[0002] With the development of the industrial Internet, higher requirements are put forward for video acquisition and processing technologies. In traditional vision application systems, an image sensor collects image information, converts the optical signal into an electrical signal, and after digital-to-analog conversion, it becomes a digital signal. Then, the image data is processed by an image signal processing unit, and finally, it needs to be output to the processor in the system through a special video interface. Then, the processor performs data analysis and makes corresponding control and operations. In the field of laser ranging, the distance measurement sensor also uses the principle of an image sensor to collect image information. The laser sensor emits a laser beam and receives the reflected signal, measures the reflection time to calculate the distance, and the sensor converts the measurement result into a digital signal.

[0003] In applications such as image processing and laser ranging, as Figure 1 shown, the sensing-in-memory integrated chip realizes efficient and low-power data processing by integrating sensing, storage, and computing functions. Among them, in the middle is an array of processing macrocells (PE) 1, where the PEs are closely arranged in an array form, for example, with a scale of 1024*1024. Since each PE includes a basic sensing-in-memory unit, all the PEs in the PE array can simultaneously and parallelly process the data within each unit. Such a method is also often called the single instruction multiple data mode, i.e., SIMD, which is more common in GPUs. A row control module 5 and a column control module 6 are respectively designed in the horizontal and vertical directions of the PE array. The row control module 5 is used for row selection and related control of the PE array, and the corresponding column mode control module is used for column selection and related control of the PE array, as well as data readout selection. An external digital module 4, an INS bus 41, an external analog module 3, and an interface module 7 are also included outside the PE array.

[0004] As Figure 2 shown, the PE unit includes a sensing unit (SU), an analog signal operator arithmetic unit (AOP), an analog memory and computing unit (AREG BANK), a digital memory and computing unit (DREG BANK), a tag module (TAG), and an adjacent PE communication unit (adjacentIF). Among them, the analog memory and computing unit includes several analog registers AREG0, AREG1..., and the analog register itself is also an arithmetic unit. Similarly, the digital memory and computing unit includes several digital registers DREG0, DREG1..., and in addition to storing digital signals, the digital registers can also perform logical operations. The output of the tag unit is used as a judgment signal to control whether the current PE executes the current SIMD instruction.

[0005] Converting conventional digital signals to analog signals requires the use of a dedicated DAC chip or DAC circuit to achieve the conversion. For the image data in vision chips, serial passing through the DAC chip or circuit brings extremely low efficiency problems, as well as high latency and high power consumption problems caused by data transfer. Especially for sense-compute chips, there are analog signal operation and storage units and digital signal operation and storage units in the PE. When signals interact or flow between the analog domain and the digital domain, significant problems are faced. Either a DAC circuit is designed in the PE, but this brings problems such as circuit area and power consumption. Or a dedicated DAC circuit is designed in the chip, and the data in the PE is serially converted through this DAC, resulting in efficiency problems, as well as latency and power consumption problems in data flow. Summary of the Invention

[0006] The present invention proposes a sense-compute integrated macrocell circuit, system, and digital-to-analog conversion method, which can utilize existing PE resources, implement the principle of digital-to-analog conversion through a control method, and then realize a method for parallel digital domain to analog domain signal conversion, which conforms to the characteristics of the SIMD of sense-compute chips, enabling efficient parallel conversion of analog domain signals and digital domain signals at the entire pixel level or single PE level.

[0007] The present invention proposes a digital-to-analog conversion method for a sense-compute integrated macrocell circuit, including the steps of:

[0008] Setting weight coefficients;

[0009] Writing weight signals to the analog memory and computing unit according to the weight coefficients through the iSC bus, with each bit of the digital signal corresponding to a weight signal;

[0010] The tag module reads the digital signal from the iSC bus, sequentially obtains each bit of the digital signal and performs digital-to-analog conversion calculation, with the formula: DREGn * weight signal;

[0011] After the conversion calculations for all bits of the digital signal are completed, the calculation results corresponding to each bit of the digital signal are accumulated to obtain an analog signal.

[0012] A sense-compute integrated macrocell circuit includes:

[0013] An iSC bus for connecting each module to transfer sensing signals and operation signals between modules;

[0014] An INS bus for connecting each module;

[0015] A first control module for setting the weight coefficients corresponding to each bit of the digital signal and writing weight signals to the analog memory and computing unit according to the weight coefficients through the iSC bus;

[0016] The digital memory and computing unit includes multiple digital registers for simultaneously storing digital data and performing data operations, and each digital register stores one-bit digital signals;

[0017] The analog memory and computing unit includes multiple analog registers for simultaneously storing analog data and performing data operations, which are divided into read registers and result registers. The read registers are used to store weight signals, and the result registers are used to store the results of digital-to-analog conversion;

[0018] The tag module is used to read digital signals from the iSC bus, sequentially judge each bit of the digital signals. When it is not 0, retain or read out the weight signals, otherwise rewrite or do not read the weight signals;

[0019] The second control module is used to, after all bits of a digital signal are judged, accumulate the weight signals read from the read registers of the analog memory and computing unit and store them in the result registers of the analog memory and computing unit.

[0020] The present invention also provides a circuit system, including: the sense memory and computing integrated macro cell circuit, and the multiple sense memory and computing integrated macro cell circuits are arranged in an array structure.

[0021] The present invention utilizes the existing PE resources, realizes the principle of DAC through a control method, and further realizes the method of parallel digital domain to analog domain signal conversion, which conforms to the characteristics of the sense memory and computing integrated system chip SIMD, and simultaneously realizes DAC conversion for the entire PE array.

[0022] The present invention is realized by using existing components, converts digital signals into current signals and stores them in the AREG in the PE. Without adding special conversion circuits, it realizes the method of parallel digital domain to analog domain signal conversion. This method does not require a dedicated DAC circuit, utilizes the existing circuits in the PE to realize the conversion function. This parallel conversion is equivalent to signal conversion at the pixel level or the PE level, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0024] Figure 1 It is a schematic diagram of the architecture of a sense memory and computing integrated circuit system;

[0025] Figure 2 It is a schematic diagram of the architecture of a sense memory and computing integrated macro cell circuit;

[0026] Figure 3 It is a schematic diagram of the AREG BANK operation of a sense-in-memory computing macrocell circuit;

[0027] Figure 4 It is a schematic diagram of the AREG BANK operation of another sense-in-memory computing macrocell circuit;

[0028] Figure 5 It is a schematic diagram of the AREG BANK operation of another sense-in-memory computing macrocell circuit;

[0029] Figure 6 It is a schematic diagram of the DREG BANK structure of a sense-in-memory computing macrocell circuit;

[0030] Figure 7 It is a schematic diagram of the SRAM circuit of a sense-in-memory computing macrocell circuit;

[0031] Figure 8 It is a schematic diagram of the TAG circuit of a sense-in-memory computing macrocell circuit;

[0032] Figure 9 It is a schematic diagram of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit according to an embodiment of the present application;

[0033] Figure 10 It is a flowchart of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit according to the first embodiment of the present application;

[0034] Figure 11 It is Figure 10 A schematic diagram of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit of the embodiment;

[0035] Figure 12 It is a flowchart of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit according to the second embodiment of the present application;

[0036] Figure 13 It is Figure 12 A schematic diagram of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit of the embodiment;

[0037] Figure 14 It is a flowchart of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit according to the third embodiment of the present application;

[0038] Figure 15 It is Figure 14 A schematic diagram of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit of the embodiment;

[0039] Figure 16 It is a coding schematic diagram of the digital-to-analog conversion method of the sense-in-memory computing macrocell circuit according to the first embodiment of the present application;

[0040] Figure 17 Schematic diagram of the correspondence between binary digital signals and analog signals of the sense-compute-integrated macrocell circuit according to another embodiment of the present application;

[0041] Figure 18 Coding schematic diagram of the digital-to-analog conversion method of the sense-compute-integrated macrocell circuit according to the fourth embodiment of the present application;

[0042] Figure 19 Flowchart of the digital-to-analog conversion method of the sense-compute-integrated macrocell circuit according to the fourth embodiment of the present application;

[0043] Figure 20 is Figure 19 Schematic diagram of the digital-to-analog conversion method of the sense-compute-integrated macrocell circuit of the embodiment. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention. Obviously, the embodiments described in the present invention are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0045] In the present application, unless otherwise stated, the use of "or" means "and / or". In addition, the use of terms such as "comprising", "including" and other forms of "including" is not restrictive. In addition, unless specifically stated otherwise, terms such as "element" or "component" cover both elements and components including one unit and elements and components including more than one unit.

[0046] The present invention provides a sense-compute-integrated macrocell system, including a plurality of sense-compute-integrated macrocell circuits arranged in an array. As Figure 1 shown, in this embodiment, the sense-compute-integrated macrocell system is specifically designed in a sense-integrated chip. In the middle is a processing macrocell (PE) array, where PE1s are closely arranged in an array form, for example, with a scale of 1024*1024. The internal structure of the PE will be described in detail with reference to the specific sense-compute-integrated macrocell circuit and the embodiment of the sense-compute-integrated macrocell circuit later. Here, only the overall architecture of the sense-integrated macrocell system is described.

[0047] Since each PE includes a sensing-in-memory computing basic unit, all the PEs in the PE array can simultaneously and parallelly process the data within each unit. Such a method is also often referred to as the single instruction multiple data mode, i.e., SIMD, which is relatively common in GPUs. A row control module and a column control module are respectively designed in the horizontal and vertical directions of the PE array. The row control module is used to perform row selection and related control on the PE array, and the corresponding column mode control module is used to perform column selection and related control on the PE array, as well as data readout selection. Therefore, in addition to the PE array, the sensing-in-memory integrated circuit system also includes a digital-to-analog conversion unit (DAC) 2, a peripheral analog module 3, a peripheral digital module 4, a row control module 5, a column control module 6, an interface module 7, etc. arranged outside the PE array, and an INS bus 41.

[0048] In one embodiment, the sensing-in-memory integrated macro unit system includes a plurality of sensing-in-memory integrated macro unit circuit layouts in an array structure. Specifically, it can be a sensing-in-memory integrated macro unit circuit of a distance measurement sensor, such as Figure 2 shown, the PE unit includes a sensing unit SU, an analog signal operator arithmetic unit AOP, an analog memory computing unit AREG BANK, a digital memory computing unit DREGBANK, a tag module TAG, an adjacent PE communication unit adjacent IF, an iSC bus, and an INS bus. The above units and modules are all connected to the iSC bus and the INS bus. The iSC bus is used to transmit sensing signals and arithmetic signals, and the sensing unit and the memory computing unit are both connected to the iSC bus; the INS bus is used to transmit instructions.

[0049] The analog memory computing unit is provided with an AREG BANK, and the AREG BANK includes a plurality of analog registers AREG, which are the basic units for storing and operating on analog signals in the PE analog domain. A group of AREG0, AREG1, AREG2... form the AREG BANK to achieve a more powerful signal processing ability. Such as Figure 3 , for the read operation of AREG0, read out I0, for the write operation of AREG1, write the current read out from AREG0 to this register, but the current flowing into AREG1 is I0. Since the current has a direction, it is defined as -I0.

[0050] Such as Figure 4 shown, for the read operation of AREG0, read out I0, for the read operation of AREG1, read out I1 to the iSC BUS, and AREG2 is in the write state. Therefore, the magnitude of the written current should be I0 + I1, that is, the addition operation is realized. If the current directions of I0 and I1 are different, the subtraction operation is realized. If the same current is repeatedly added, the integer multiplication operation is realized. Of course, a dedicated multiplication circuit can also be designed.

[0051] Such as Figure 5, For the read operation of AREG0, I0 is read out. AREG1 and AREG2 are both in write operations at the same time. The current magnitude written into each register AREG1 / 2 is I0 / 2. Therefore, an integer division operation is achieved.

[0052] Several AREGs form an AREG BANK, such as 5 or 10. The number of AREGs is designed according to the application. Such a group of AREGs can achieve a large amount of signal storage and arithmetic operations of addition, subtraction, multiplication, and division, providing basic arithmetic capabilities for complex algorithms in the application.

[0053] In the present invention, the above arithmetic operations of AREG are utilized to achieve the conversion from the digital domain of the PE to the analog domain, that is, converting the digital signal in the PE into a corresponding analog signal.

[0054] Specifically, the tag module is used to read digital signals from the iSC bus and sequentially judge each bit of the digital signal. In one embodiment, the tag module sets a tag value according to each bit of the digital signal, and determines whether the current sensing, computing, and storing integrated macro cell circuit executes the instruction sent by the INS bus based on the stored tag value. The first control module is used to set the weight signal corresponding to each bit of the digital signal, and write the weight signal into the analog computing and storing unit according to the weight coefficient through the iSC bus. Each bit of the digital signal corresponds to a weight signal; the digital computing and storing unit includes multiple digital registers for simultaneously storing digital data and performing data operations. Each digital register stores one bit of digital signal; the analog computing and storing unit includes multiple analog registers for simultaneously storing analog data and performing data operations, including a read register and a result register. The read register is used to store the weight signal, and the result register is used to store the digital-to-analog conversion result; the tag module is used to read digital signals from the iSC bus, sequentially judge each bit of the digital signal. When it is not 0, retain or read out the weight signal, otherwise rewrite or do not read the weight signal; the second control module is used to, after all bits of a digital signal are judged, accumulate the weight signals read from the read register of the analog computing and storing unit and store them into the result register of the analog computing and storing unit.

[0055] In one embodiment, the weight coefficients corresponding to each bit of the digital signal change according to a linear function, increasing or decreasing in multiples.

[0056] In one embodiment, an encoding module is further included for encoding the digital signal according to the standard binary code.

[0057] In one embodiment, the weight signal and the analog signal are current values.

[0058] In one embodiment, the analog memory and computing unit includes three read registers, one result register, and one cache register; it further includes a processing unit that sequentially determines each bit of the digital signal. When the bit is not 0, the analog memory and computing unit is enabled, and the weight signal read out is added to the result signal stored in the result register and then written into the cache register; the result in the cache register is written into the result register.

[0059] In one embodiment, the analog memory and computing unit includes three read registers and one result register; it further includes a processing unit that sequentially determines each bit of the digital signal. When the bit is 0, the weight signal is rewritten as 0, and the weight signals corresponding to each bit of the digital signal are added and then stored in the result register.

[0060] In one embodiment, the analog memory and computing unit includes one cache register, one result register, and one weight signal register; the external DAC unit sequentially sends the weight signal to the weight signal register; each bit of the digital signal is sequentially determined. When the bit is not 0, the analog memory and computing unit is enabled, and the weight signal read out is added to the result signal in the result register and then written into the cache register; the result in the cache register is written into the result register.

[0061] In one embodiment, the analog memory and computing unit includes three read registers and one result register; one of the read registers is used to store the sign bit.

[0062] In one embodiment, the sensing unit, the analog memory and computing unit, the digital memory and computing unit, the iSC bus, the INS bus, and the tag module are integrally integrated on the same substrate.

[0063] In one embodiment, the analog memory and computing unit includes a plurality of analog registers. The analog registers also serve as analog arithmetic units. By connecting the plurality of analog memory and computing units to the same iSC bus for read and write operations, analog signals can directly perform addition, subtraction, multiplication, and division operations in the analog registers.

[0064] In one embodiment, the digital memory and computing unit includes a plurality of digital registers, and the digital registers have both storage and logical operation capabilities.

[0065] In one embodiment, a DREG BANK is provided in the digital memory and computing unit. The DREG BANK includes a plurality of digital registers, as well as a digital read bus iSC RD data bus and a digital write bus iSC WR data bus. The digital register is a digital register DREG. A plurality of digital registers DREG are connected in parallel between the digital read bus iSC RD data bus (DBUS) and the digital write bus iSCWR data bus. Among them, the input end IN of the digital register DREG is connected to the iSC WR data bus, and the output end OUT of the digital register DREG is connected to the iSC RD data bus. A multiplexer MUX is also connected between the digital read bus iSC RD data bus and the digital write bus iSC WR data bus. The digital read bus iSC RD data bus of the digital register DREG is also connected to the iSC bus through a switch.

[0066] In one embodiment, the digital register is implemented by Flash. Further, it includes: a plurality of FLASH memories, as well as a read-write control circuit, a read data iSC RD data bus, and a multiplexer MUX. Among them, the input end IN of the FLASH memory is connected to the read-write control circuit, and the output ends of the FLASH are connected in parallel to the iSC RD data bus, and a multiplexer MUX is connected between the iSC RD data bus and the read-write control circuit.

[0067] In one embodiment, a comparator circuit (COMP) is included inside the tag module. Figure 8 , which is used to compare the magnitudes of two signals.

[0068] In one embodiment, the analog memory and computing unit includes several analog registers AREG0, AREG1… The analog register itself is also an arithmetic unit, and signals can perform addition, subtraction, multiplication, and division operations through the analog register. For example, 5 registers can be designed to meet the basic arithmetic requirements. Similarly, a DREG BANK is provided in the digital memory and computing unit. The DREG BANK includes a plurality of digital signal memories DREG, and each digital register can store one bit of data.

[0069] The digital register is implemented by 3T DRAM, or 6T DRAM, SRAM. 6T SRAM is used as the circuit for storing digital signals DREG in the PE. Compared with the previous DRAM, the storage is more stable, but it will increase the cell size of the DREG. Data is written through the MWR transistor, WR is valid, and the IN input valid signal is used to complete the write operation. Correspondingly, data is read through the MRD transistor, RD is valid, and the OUT output valid signal is used to complete the read operation. The specific RAM in this embodiment refers to Figure 7 .

[0070] In one embodiment, in addition to performing conventional operations through analog registers, the analog signal operator operation unit AOP can separately design an efficient special operator to implement special operations according to the particularity of the application scenario, such as square operation, log operation, square root operation, etc.

[0071] In one embodiment, the tag value of the tag unit TAG serves as a judgment signal for controlling whether the current PE executes the instruction of the current SIMD. For example, when the TAG tag value is 0, the current PE does not execute the current instruction, such as closing the read / write register, that is, the read data is 0. Conversely, when the TAG tag value is 1, the current PE executes the current instruction, such as reading the weight signal. A communication interface between adjacent PEs is also designed in the PE, such as Figure 2 the adjacent PE communication unit (Adjacent IF) in, which can provide the information of the 8 PEs surrounding the current PE to the current PE. The above-mentioned module units are connected together through the specially designed iSC bus for sensing, computing and storing. The analog signal can be a voltage or a current signal. In addition to the iSC bus, a global instruction bus INS bus is also designed in the PE to perform overall operation control on each functional module in the PE. Since the INS bus of each PE is controlled by the same global signal, in this way, the integration of storage and computing (SIMD) is achieved. The circuit structure of the tag unit TAG is as Figure 8 shown.

[0072] In an embodiment of the circuit system of the present invention, it includes a plurality of the above-mentioned macro units for integrating sensing, computing and storing, and the plurality of macro units for integrating sensing, computing and storing are arranged in an array structure; it further includes: a DAC unit arranged outside the array structure.

[0073] The present invention also provides a circuit system, including: a plurality of macro units for integrating sensing, computing and storing are arranged in an array structure.

[0074] This will be further described below in conjunction with the macro unit circuit for integrating sensing, computing and storing and its digital-to-analog conversion method.

[0075] Refer to Figure 9 , in the digital-to-analog conversion method of the macro unit circuit for integrating sensing, computing and storing in this embodiment, it includes the steps of: setting weight coefficients; writing weight signals to the analog storage and computing unit through the iSC bus, and each bit of the digital signal corresponds to a weight signal; the tag module reads the digital signal from the iSC bus, sequentially obtains each bit of the digital signal, from the MSB to the LSB, or from the LSB to the MSB, and performs digital-to-analog conversion calculation, and the formula is:; after the conversion calculation of all bits of the digital signal is completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal.

[0076] The present invention realizes the conversion from the digital domain of PE to the analog domain, that is, converting the digital signal in PE into the corresponding analog signal. The following example converts the digital signal of DREG in PE, for example, with a precision of 3 bits, and in actual use, 5-bit precision or even higher 8-bit digital signals can be used, into an analog signal and stores it in the analog register AREG. The iSC bus is used for transmission.

[0077] In one embodiment, a 3-bit digital signal is taken as an example. The digital signals of DREG0, DREG1, and DREG2 in the DREG BANK are converted into analog current signals and stored in the result register AREG3 of the AREG BANK. For example, in this embodiment, the current range stored in AREG is 0uA to 8uA, and the range of the current signal is 8uA, denoted as Ipp, which is the current range stored in the analog memory and computing unit, that is, the difference between the maximum and the minimum. In this range, the digital value stored in DREG is mapped into the corresponding current signal and stored in AREG.

[0078] First, an analog signal of 1 / 2*Ipp needs to be stored in the read register AREG2, an analog signal of 1 / 4*Ipp needs to be stored in the read register AREG1, and an analog signal of 1 / 8*Ipp needs to be stored in the read register AREG0. The result register AREG3 is used to store the final analog signal result, and a 0uA analog signal is stored in AREG3 during the initialization phase. Specifically, the current corresponding to the weight signal can be written into AREG by means of writing through the iSC bus, or the weight signal of the AREG reading the iSC bus can be used to calculate the analog signal of the corresponding current in the corresponding register.

[0079] Next, the binary digital signal to be converted is stored in DREG0, DREG1, and DREG2. Among them, DREG2 stores the highest bit [2] of the 3-bit binary value, DREG1 stores [1] of the 3-bit binary value, and DREG0 stores the lowest bit [0] of the 3-bit binary value. Specifically, the digital signal to be converted can be written into DREG by means of writing through the iSC bus.

[0080] Reference Figure 11 , by using the iSC bus, in the way that AREG0, AREG1, and AREG2 read operations output current and AREG3 write operation inputs current, the binary weight relationship is calculated according to the following formula for the analog signal (Value DAC ):

[0081] k is the conversion accuracy. In this embodiment, it is 3 bits, k = 3, which is specifically related to the digital signal coding rule for conversion. n is the corresponding number of bits, and n takes values of 0, 1, 2. In other embodiments, the accuracy of the digital signal can also be adjusted. For example, k can take 4 or 5 corresponding to accuracy bits of 4 bits and 5 bits, and then the corresponding value range of n is from 0 to k - 1.

[0082] Specifically, in this embodiment:

[0083] Value DAC = DREG2 * 2 2 *(1 / 8*Ipp) + DREG1 * 2 1 * (1 / 8* Ipp) + DREG0 * 2 0 * (1 / 8* Ipp)

[0084] =》Value DAC = DREG2 * (1 / 2*Ipp) + DREG1 * (1 / 4* Ipp) + DREG0 * (1 / 8*Ipp)

[0085] =》Value DAC = DREG2 * I AREG2 + DREG1 * I AREG1 + DREG0 * I AREG0

[0086] The highest bit [2] of the binary represents 1 / 2*Ipp, the [1] of the binary value represents 1 / 4*Ipp, and the lowest bit [0] of the binary value represents 1 / 8* Ipp. Add the analog signal currents corresponding to the weights with the value of 1 in the 3 bits to Value DAC (AREG3). I AREG represents the current of its corresponding register. Of course, in other embodiments, the current can also be changed to a voltage value.

[0087] Therefore, it is only necessary to operate according to the values stored in DREG0, DREG1, and DREG2. In this embodiment, read the values in DREG0, DREG1, and DREG2 in sequence. If the value stored in DREG is 1, then TAG = 1, perform an addition operation, and store the result in Value DAC If the value stored in DREG is 0, then TAG = 0, and this PE does not perform the current global addition operation, that is, this AREG does not perform a read operation, and Value DACKeep the result of the previous calculation. Specifically, in one embodiment, the reference signal can be input through the negative input terminal of the TAG, and the value of 1 / 2*VDD can be input through the positive input terminal by, for example, gating, and the values of DREG0, DREG1, and DREG2 can be input in sequence. If DREG0 is 1, then AREG0 performs a read operation; otherwise, the PE does not perform an operation. Similarly, if DREG1 is 1, then AREG1 performs a read operation; otherwise, the PE does not perform an operation. Similarly, if DREG2 is 1, then AREG2 performs a read operation; otherwise, the PE does not perform an operation. In this way, a 3-bit digital signal requires three judgments and analog signal addition to complete the conversion. By analogy, a 5-bit signal requires five times.

[0088] Reference Figure 16 In one embodiment, the conversion is carried out according to the binary principle, with equal proportion conversion, that is, linear conversion. The weight coefficients are 1 / 2, 1 / 4, and 1 / 8 respectively. Specifically, the storage current range of AREG is 0 μA to 8 μA. The correspondence between the binary digital signal and the analog signal is as Figure 17 , which also shows the encoding of the digital-to-analog conversion method of the sense-storage-computation integrated macro cell circuit.

[0089] In the first embodiment, refer to Figure 10 and 8 , a cache register Cache can be set. The conversion results of each AREGn are accumulated into Cache and then stored in the result register AREG3. The conversion result of each digital signal is added to the result signal stored in the result register example and then stored in Cache, and then written from Cache to the result register. Finally, the value of the read result register is used for output. Specifically, AREG4 can be used as Cache.

[0090] In the second embodiment, refer to Figure 12 and 10 , Cache can be not set, and the conversion results of each AREGn are directly accumulated into AREG3 for output.

[0091] In the third embodiment, refer to Figure 14 and Figure 15, the writing of the weight coefficient can be achieved through the DAC outside the PE in the chip, with global writing. The DAC can be 5-bit or of higher precision to achieve a more refined analog signal input. The AREG1 is used to store the weight data, and write operations are performed on AREG1. The AREG0 serves as a Cache. Thus, each digital signal passes through one AREG. For example, AREG1 is used to convert the analog signal, and the converted signals are added and stored in the Cache, which is AREG0, and then stored in the result register AREG1. The conversion result of each digital signal is added to the result stored in the result register and then stored in the Cache, and then written from the Cache to the result register. Finally, the value of the read result register AREG1 is used for output.

[0092] In one embodiment, the DAC outside the PE can also directly write the current analog signal corresponding to the weight coefficient.

[0093] In one embodiment, the original signal can come from the SU unit, or be written into the PE from outside the chip, or come from the digital memory and computing unit DREG BANK, or the AOP unit, and then be sent to the iSC bus. The TAG unit receives the digital signal from the iSC bus, and thus, according to the magnitude of the DREG digital signal, makes a comparison to obtain the TAG value, and then performs read and write operations on the AREGBANK according to the TAG value, so as to realize the conversion from digital signal to analog signal. The operation result can be stored in the AREG of the PE and then output through the iSC bus to achieve a certain application function.

[0094] All of the above data transmissions and signal acquisitions require control by the INS instruction. The INS bus connects the components in each PE. The INS can be an instruction sent from a system outside the chip, or be issued by the internal MCU module of the chip, or the chip internally generates specific application INS.

[0095] In one embodiment, the storage current range of the AREG is from -8uA to 8uA, and the voltage output to the iSC bus will also change correspondingly, from 0.2V to 0.9V.

[0096] Because the main circuit of the TAG module is a comparator circuit, therefore, by utilizing the characteristics of the TAG comparator, the DAC function is implemented in the PE, that is, the mutual conversion between the digital domain signal and the analog domain signal in the PE is realized. Specifically, the iSC bus is connected to the positive terminal of the comparator in the TAG. The negative terminal of the comparator in the TAG inputs a reference signal, which is 1 / 2*VDD in this embodiment.

[0097] Specifically, the DREG BANK can send digital signals to the iSC bus. The TAG internally includes a comparator circuit used to compare the magnitudes of the digital signal obtained from the iSC and the reference signal. For exampleFigure 8 As shown, the gate of MOS transistor M171 inputs signal A, the gate of MOS transistor M172 inputs signal B, the drain of MOS transistor M172 serves as the output terminal, and the comparator circuit is used to compare the magnitudes of the two signals. When A is less than B, the output of TAG will become 0, or the output terminal of digital register DREG is input to terminal B, and the reference signal voltage is input to terminal A to determine whether the value of DREG exceeds the given reference signal voltage. If it exceeds, it is 0; if it is lower, it becomes 1.

[0098] Next, the sense-storage-and-computation integrated macrocell circuit and its digital-to-analog conversion method of the present invention will be further described in conjunction with the specific digital-to-analog conversion process. Embodiment

[0099] In this embodiment, referring to Figure 10 and Figure 11 , the encoding rule of the digital signal is the standard binary code. The weight coefficient increases or decreases in multiples according to a linear function. As Figure 10 shown, in the control flow, through instruction control, the chip executes operations according to the instructions, and the entire PE array operates in the SIMD mode. The analog signal is converted into a digital signal, and the specific operation process and steps are as follows:

[0100] S10: Write the weight signal to AREG;

[0101] Among them, each read register corresponds to a weight signal. In this embodiment, AREG0, AREG1, and AREG2 are used to store the weight signals. Therefore, in this step, AREG0, AREG1, and AREG2 respectively store a weight signal corresponding to one-bit digital signal.

[0102] S20: Initialize the AREG result register to 0;

[0103] In this embodiment, AREG3 is set as the result register to store the result RESULT after digital-to-analog conversion.

[0104] S30: Set the tag value of TAG to 1;

[0105] S40: Read the digital signal of DREGn;

[0106] Among them, the initial value of n is 2;

[0107] k is the conversion accuracy. In this embodiment, it is 3bit, k = 3, n is the corresponding number of bits, and n takes values of 0, 1, 2. In other embodiments, the accuracy of the digital signal can also be adjusted. For example, k can take 4, 5 corresponding to the accuracy bits of 4bit, 5bit, then the corresponding value range of n is from 0 to k - 1.

[0108] S50: The TAG unit compares the digital signal of the currently read DREG(n) with the reference signal;

[0109] S60: Set the tag value according to the comparison result, and determine whether the tag value is 1;

[0110] Among them, if the TAG tag value = 1, continue to execute step S70; if the TAG tag value = 0, then execute step S90;

[0111] Specifically, the reference signal is 1 / 2*VDD. If the comparison digital signal is greater than the reference signal, the TAG tag value is 1, otherwise it is 0. If the TAG tag value = 1, continue to execute step S70; if the TAG tag value = 0, then execute step S90.

[0112] S70: Cache = AREGn + RESULT;

[0113] Specifically, the PE executes the global instruction, performs the AREG read operation, that is, reads the weight signal and adds (writes) it to the Cache. In this embodiment, AREG4 is set as the Cache.

[0114] Read the weight signal corresponding to this bit and perform digital-to-analog conversion:

[0115] Add digital-to-analog conversion:

[0116] Cache(AREG4) = + RESULT(AREG3)

[0117] S80: AREG3 = Cache;

[0118] Specifically, the result of Cache(AREG4) is written into AREG3.

[0119] S90: Determine whether n = 0;

[0120] Specifically, then judge n. If n is not equal to 0, then execute n = n - 1, return to step S30, otherwise end the conversion.

[0121] Second Embodiment

[0122] In this embodiment, refer to Figure 12 and Figure 13 as shown, the specific operation process and steps are as follows:

[0123] S10: Write the weight signal to AREG;

[0124] Specifically, each digital signal corresponds to a weight signal. In this embodiment, AREG0, AREG1, and AREG2 are used to store the weight signals. Therefore, in this step, AREG0, AREG1, and AREG2 respectively store a weight signal corresponding to one digital signal.

[0125] S20: Initialize the AREG result register to 0;

[0126] In this embodiment, AREG3 is the result register, and AREG3 = 0.

[0127] S30: Set the tag value of TAG to 1;

[0128] S40: Read the digital signal of DREGn;

[0129] Among them, the initial value of n is 2;

[0130] S50: The TAG unit compares the digital signal and the reference signal;

[0131] Specifically, the TAG unit compares the digital signal of the currently read DREGn and the reference signal.

[0132] S60: Set the tag value according to the comparison result and determine whether the tag value is 1;

[0133] Specifically, if the TAG tag value = 1, continue to execute step S80; if the TAG tag value = 0, then execute step S70;

[0134] The reference signal is 1 / 2*VDD. If the comparison digital signal is greater than the reference signal, the TAG tag value is 1, otherwise it is 0. If the TAG tag value = 1, continue to execute step S80; if the TAG tag value = 0, then execute step S70.

[0135] S70: AREGn = RESULT = 0;

[0136] Specifically, this PE executes the global instruction, performs the AREGn read and write operations, that is, reads the weight signal, performs analog conversion, and then saves it to AREGn; reads the weight signal corresponding to this bit and performs digital-to-analog conversion:

[0137]

[0138] S80: Then determine whether n is 0;

[0139] Specifically, if n is not equal to 0, then execute n = n - 1 and return to step S30.

[0140] S90:;

[0141] Specifically, if n = 0, end the conversion and output Value DAC .

[0142] Third Embodiment

[0143] In this embodiment, referring to Figure 14 and Figure 15 , the present invention also provides another implementation method, which occupies fewer AREGs. Only 1 AREG register is used to store the weight that needs to be converted currently. As Figure 14 shown, IO_REG is used. This REG is a type of AREG and can be considered as an AREG register. However, the input source is the chip I / O. That is, for each bit conversion, the chip IO needs to provide the corresponding analog signal, which can be a voltage or a current signal.

[0144] It includes the steps:

[0145] S10: Initialize the AREG result register to 0;

[0146] In this embodiment, AREG3 is used as the result register.

[0147] S20: Set the tag value of TAG to 1;

[0148] S30: The external DAC unit sends a weight signal to the iSC and writes to IO_REG;

[0149] Specifically, the external DAC unit sends a weight signal to the iSC. For each bit of the digital signal read, the iSC sends the weight signal corresponding to this bit of the digital signal and writes to IO_REG

[0150] S40: Read the digital signal of DREGn;

[0151] Specifically, the initial value of n is 2;

[0152] S50: The TAG unit compares the digital signal and the reference signal;

[0153] Specifically, the TAG unit compares the digital signal of the currently read DREGn and the reference signal. If DREGn = 1, the TAG tag value is 1, otherwise it is 0.

[0154] S60: Set the tag value according to the comparison result and determine whether the tag value is 1;

[0155] Specifically, if the TAG tag value = 1, continue to execute step S70. If the TAG tag value = 0, then execute step S90;

[0156] S70: Cache = IO_REG + RESULT;

[0157] Specifically, the PE executes a global instruction, performs an AREG read operation, that is, adds the read weight coefficient and RESULT in the result register, and writes it to the Cache. In this embodiment, AREG0 is used as the Cache.

[0158] Read the weight signal corresponding to this bit and perform digital-to-analog conversion:

[0159]

[0160] Addition digital-to-analog conversion:

[0161] Cache (AREG0) = DREGn * IO_REG + RESULT(AREG3)

[0162] S80: AREG3 = Cache;

[0163] Specifically, the addition result of the Cache is written to AREG3

[0164] S90: Determine whether n is 0;

[0165] Specifically, if n is not equal to 0, then execute n = n - 1 and return to step S20; if n = 0, then end the conversion.

[0166] The previous method will occupy more AREG registers, but since the weight values have been written to the corresponding AREGs during the initialization phase, the execution efficiency will be relatively high.

[0167] The converted analog signal is stored in the AREG of Value DAC and can be used for calculations in the analog domain, or output as the final operation result to the system at the back-end of the chip to provide relevant analog signals for the back-end system.

[0168] Fourth Embodiment

[0169] The same parts of this embodiment and Embodiment 1 will not be elaborated, and the differences are as follows:

[0170] In the previous embodiments, the conversion range is quantization in the range of 0 uA to 8 uA. If there is a negative value in the conversion range, such as from -4 uA to 4 uA, the method is as Figure 18 shown. If still with 3-bit precision, referring to Figure 20 , then use the high bit (the 3rd bit) as the sign bit, and the lower 2 bits perform the conversion principle described before. At this time, Ipp is 4 uA, not 8 uA described before. Refer to Figure 19 and Figure 20, AREG2 stores -1 * Ipp, i.e., -4 μA. The operations of the lower two bits are exactly the same as those in the first embodiment. When it comes to the sign bit, when Sign bit = 0, AREG2 participates in the operation, i.e., Cache = AREG2 + RESULT, and then AREG3 = Cache; when Sign bit = 1, AREG2 does not participate in the operation, and the current conversion is completed. The flowcharts n are 0 and 1.

[0171] The present invention provides a method for parallel digital - to - analog signal conversion in a PE. This method does not require a dedicated DAC circuit and utilizes the existing circuits in the PE to achieve the conversion function. This parallel conversion is equivalent to signal conversion at the pixel level or the PE level, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion.

[0172] For the conventional conversion of digital signals to analog signals, a dedicated DAC chip or a DAC circuit is required to achieve the conversion. For traditional image sensors, it has evolved from a single DAC in the early stage, to column - level DACs, and then to the latest pixel - level DAC design. However, this requires advanced process manufacturing requirements due to the size limitation of DAC design and the frequency characteristic requirements of DACs. In this traditional way, the data transfer process results in high latency and high power consumption.

[0173] Especially for the sense - compute chip, there are analog signal operation and storage units and digital signal operation and storage units in the PE. When signals interact or flow between the analog domain and the digital domain, significant problems are faced. Either design a DAC circuit in the PE, which brings problems of circuit area and power consumption, or perform serial conversion through a single DAC circuit, which brings problems of efficiency, as well as delays and power consumption in data flow.

[0174] The present invention does not require a dedicated DAC circuit and utilizes the existing circuits in the PE to achieve the conversion function. This parallel conversion is equivalent to signal conversion at the pixel level or the PE level, with high efficiency and high bandwidth, and is very suitable for visual signal processing and conversion.

[0175] The embodiments of the mechanism disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of this application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system including volatile and non - volatile memories and / or storage elements, at least one input device, and at least one output device.

[0176] The program code can be applied to the input instructions to execute the various functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner.

[0177] The program code can be implemented in a high-level procedural language or an object-oriented programming language to communicate with the processing system. When necessary, the program code can also be implemented in an assembly language or a machine language. In fact, the mechanisms described in this application are not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0178] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried or stored on one or more transient or non-transitory machine-readable (e.g., computer-readable) storage media, which can be read and executed by one or more processors. For example, the instructions can be distributed via a network or via other computer-readable media. Thus, the machine-readable media can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to, floppy disks, optical disks, optical discs, compact disc read-only memories (CD-ROMs), magneto-optical discs, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) in electrical, optical, acoustic, or other forms via the Internet. Thus, the machine-readable media includes any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0179] In the drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or ordering may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Additionally, the inclusion of a structural or method feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0180] It should be noted that each unit / module mentioned in the device embodiments of the present application is a logical unit / module. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or can be implemented as a combination of multiple physical units / module. The physical implementation manner of these logical units / modules themselves is not the most important. The combination of the functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0181] It should be noted that in the examples and descriptions of the present application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0182] Although the present application has been illustrated and described by referring to some preferred embodiments of the present application, those of ordinary skill in the art should understand that various changes can be made in form and detail without departing from the spirit and scope of the present application.

Claims

1. A digital-to-analog conversion method for a sensing-storage-computing integrated macro unit circuit, characterized in that: Includes steps: Set the weight coefficient and obtain the weight signal according to the weight coefficient; A register for storing a weight signal is set in the analog storage unit; A cache register for temporarily storing calculation results is set in the analog storage unit; a result register for storing analog signal data is set in the analog storage unit; According to the weight coefficient, the weight signal is written into the register for storing the weight signal of the analog storage unit through the iSC bus, and each bit of the digital signal corresponds to a weight signal; Read each bit of digital signal from the digital register in sequence; The tag module judges and compares the value of each digital signal and performs digital-to-analog conversion calculation. The formula is: DREGn*weight signal. The calculation formula of the weight signal is: weight signal = weight coefficient * Ipp, where DREGn represents the digital signal of the corresponding bit stored in the digital register, n is a natural number, representing the corresponding conversion bit number, and Ipp represents the current range stored in the analog storage unit; The analog signal is read from the analog register and the conversion result of the previous step is added and written into the cache register; the data of the cache register is written back to the result register; After all bit conversion calculations of the digital signal are completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal.

2. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The weight coefficient corresponding to each bit of the digital signal changes in sequence according to a linear function, increasing or decreasing in multiples.

3. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The encoding rule of digital signals is standard binary code.

4. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The calculation formula for the analog signal is: , k represents the conversion precision, which is an integer greater than 0, and n is the corresponding number of conversion bits, ranging from 0 to k-1.

5. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 1, characterized in that: The method also includes the steps of setting a label value of the label module according to each bit of the digital signal, and determining whether the current sensing, storage and computing integrated macro unit circuit executes the instruction sent by the INS bus based on the stored label value.

6. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 5, characterized in that: After all bit conversion calculations of the digital signal are completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal, including the steps of: Read each bit of the digital signal in sequence; Compare the reference signal with the current bit of the read digital signal; Set the label value according to the comparison result, and determine whether the label value is 1. If the label value is 1, read the corresponding weight signal and the current result signal in the result register, add them and write them into the cache register; Write the result of the cache register into the result register; If the tag value is 0, no reading or writing is performed.

7. The digital-to-analog conversion method of the sensing-storage-computing-in-one macro-unit circuit according to claim 5, characterized in that: After all bit conversion calculations of the digital signal are completed, the conversion results corresponding to each bit of the digital signal are accumulated to obtain an analog signal, including the steps of: Read each bit of the digital signal in sequence; Compare the reference signal with the current bit of the read digital signal; Set the label value according to the comparison result, and determine whether the label value is 1. If the label value is 1, retain the weight signal of the corresponding bit; If the label value is 0, rewrite the weight signal of the corresponding bit to 0; After all bits of the digital signal are converted, the conversion results corresponding to each bit are added and stored in the result register.

8. A sensing-storage-computing integrated macro unit circuit using the digital-to-analog conversion method according to any one of claims 1 to 7, characterized in that: include: iSC bus is used to connect various modules and transmit perception signals and operation signals between modules; INS bus, used for global control of each module; The first control module is used to set the weight coefficient corresponding to each bit of the digital signal, and write the weight signal to the analog storage and calculation unit through the iSC bus according to the weight coefficient; A digital storage and calculation unit includes a plurality of digital registers for simultaneously performing digital data storage and data calculation, each digital register storing one bit of digital signal; The analog storage and calculation unit includes a plurality of analog registers for simultaneously performing analog data storage and data calculation, wherein the analog storage and calculation unit includes a read register and a result register. The read register is used to store a weight signal, and the result register is used to store a digital-to-analog conversion result. The label module is used to judge and compare the value of each digital signal. When it is not 0, the weight signal is retained or read out, otherwise the weight signal is rewritten or not read; The second control module is used to accumulate the weight signals read from the analog storage unit read register and store them in the result register of the analog storage unit after all the bits of a digital signal are judged.

9. The sensing-storage-computing-in-one macro unit circuit according to claim 8, characterized in that: The weight coefficient corresponding to each bit of the digital signal changes according to a linear function, increasing or decreasing by multiples.

10. The sensing-storage-computing-in-one macro unit circuit according to claim 8, characterized in that: Also includes: The encoding module is used to encode the digital signal according to the standard binary code.

11. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The label module sets the label value according to each bit of the digital signal, and determines whether the current integrated sensing, storage and computing macro unit circuit executes the instructions sent by the INS bus based on the stored label value. If the instructions sent by the INS bus are executed, the analog storage and computing unit performs read and write operations.

12. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The analog storage and calculation unit includes 3 read registers, 1 result register, and 2 cache registers; It also includes a processing unit, which obtains each bit of the digital signal in turn. When it is not 0, the analog storage unit is turned on, the weight signal and the result signal stored in the result register are read out, and the weight signal and the result signal stored in the result register are added and written into the cache register; the result of the cache register is written into the result register.

13. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The analog storage and calculation unit includes 3 read registers and 2 result registers; It also includes a processing unit, which judges each bit of the digital signal in turn, and when it is 0, rewrites the weight signal to 0, and adds the weight signals corresponding to each bit of the digital signal and stores them in the result register.

14. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The analog storage and calculation unit includes 1 cache register, 1 result register, and 1 weight signal memory; The external DAC unit sends the weight signal to the weight signal register in turn; Each bit of the digital signal is judged in turn. When it is not 0, the analog storage unit is turned on, the weight signal and the result signal of the result register are read out, and the result is written into the cache register after adding them; the result of the cache register is written into the result register.

15. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The analog storage and calculation unit includes three read registers and one result register, wherein one read register is used to store the sign bit.

16. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: It also includes a sensing unit, wherein the sensing unit, the analog storage and computing unit, the digital storage and computing unit, the iSC bus, the INS bus and the tag module are integrated on the same substrate.

17. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The digital register is implemented by using 3T DRAM, or 6T DRAM, or SRAM.

18. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The tag module includes a comparator circuit inside, which is used to compare the magnitudes of two signals.

19. The sensing-storage-computing-in-one macro-unit circuit according to claim 8, characterized in that: The weight signal and the analog signal are current values.

20. A circuit system, characterized in that: include: The sensing-storage-computing-in-one macro-unit circuit described in any one of multiple claims 8-19 is arranged in an array structure.

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