3D perception circuit, sensing and storage integrated macro unit circuit and system

Abstract

The application discloses a 3D perception circuit, a sensing and storage integrated macro unit circuit, a system and a data processing method. The 3D perception circuit comprises a 3D light signal perception unit, which is used for converting a light flight time into a time pulse signal; a time conversion analog circuit, which is used for converting the flight time of a photon into an analog current signal or an analog voltage signal according to the time pulse signal; the time conversion analog circuit comprises a control module, an integration module and a readout module, wherein the control module is used for controlling the start integration and the end integration of the integration module, and is used for outputting a start signal when a photon is emitted and outputting a stop signal when the time pulse signal is received; the integration module is used for starting to integrate the current after receiving the start signal, and the integration is ended after receiving the stop signal; and the readout module is used for converting the integrated signal into a voltage signal and a current signal required by a later stage of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuits and signal processing, in particular to a 3D sensing circuit, a sensing-storage-computing integrated macro unit circuit and system. BACKGROUND

[0002] With the development of industrial internet, higher requirements are put forward for video acquisition and processing technology. In traditional visual application systems, image sensors collect image information, convert optical signals into electrical signals, and then into digital signals after digital-analog conversion. The image data is processed by an image signal processing unit, and finally output to the processor in the system through a special video interface, and then the processor performs data analysis and makes corresponding control and operation. In recent years, distance measurement sensors have become increasingly popular. Compared with traditional 2D image information of image sensors, distance measurement sensors can provide distance information, which is called 3D information. The mainstream implementation method is to use APD devices and SPAD devices to obtain more accurate distance information by using time of flight (TOF).

[0003] In image processing and laser ranging applications, as shown in Figure 1 , a sensing-storage-computing integrated chip realizes efficient and low-power data processing by integrating sensing, storage and computing functions. Among them, the middle is a processing macro unit (PE) 1 array, which is closely arranged in an array form by PEs, for example, a scale of 1024*1024. Because each PE includes a sensing-storage-computing basic unit, all PEs in the PE array can simultaneously and in parallel process data within each unit. This mode is also commonly known as single instruction multiple data (SIMD), which is commonly used in GPUs. Row control module 5 and column control module 6 are designed in the horizontal and vertical directions of the PE array, respectively. The row control module 5 is used for row selection and related control of the PE array, and the corresponding column control module is used for column selection and related control of the PE array, as well as data readout selection. The PE array also includes peripheral digital module 4, INS bus 41, peripheral analog module 3 and interface module 7.

[0004] As shown in Figure 2 , the PE unit includes a sensing unit (SU). The original signal can come from the detection of the SU, and then the SU can store and operate to convert the analog signal into a digital signal and then store it. For visual sensing units, the SU is divided into 2D and 3D. The light signal of the 3D sensing unit can be detected by using an APD (avalanche photodiode) device or a SPAD (single photon avalanche diode) device. First, the transmitting end transmits laser, and the receiving end SU measures the time from the transmission of the light signal to its return to calculate the distance of the object.

[0005] like Figure 3 As shown, the traditional TOF (Time of Flight) chip ranging principle typically uses a SPAD (Spatial Aperture Deposition Device) and a TDC (Time to Digital Converter) to achieve accurate distance measurement. The high-precision TDC circuit acts as a timer, functioning like a stopwatch. By synchronizing with the transmitter, the TDC allows the light signal received by the SPAD to generate a current within picoseconds (ps) and be detected and recorded by the TDC. TCSPC (Time Correlated Single Photon Counting) technology subdivides the time axis into several time intervals with varying precision. Whenever a sensor pixel detects a single photon event, a digital pulse is generated, and the moment of its generation is recorded. Then, the accumulated single photon count value within the corresponding time interval is incremented by one. After repeating this measurement extensively, a large amount of time data is obtained. These time data are then accumulated in the same way within the corresponding time intervals, thus generating the corresponding single photon count histogram.

[0006] The disadvantages of the traditional approach:

[0007] TDC's design, based on the calculation of light's time of travel, is based on the speed of light being 3 × 10⁻⁶. 8 High-precision distance parameters, measured in meters per second, require high-frequency clocks, placing significant demands on both manufacturing processes and circuitry. Achieving a highly stable distance conversion rate (TDC) necessitates complex circuitry, resulting in a large footprint. The mainstream method uses TCSPC to calculate distance results, requiring substantial SRAM storage for histogram information, thus leading to lower efficiency. Summary of the Invention

[0008] This invention proposes a 3D sensing circuit, a sensing-storage-computing integrated macrocell circuit and system, which can convert the time-of-flight of light into corresponding voltage or current signals, transmit them to the subsequent analog domain storage and computing unit, and perform distance information statistics and further application calculations.

[0009] This invention proposes a 3D sensing circuit, comprising:

[0010] A 3D optical signal sensing unit is used to convert the time of light flight into a time pulse signal;

[0011] The time-conversion analog circuit converts the time of flight of photons into analog current or analog voltage signals based on time pulse signals.

[0012] The time-conversion analog circuit includes: a control module, an integration module, and a readout module.

[0013] The control module is configured to control the start and end of the integration of the integration module, output a start signal when a photon is emitted, and output a stop signal when a time pulse signal is received.

[0014] The integration module is configured to start integrating the current after receiving the start signal and end the integration after receiving the stop signal.

[0015] The readout module is configured to convert the integrated signal into a voltage signal and a current signal required by a subsequent stage of the system.

[0016] Optionally, the integration module comprises:

[0017] The reset switch is configured to reset the integration module after an integration period, with an input end connected to a reset signal and a control end connected to a system reset signal.

[0018] The integration capacitor has a first end connected to an output end of the reset switch and a second end connected to the ground.

[0019] The integration input circuit is composed of a current source and an integration switch, with an input end of the integration switch connected to the current source, an output end connected to the first end of the integration capacitor, and a control end connected to an output of the flip-flop.

[0020] Optionally, the control module is an RS flip-flop, with an S end connected to an output of the pulse modulation unit to input the time pulse signal, an R end connected to the system reset signal, and a Q end connected to a control end of the integration switch.

[0021] Optionally, the control module is a latch, with a CK end connected to an output of the pulse modulation unit to input the time pulse signal, an S end connected to the system reset signal, a D end connected to the ground, and a Q end connected to a control end of the integration switch.

[0022] Optionally, a logic circuit is further connected between the integration input circuit and the RS flip-flop or the latch, and the logic circuit comprises an NAND gate, with a first input end connected to a Q end of the RS flip-flop or the latch, a second input end connected to the system reset signal, and an output end connected to a control end of the integration switch.

[0023] Optionally, the readout module comprises:

[0024] The readout MOS tube has a gate connected to the first end of the integration capacitor and a drain connected to the ground.

[0025] The gate MOS tube has a drain connected to a source of the readout MOS tube, a gate connected to a gate control signal, and a source connected to an output end.

[0026] Optionally, the readout module comprises:

[0027] Readout MOS, the gate is connected with the first end of the integration capacitor, and the source is connected with a high level;

[0028] Gate control MOS, the drain is connected with the drain of the readout MOS, the gate is connected with a gate control signal, and the source is connected with an output end.

[0029] Optionally, the 3D light signal sensing unit comprises a SPAD module and an inverter connected with the output end of the SPAD module.

[0030] Optionally, the 3D light signal sensing unit comprises an APD module and a comparator connected with the APD module, wherein the positive segment of the comparator is connected with the output of the APD module, and the negative segment inputs a modulation signal.

[0031] Optionally, the reset switch and the integration switch MOS have a gate as a control end, a source as an input end, and a drain as an output end.

[0032] Optionally, the 3D light signal sensing unit further comprises a 2D light signal sensing unit, and the output end of the 2D light signal sensing unit is connected with the output end of the 3D light signal sensing unit and the gate of the output MOS.

[0033] Optionally, the source of the output MOS is connected with ground, and the drain outputs a current.

[0034] Optionally, the source of the output MOS is connected with VDD, and the drain outputs a voltage.

[0035] A sensing and storage calculation integrated macro unit circuit of a hybrid sensing circuit.

[0036] A sensing and storage calculation integrated circuit system.

[0037] The application can convert the time of flight of light into corresponding voltage or current signals, facilitate the sensing signal storage and processing of the subsequent storage and calculation unit, and realize the sensing and storage calculation unit with 3D sensing and storage calculation capability. The execution efficiency is increased, and the power consumption is very small. The processing and application of 3D distance information are greatly flexible and rich. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 It is a schematic diagram of the architecture of a sensing and storage calculation integrated circuit system.

[0040] Figure 2 It is a schematic diagram of the architecture of a sensing and storage calculation integrated macro unit circuit.

[0041] Figure 3 is a schematic diagram of an existing 3D perception circuit;

[0042] Figure 4 is a schematic diagram of a 3D perception circuit according to an embodiment of the present application;

[0043] Figure 5a is a schematic diagram of a 3D perception circuit according to a first embodiment of the present application;

[0044] Figure 5b is a schematic diagram of a 3D perception circuit according to a first embodiment of the present application;

[0045] Figure 6 is a schematic diagram of a 3D perception circuit according to a second embodiment of the present application;

[0046] Figure 7 is a schematic diagram of a 3D perception circuit according to a third embodiment of the present application;

[0047] Figure 8 is a schematic diagram of a 3D perception circuit according to a fourth embodiment of the present application;

[0048] Figure 9 is a schematic diagram of a 3D perception circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, so that the advantages and characteristics of the present application can be more easily understood by those skilled in the art, and the protection scope of the present application can be more clearly and definitely defined. Obviously, the embodiments described in the present application are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0050] In the present application, “or” is used to mean “and / or” unless otherwise stated. In addition, the use of the term “including” as well as “comprising” and other forms thereof is not limiting. Also, terms such as “element” or “component” encompass both elements and components comprising a single unit and elements and components that comprise more than one unit.

[0051] The present application provides a memory computing integrated macro unit system, as shown in Figure 1As shown, in this embodiment, the integrated sensing, storage, and computing macrocell circuit is specifically designed in a pixel-level integrated sensing, storage, and computing chip. In the middle is a processing macrocell (PE) array, which consists of PEs arranged closely together in an array, for example, a scale of 1024*1024. The internal structure of the PE will be described in detail in the following specific embodiments of the integrated sensing, storage, and computing macrocell circuit and 3D sensing circuit. Here, only the overall architecture of the integrated sensing, storage, and computing macrocell system is described.

[0052] Because each PE includes a basic sensing and memory computing unit, all PEs in the PE array can process the data within each unit simultaneously and in parallel. Row control modules and column control modules are designed in the horizontal and vertical directions of the PE array, respectively. The row control module is used for row selection and related control of the PE array, while the corresponding column control module is used for column selection and related control, as well as data readout selection. Therefore, in addition to the PE array, the integrated sensing and memory circuit system also includes an analog-to-digital converter (ADC) 2, an external analog module 3, an external digital module 4, a row control module 5, a column control module 6, an interface module 7, and an INS bus 41, all located around the PE array.

[0053] This invention also provides a macrocell circuit integrating sensing, storage, and computation for a distance measurement sensor, such as... Figure 2 As shown, in this invention, the PE includes a 3D sensing (SU) unit or a 2D / 3D hybrid sensing unit. The PE also incorporates a communication interface between adjacent PEs, the Adjacent IF communication unit, which can transmit information from the eight surrounding PEs to the current PE. These modules are connected via a specially designed iSC (In-Sensor Computing Bus), where the analog signal can be either voltage or current. In addition to the iSC bus, the PE also includes a global instruction bus (INS) for overall operation and control of each functional module. Because the INS bus of each PE is controlled by the same global signal, this method achieves the integration of the sensing and computing system. In the PE, signal acquisition and processing are performed in the form of current.

[0054] The sensing circuit within the aforementioned integrated sensing, storage, and computing macrocell system and integrated sensing, storage, and computing macrocell circuit will be described in detail below.

[0055] like Figure 4 As shown, in one embodiment of the present invention, the 3D sensing circuit includes: a 3D optical signal sensing unit 301, used to convert the time of flight of light into a time pulse signal; and a time-to-analog converter (TAC) 303, used to convert the time of flight of photons into an analog current signal or an analog voltage signal according to the time pulse signal.

[0056] The time conversion analog circuit 303 includes a control module, an integration module, and a readout module. The control module controls the start and end of integration of the integration module, outputs a start signal when a photon is emitted, and outputs a stop signal when a time pulse signal is received. The integration module starts integrating the current after receiving the start signal and ends integration after receiving the stop signal. The readout module converts the integrated signal into voltage and current signals required by the subsequent stages of the system.

[0057] In one embodiment, such as Figure 5a As shown, the 3D optical signal sensing unit 301 includes a SPAD module, specifically including a single-photon avalanche diode and a quenching circuit; the pulse modulation unit includes an inverter.

[0058] The control module is an RS trigger RS1, whose S terminal is connected to the output of the 3D optical signal sensing unit and inputs a time pulse signal sp, which serves as the integration end control signal; its R terminal is connected to the system reset signal st, which serves as the integration start control signal; and its Q terminal is connected to the integration switch M. int The control terminal.

[0059] The integration module includes: a reset switch M rx Used to perform an integral on the integration module C after one integration period. sig To perform a reset, its input terminal is connected to the reset signal reset voltage, and its control terminal is connected to the system reset signal st; the integrating capacitor C sig Its first terminal is connected to reset switch M int The output terminal is connected to ground; the integrating input circuit is supplied by current source I. int and integral switch M int Composition, integral switch M int Input terminal connected to current source I int The output terminal is connected to the integrating capacitor C. sig The first terminal, the control terminal, is connected to the output of the RS flip-flop.

[0060] A logic circuit is also connected between the integral input circuit and the RS flip-flop. The logic circuit includes a NOR gate U1, the first input of which is connected to the Q terminal of the RS flip-flop, the second input of which is the system reset signal st, and the output of which is connected to the integral switch M. int The control terminal.

[0061] The readout module includes: a readout MOS transistor M rd Its gate is connected to an integrating capacitor C sig The first terminal has its drain grounded; the MOSFET M is selected. sel Its drain is connected to the readout MOS transistor M. rxThe source of the reset switch MOS transistor M rx and the integral switch MOS transistor M int The control end is the gate, the input end is the source, and the output end is the drain.

[0062] In this embodiment, the RS flip-flop includes two NOR gates, and the relationship of each port is as follows:

[0063] S end = 1, R end = 1, Q end = 0;

[0064] S end = 1, R end = 0, Q end = 1;

[0065] S end = 0, R end = 1, Q end = 0;

[0066] S end = 0, R end = 0, Q end remains the last storage state

[0067] The working principle is further described below. Referring to Figure 5b , the working principle is divided into four stages: an initialization (initial) stage p1, a flight stage p2, a trigger stage p3, and a hold stage p4.

[0068] 1. Initialization stage:

[0069] st = 1, sp = 0, Q = 0

[0070] M int is turned off, M rx is turned on, C sig is reset to the reset voltage V reset .

[0071] The SPAD is reset, is in a recharge state, enters a Geiger mode in a recharge photosensitive state, and is ready to detect photons, and the TAC is reset.

[0072] 2. Flight stage:

[0073] st = 0, sp = 0, Q = 0

[0074] M int is turned on, M rx is turned off, C sig begins to accumulate charges, the SPAD is in a detection state, and the voltage linearly increases with time. When the initial stage enters the flight stage, that is, when the st changes from 1 to 0, the system controls the light emission end to emit a light signal.

[0075] 3. Trigger stage:

[0076] When the initial stage enters the flight stage, that is, the moment st changes from 1 to 0, the system control light emitting end emits a light signal. When the photon is detected by the SPAD and an avalanche current is generated, the trigger signal sp is activated to become 1.

[0077] st = 0, sp = 1, Q = 1

[0078] M int Off, M rx Off, C sig The voltage V = I * T (I is the current, and T is the time from photon emission to detection).

[0079] 4. Hold stage:

[0080] st = 0, sp = 0, Q = 1

[0081] M in Off, M rx Off

[0082] Hold C sig The voltage on the capacitor does not change until the next measurement period.

[0083] Thus, the gate end of the readout MOS tube M rd at the back stage forms a voltage, and by controlling the gate, the on-current of the readout MOS tube is controlled, that is, the signal is converted into a current signal, which can be connected to the iSC (in Sensor Computing) bus in the PE. Further processing is performed on other components connected to the MSC bus, such as operation on analog registers, or storage and operation on digital registers, or transmission to adjacent PEs through Adjacent IF. In this embodiment, TAC is the conversion of a time signal into an analog signal. Unlike the traditional TDC (time to digital converter), TAC does not convert time information into a binary digital signal, but converts time into an analog signal such as a voltage signal or a current signal. The first method proposed in the present application is TCC (time to current converter), which converts the optical time of flight into an analog signal such as a current, and then performs related processing in the PE to realize 3D sensing, computing, and integration.

[0084] Traditional DTOF chips need to design TDC on the SPAD device chip, convert time into digital signals, and then give these signals to the system processing chip. This is low in efficiency, highly dependent on the working frequency of the TDC for distance measurement accuracy, high in power consumption, and low in efficiency. The mainstream TCSPC method calculates the distance result, which needs a large-capacity SRAM to store histogram information, occupies chip area, and is difficult to control power consumption.

[0085] This invention converts the time-of-flight of light into corresponding voltage or current signals, facilitating the storage and processing of sensing signals by subsequent memory units, thus enabling 3D sensing-memory computing units. This increases execution efficiency while consuming very little power. It also greatly expands the flexibility and range of applications for processing 3D distance information.

[0086] like Figure 6 As shown, in the second embodiment of the present invention, a voltage-type TAC, namely TVC (time to voltage converter), is used, which converts the signal into a voltage signal for output.

[0087] The 3D optical signal sensing unit includes a SPAD module, specifically comprising a single-photon avalanche diode, a quenching circuit, and an inverter.

[0088] The control module is an RS flip-flop RS1, whose S terminal is connected to the output of an inverter and receives the input time pulse signal sp; its R terminal is connected to the system reset signal st; and its Q terminal is connected to an integrating switch M. int The control terminal. This module is used to control the start and end of integration of the integration module, outputting a start signal when photons are emitted and a stop signal when a time pulse signal is received.

[0089] The integration module includes: a reset switch M rx Used to perform an integral on the integration module C after one integration period. sig To perform a reset, its input terminal is connected to the reset signal reset voltage, and its control terminal is connected to the system reset signal st; the integrating capacitor C sig Its first terminal is connected to reset switch M int The output terminal is connected to ground; the integrating input circuit is supplied by current source I. int and integral switch M int Composition, integral switch M int Input terminal connected to current source I int The output terminal is connected to the integrating capacitor C. sig The first terminal, the control terminal, is connected to the output of the RS flip-flop.

[0090] A logic circuit is also connected between the integral input circuit and the RS flip-flop. The logic circuit includes a NOR gate U1, the first input of which is connected to the Q terminal of the RS flip-flop, the second input of which is the system reset signal st, and the output of which is connected to the integral switch M. int The control terminal.

[0091] The difference from the aforementioned embodiments is that:

[0092] The readout module includes: a readout MOS transistor M rdIts gate is connected to an integrating capacitor C sig The first terminal has its source connected to a high level; this selects the MOSFET M. sel Its drain is connected to the readout MOS transistor M. rd The drain and gate are connected to the strobe control signal SEL, and the source is connected to the output terminal.

[0093] like Figure 7 As shown, in the third embodiment of the present invention, the 3D optical signal sensing unit includes a SPAD module, specifically including a single-photon avalanche diode, a quenching circuit, and an inverter connected to the output of the SPAD module.

[0094] The integration module includes: a reset switch M rx Used to perform an integral on the integration module C after one integration period. sig To perform a reset, its input terminal is connected to the reset signal reset voltage, and its control terminal is connected to the system reset signal st; the integrating capacitor C sig Its first terminal is connected to reset switch M int The output terminal is connected to ground; the integrating input circuit is supplied by current source I. int and integral switch M int Composition, integral switch M int Input terminal connected to current source I int The output terminal is connected to the integrating capacitor C. sig The first terminal, the control terminal, is connected to the output of the latch LATCH.

[0095] A logic circuit is also connected between the integrating input circuit and the latch. The logic circuit includes a NOR gate U1, the first input of which is connected to the Q terminal of the latch, the second input of which is the system reset signal st, and the output is connected to the integrating switch M. int The control terminal.

[0096] The readout module includes: a readout MOS transistor M rd Its gate is connected to the first terminal of the integrating capacitor Csig, and its drain is grounded; the MOSFET M is selected. sel Its drain is connected to the readout MOS transistor M. rx The source and gate of the circuit are connected to the selection control signal SEL, and the source is connected to the output terminal to output the voltage signal to the iSC bus. The reset switch M rx and integral switch MOSFET M int The control terminal is the gate, the input terminal is the source, and the output terminal is the drain.

[0097] The control module is a latch, with its CK terminal connected to the output of the pulse modulation unit and the input time pulse signal sp; the S terminal connected to the system reset signal; the D terminal grounded; and the Q terminal connected to the control terminal of the integral switch.

[0098] like Figure 8 As shown, in the fourth embodiment of the present invention, the 3D optical signal sensing unit includes an APD module, which specifically includes a photodiode APD and a bias circuit BIAS; and a comparator OP connected to the APD module, the positive segment of which is connected to the output of the APD module, and the negative segment is input to the modulation signal.

[0099] like Figure 9 As shown, the present invention also proposes a 3D sensing circuit, which includes the aforementioned 3D optical signal sensing unit and a 2D optical signal sensing unit PD. The output terminals of the 2D optical signal sensing unit and the 3D optical signal sensing unit are connected together to the gate of the output MOS transistor M1. The source of the output MOS transistor M1 is grounded, and the drain output current I... pix .

[0100] In another embodiment, the source of the output MOSFET M1 is connected to VDD, and the drain outputs voltage.

[0101] The present invention also proposes a data processing method utilizing the above-mentioned 3D sensing circuit.

[0102] This invention proposes a new circuit principle and structure to realize the detection and perception of distance information in a specific scene. In addition to obtaining a 3D image with a certain resolution, the 3D perception circuit designed in this invention is organically combined with the previously designed sensing-memory-computing macrocell to realize a 3D sensing-memory-computing circuit. It directly performs calculation and processing in the analog signal domain, which greatly improves latency, power consumption and efficiency.

[0103] The 3D sensing and computing structure proposed in this invention can provide methodological and circuit support for subsequent 3D processing, such as edge extraction, feature point extraction, and tracking of 3D information.

[0104] This design proposes a new structure and principle for detecting and sensing distance information. In addition to obtaining a 3D information map with a certain resolution, it works with a processing unit to perform distance information application calculations, realizing 3D-related sensing and computing applications. The features of this invention are small area and high distance measurement efficiency.

[0105] The 3D distance information sensing and storage computing implementation method of the present invention breaks the traditional von Neumann architecture implementation method, and integrates single-chip 3D sensing and signal processing for more efficient execution.

[0106] The above merely illustrates the embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, such as the mutual combination of technical features between embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A 3D sensing circuit, characterized by, Comprising: a 3D optical signal sensing unit for converting the optical time of flight into a time pulse signal; a time conversion analog circuit for converting the time of flight of the photon into an analog current signal or an analog voltage signal according to the time pulse signal; the time conversion analog circuit comprises a control module, an integration module and a readout module, wherein the control module is used to control the start and end of integration of the integration module, and is used to output a start signal when the photon is emitted and a stop signal when the time pulse signal is received; the integration module is used to start integrating the current after receiving the start signal and end the integration after receiving the stop signal; the readout module is used to convert the integrated signal into a voltage signal and a current signal required by the system back-end; The integration module includes: a reset switch M rx Used to perform an integral on the integration module C after one integration period. sig To perform a reset, its input terminal is connected to the reset signal reset voltage, and its control terminal is connected to the system reset signal st; the integrating capacitor C sig Its first terminal is connected to reset switch M int The output terminal is connected to ground; the integrating input circuit is supplied by current source I. int and integral switch M int Composition, integral switch M int Input terminal connected to current source I int The output terminal is connected to the integrating capacitor C. sig The first terminal, the control terminal, is connected to the output of the RS flip-flop; The integral input circuit is also connected with a logic circuit, the logic circuit includes an NOR gate U1, the NOR gate U1 has a first input end and a second input end, the control module is an RS flip-flop, the first input end is connected with the Q end of the RS flip-flop, the second input end inputs a system reset signal st, and an output end is connected with the control end of the integral switch M int . The readout module comprises a readout MOS transistor M rd , a gate of which is connected to a first end of the integrating capacitor C sig , and a drain of which is connected to ground; a gating MOS transistor M sel , a drain of which is connected to a source of the readout MOS transistor M rx , a gate of which is connected to a gating control signal SEL, and a source of which is connected to an output end for outputting a voltage signal to the MSC bus; and a reset switch MOS transistor M rx and an integrating switch MOS transistor M int , a control end of which is a gate, an input end of which is a source, and an output end of which is a drain.

2. The 3D sensing circuit according to claim 1, wherein the control module is an RS flip-flop, the S terminal of which is connected to the output of the pulse modulation unit and inputs the time pulse signal, the R terminal of which is connected to the system reset signal, and the Q terminal of which is connected to the control terminal of the integration switch.

3. The 3D sensing circuit according to claim 1, wherein the control module is a latch, the CK terminal of which is connected to the output of the pulse modulation unit and inputs the time pulse signal, the S terminal of which is connected to the system reset signal, the D terminal of which is connected to ground, and the Q terminal of which is connected to the control terminal of the integration switch.

4. The 3D sensing circuit according to claim 2 or 3, characterized in that, a logic circuit is further connected between the integration input circuit and the RS flip-flop or the latch, the logic circuit comprising an NOR gate, the first input terminal of the NOR gate being connected to the Q terminal of the RS flip-flop or the latch, the second input terminal of the NOR gate inputting the system reset signal, and the output terminal of the NOR gate being connected to the control terminal of the integration switch.

5. The 3D sensing circuit according to claim 2 or 3, characterized in that, the 3D optical signal sensing unit comprises a SPAD module and an inverter connected to the output terminal of the SPAD module.

6. The 3D sensing circuit according to claim 2 or 3, characterized in that, the 3D optical signal sensing unit comprises an APD module and a comparator connected to the APD module, the positive terminal of the comparator being connected to the output of the APD module, and the negative terminal of the comparator inputting the modulation signal.

7. The 3D sensing circuit of claim 1, wherein, a 2D optical signal sensing unit is further included, the output terminal of the 2D optical signal sensing unit being commonly connected to the gate of an output MOS transistor together with the output terminal of the 3D optical signal sensing unit.

8. The 3D sensing circuit of claim 7, wherein, the source of the output MOS transistor is connected to ground, and the drain of the output MOS transistor outputs current.

9. The 3D sensing circuit of claim 7, wherein, the source of the output MOS transistor is connected to VDD, and the drain of the output MOS transistor outputs voltage.

10. A sensing-computing integrated macro cell circuit comprising the 3D sensing circuit according to any one of claims 1-9.

11. A sensing-computing integrated circuit system comprising the sensing-computing integrated macro cell circuit according to claim 10.

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