Device for protecting processor, processor and method for protecting processor

Abstract

The invention provides a device for protecting a processor, the processor and a method for protecting the processor, and the device for protecting the processor comprises an input interface which is configured to monitor program code instructions processed by the processor, and one or more of the program code instructions comprise one or more error detection bits; and a protection circuit configured to detect one or more errors in the program code using the error detection bits, and initiate a corresponding action when an error is detected in consideration of an abnormal event occurring in the processor.

Description

Technical Field

[0001] The present application relates to a device for protecting a microprocessor, a processor and a method for protecting a microprocessor, and more particularly to an in-band error detection method and system for a microprocessor circuit. Background Art

[0002] Fault injection attacks are a family of techniques used to access, analyze, or extract information from secure circuits, such as encryption circuits. Fault injection attacks typically involve causing a circuit or a portion of it to change its logical state and alter its behavior, thereby helping an attacker penetrate the circuit or the information it stores. For example, a fault injection attack can be launched by physically contacting a signal line, applying a high-powered laser or electromagnetic pulse, or inducing a fault on a power supply or other external interface. Various techniques are known in the art for detecting and / or mitigating fault injection attacks. Summary of the invention

[0003] The invention embodiments described herein provide a device for protecting a processor. The device includes an input interface and a protection circuit. The input interface is configured to monitor program code instructions processed by the processor. One or more program code instructions include one or more error detection bits. The protection circuit is configured to use the error detection bits to detect one or more errors in the program code, and to initiate corresponding actions when an error is detected, taking into account abnormal events occurring in the processor.

[0004] In certain embodiments, the program code comprises a program code paragraph, and this program code paragraph has a deterministic program code flow, and comprises at least one error detection bit calculated on the part of this program code paragraph. The protection circuit is configured to the abnormal event that occurs when the processor processes this program code paragraph. In an exemplary embodiment, when the abnormal event occurs, the protection circuit is configured to terminate the inspection of the error in the program code paragraph. In another embodiment, the protection circuit is configured to delay the processing of the abnormal event by the processor, at least until the inspection of the error in the program code paragraph is completed.

[0005] In another alternative embodiment, in response to an abnormal event, the protection circuit is configured to suspend error checking and save the checking state, and resume the checking from the saved state after the processor handles the abnormal event.

[0006] In a disclosed embodiment, when an error is detected, the protection circuit is configured to detect a fault injection attack.

[0007] In a certain embodiment, one or more of the error detection bits are inserted into reserved bit positions in the program code instructions, and the protection circuit is configured to extract the error detection bits from the reserved bit positions.

[0008] In another embodiment, one or more of the error detection bits are inserted into actually reserved bit positions in the program code instructions, which do not affect the execution of the program code instructions, and the protection circuit is configured to extract the error detection bits from these actually reserved bit positions.

[0009] In another embodiment, one or more of the error detection bits are inserted into bit positions in one or more jump instructions that are designated to indicate a jump offset, but the processor is configured to ignore those bit positions.

[0010] In another embodiment, one or more of the error detection bits are inserted into one or more specific program code instructions added to the program code specifically for error detection, and the protection circuit is configured to recognize these specific program code instructions and extract the error detection bits therefrom.

[0011] In one embodiment, the protection circuit is configured to store a definition of the location of the error detection bit in the program code instruction and extract the error detection bit from the program code instruction according to the definition.

[0012] In one exemplary embodiment, a given set of one or more error detection bits is calculated over at least a portion of a selected program code instruction, and the error detection bits are inserted into the given program code instruction. In another embodiment, one or more of a given set of error detection bits are calculated over selected bits in the program code, and at least one of the selected bits is located in a different program code instruction than at least one of the selected error detection bits.

[0013] In some embodiments, the apparatus further includes an insertion circuit configured to insert one or more error detection bits into one or more program code instructions provided to the processor for processing.

[0014] In addition, according to one embodiment described herein, a processor including an instruction pipeline and a protection circuit is provided. The instruction pipeline is configured to fetch and execute program code, the program code including program code instructions, wherein one or more program code instructions include one or more error detection bits. The protection circuit is configured to at least monitor the error detection bits in the program code instructions, use the error detection bits to detect one or more errors in the program code under consideration of abnormal events occurring in the processor, and initiate corresponding actions when an error is detected.

[0015] According to an embodiment described herein, a method for protecting a processor is also provided. The method includes program code instructions for monitoring processor processing, wherein one or more program code instructions include one or more error detection bits. Under the situation of taking into account the abnormal events occurring in the processor, these error detection bits are used to detect one or more errors in the program code. When an error is detected, a corresponding action is started.

[0016] In some embodiments, the method includes a program code section having a deterministic program code flow and including at least one of error detection bits calculated on a portion of the program code section; wherein the processing of the abnormal event includes a corresponding action for the abnormal event occurring when the processor processes the program code section.

[0017] In one embodiment, the method's corresponding action to the abnormal event includes suspending the checking of errors in the program code section.

[0018] In one embodiment, the method of handling an exception event includes delaying handling of the exception event of the processor at least until an error check in a program code section is completed.

[0019] In one embodiment, the method taking into account the exception event includes suspending the error checking in the program code section when the exception event occurs; and resuming the checking from a saved state after the processor handles the exception event.

[0020] The present application will be more fully understood through the following detailed description of the embodiments and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram schematically showing a security processor according to an embodiment of the present application;

[0022] Figure 2 is a flow chart schematically showing a method for protecting a processor according to an embodiment of the present application;

[0023] Figure 3 and Figure 4 is a block diagram schematically showing a security processor according to an alternative embodiment of the present application.

[0024] Explanation of symbols

[0025] 20: Security processor

[0026] 24: Instruction pipeline

[0027] 28: Protection circuit

[0028] 32: Memory

[0029] 36: Capture unit

[0030] 40: Decoding unit

[0031] 44: Execution unit

[0032] 48: EDC Insertion Circuit

[0033] 50: Interface

[0034] 52: Lookup Table (LUT)

[0035] 56: EDC check logic

[0036] 60,64 68,72,76,80,84: Steps

[0037] 86: Security Processor

[0038] 88: Delay Circuit

[0039] 90: Security processor

[0040] 92: EDC check stack DETAILED DESCRIPTION

[0041] Embodiments of the present application provide a method and apparatus for protecting a processor from bit errors in program code instructions. Errors in program code instructions may be caused by fault injection attacks, which attempt to capture sensitive information by causing the processor to operate abnormally. In general, the disclosed technology can be used to protect the processor from errors caused by any hostile or harmless mechanism. In this article, the term "processor" refers to various types of processors, such as central processing units (CPUs), microcontroller units (MCUs), embedded controllers, processing cores, etc.

[0042] The processor typically includes an instruction pipeline that is configured to fetch program code instructions from a memory and execute the fetched instructions. Each program code instruction is taken from the processor's specified instruction set architecture (ISA) and is represented and stored in memory as a set of bits. These bits define the instruction's operation code (opcode) and may also define one or more operands. It is understood that a bit error in any bit of an instruction may lead to unpredictable results, which is highly undesirable.

[0043] Certain embodiments of the present application provide a protection circuit that can protect a processor from bit errors. The protection circuit monitors one or more error detection bits inserted into one or more program code instructions. When an error in the program code is detected using the error detection bits, the protection circuit initiates an appropriate response action.

[0044] In some embodiments, the protection circuit is implemented as integrated into the processor. In an alternative embodiment, the protection circuit is located outside the processor. In some embodiments, the error detection bit is pre-inserted into the program code instruction, for example, by a compiler or a post-processor, so that the program code stored in the memory already contains the error detection bit. In an alternative embodiment, the error detection bit is inserted into the program code instruction during the execution phase. For example, a dedicated insertion circuit can insert the error detection bit into the program code instruction retrieved from the memory and provide the program code instruction to the processor.

[0045] In some embodiments, error detection bits are inserted into existing bit positions in instructions without modifying the specific ISA of the processor and without expanding the size ("width") of the instructions. This feature is important, for example, to help maintain the instruction throughput of the processor, while also helping with backward compatibility with legacy processors. Various techniques for reusing existing bit positions to hold error detection bits are described herein.

[0046] In certain embodiments, error detection is applied independently according to each instruction. In these embodiments, the error detection bit in a specific instruction is only calculated on (partial or all) bits of the same instruction. In other embodiments, error detection is applied to cross instruction boundaries, for example, across the entire program code paragraph. In certain embodiments, in order to perform error detection, additional commands can be inserted in the program code.

[0047] In some embodiments, the protection circuit detects errors in the program code when an abnormal event (such as an interrupt) occurs in the processor. The abnormal event (also referred to as "exception") usually causes the processor to jump to a specified address to execute the program code to handle the exception. After the exception is handled, the processor returns to the normal program flow.

[0048] For example, consider a code segment that (i) has a defined code flow and (ii) includes one or more error detection bits that have been computed over at least a portion of the code segment. Unless exceptions are taken into account, if an exception occurs during the processing of the code, the error detection of the code segment will be disrupted and the error may not be detected.

[0049] In various embodiments, the disclosed protection circuit utilizes various techniques to complete error detection of the program code segment, even if an abnormal event occurs during processing. In an exemplary embodiment, the protection circuit delays the processor's processing of the abnormal event, at least until the error check in the program code segment is completed. In another embodiment, the protection circuit suspends error checking when encountering an abnormality and saves the current check state. After the abnormal event processing is completed, the protection circuit resumes error detection from the pause point (i.e., the saved state).

[0050] The embodiments described herein mainly relate to parity checking, but any other suitable error detection scheme may be used in other embodiments. For the sake of brevity, the error detection bits are also referred to as error detection code (EDC) bits herein.

[0051] The techniques disclosed herein provide an efficient and cost-effective means for protecting processors from bit errors in program code instructions.

[0052] System Description

[0053] Figure 1 Schematically shows a block diagram of the security processor 20 of the embodiment of the present application. Figure 1 In the embodiment of FIG. 1 , the secure processor 20 includes an instruction pipeline 24 for fetching and executing program code, a memory 32 for storing program code, and a protection circuit 28 for protecting the processor from bit errors that may occur in the program code.

[0054] The instruction pipeline 24 includes a plurality of pipeline stages. In the present example, the instruction pipeline 24 includes a fetch unit 36, a decode unit 40, and one or more execution units 44. The fetch unit 36 ​​retrieves program code instructions from the memory 32. The decode unit 40 decodes the fetched instructions. The execution unit 44 executes the determined instructions. The execution unit 44 may include, for example, one or more load-store units (LSUs), arithmetic logic units (ALUs), branch units, or any other suitable execution units.

[0055] The protection circuit 28 uses error detection bits (also referred to as EDC bits) inserted at predefined bit positions in one or more program code instructions to identify bit errors in the program code. As used herein, the terms "bit errors in program code" and "bit errors in program code instructions" refer to errors introduced into the program code, either maliciously or unintentionally, after the program code is provided to the system or processor (e.g., after the original program code has been stored in the memory 32). In other words, in the disclosed technology, the original program code provided to the system or processor (e.g., the program code initially stored in the memory 32) is not affected by errors mitigated by the disclosed technology.

[0056] The following description mainly takes parity check bits as an example. When parity check is used, each parity check bit is calculated based on a set of predefined bits of the program code instruction. If the number of "1"s in the set is odd, the parity check bit is set to "1"; if the number of "1"s in the set is even, the parity check bit is set to "0". Parity check can be used to detect multiple errors, such as errors in Hamming code. Other error detection schemes, such as CRC, hash, SHA, multi-bit parity check, or any other suitable scheme, can be used to implement the disclosed technology.

[0057] In some embodiments, the program code stored in the memory 32 already includes EDC bits. For example, these EDC bits can be inserted by a compiler, or by a post-processor that processes the compiled program code generated by the compiler. In other embodiments, the program code stored in the memory 32 does not include EDC bits, and the security processor 20 further includes an EDC insertion circuit 48, which inserts EDC bits into the program code during the execution phase. In one embodiment, the EDC insertion circuit is arranged in a row between the memory 32 and the instruction pipeline 24, and inserts EDC bits into one or more program code instructions retrieved from the memory by the capture unit 36.

[0058] exist Figure 1 In an embodiment of the present invention, protection circuit 28 receives program code instructions through instruction pipeline 24 using interface 50. Protection circuit 28 generally maintains a definition of an EDC scheme, for example, a definition of (i) the location of EDC bits in the program code instructions, and a definition of (ii) the location of corresponding bits for calculating the EDC bits. Using this definition, protection circuit 28 verifies whether the value of the EDC bits represents one or more bit errors in the program code.

[0059] In this example, the EDC scheme defines that each program code instruction contains at most one EDC bit. When a program code instruction contains an EDC bit, the EDC bit is calculated as a parity check of all other bits in the instruction, or is calculated as a parity check of a predefined portion of the instruction. In this example, the protection circuit 28 includes a lookup table (LUT) 52, which represents the EDC scheme. For each instruction monitored by the interface 50, the LUT 52 produces two outputs: (i) an "EDC presence" bit indicating whether the instruction contains an EDC bit, and (ii) an "EDC position" bit indicating the position of the EDC bit. In other embodiments, the LUT 52 can have any other suitable structure and output to support other types of EDC schemes. In addition, the EDC scheme can be defined and stored using any other suitable circuit or data structure, and does not necessarily have to use a lookup table.

[0060] The protection circuit 28 further includes an EDC check logic 56, which verifies whether the EDC bit indicates any bit error in the program code. In this example, the EDC check logic 56 receives the program code instruction monitored via the interface 50 as input. For each instruction, the EDC check logic 56 receives the corresponding "EDC exists" and "EDC position" bits generated by the LUT 52. For a given instruction, if the corresponding "EDC exists" bit is "1", the EDC check logic 56 calculates the parity check (odd / even) of the appropriate bit in the instruction and compares it with the bit value at the "EDC position". If the parity check (odd / even) of the appropriate bit in the calculated instruction does not match the bit value at the "EDC position", the EDC check logic 56 determines that a bit error has occurred in the instruction and initiates an appropriate response action.

[0061] In various embodiments, the EDC check logic 56 can initiate a variety of different response actions. For example, the EDC check logic 56 can issue an alarm indicating that a fault injection attack may be ongoing. In addition, the EDC check logic 56 can also disable the processor or part thereof, erase sensitive data from the processor, or initiate any other appropriate operation.

[0062] like Figure 1As shown, the "EDC position" bit is also provided to the instruction pipeline 24 (usually provided to the decoding unit 40). In some embodiments, the components of the instruction pipeline 24 (e.g., the decoding unit 40) may need to know the position of the EDC bit in the instruction in order to ignore it. This aspect is further explained in detail below. In some embodiments, the EDC check logic 56 also receives a "jump" input, which is triggered when the currently monitored instruction is a jump instruction or a jump destination instruction (a "target" or "landing" instruction to which a jump instruction jumps). In some embodiments, the EDC check logic 56 also receives an "exception" input that is triggered when an exception occurs in the processor. The "jump" input is used to mark the boundaries between individual program code paragraphs, where the EDC bits are checked separately. The "exception" input is used to temporarily disable or suspend error detection checks. These aspects will also be explained in further detail below.

[0063] Figure 1 The configuration of the security processor 20 and the protection circuit 28 shown in FIG. Figure 3 and Figure 4 The configurations of the security processor and the protection circuit shown in the are all example configurations depicted purely for the purpose of clarifying the concepts. In alternative embodiments, any other suitable configurations may be used.

[0064] For example, in Figure 1 , memory 32 is shown as part of the processor. In alternative embodiments, memory 32 may be external to the processor and / or accessible via an appropriate instruction cache.

[0065] Another example, in Figure 1 In the embodiment of the present invention, the protection circuit 28 is shown as part of the security processor 20. Alternatively, the protection circuit 28 can be external to the processor. Similarly, the EDC insertion circuit 48 (if used) can be external to the processor. Therefore, the disclosed technology is suitable for use with conventional general-purpose processors by coupling external circuits.

[0066] As another example, although in Figure 1In one embodiment, the instruction is provided to the protection circuit 28 from the output of the fetch unit 36, but the disclosed technique is not limited to this configuration. In other embodiments, the interface 50 may transmit the instruction to the protection circuit from any other appropriate point in the instruction pipeline 24, for example, from the output of the decode unit 40, or even from the output of the execution unit 44. In one embodiment, if the instruction is retrieved from a later stage of the pipeline, the protection circuit 28 may need to reconstruct the original format of the instruction after the instruction is fetched (i.e., the format in which the instruction is stored in the memory 32) in order to associate the EDC bit with the other bits of the instruction. In an alternative embodiment, the compiler or post-processor may insert the EDC bit into the program code while taking into account the structure of the instruction at the sampling point of the interface 50. When using this technique, care should be taken that the components of the instruction pipeline 24 do not discard the EDC bit before reaching the interface 50.

[0067] Also, for the sake of clarity, the structure of the instruction pipeline 24 is highly simplified. Real processors may include more complex instruction pipelines. In addition, the disclosed techniques are not limited to use with pipeline processors, and can be used with processors having any other suitable microarchitecture. For the sake of clarity, elements that are not necessary for understanding the disclosed techniques are generally omitted.

[0068] In various embodiments, any circuit disclosed (e.g., in Figure 1 , Figure 3 and Figure 4 Any circuits shown in the drawings) may be implemented using any suitable hardware or firmware, for example using one or more discrete components, one or more application specific integrated circuits (ASICs) and / or one or more field programmable gate arrays (FPGAs).

[0069] In some embodiments, the protected processor may include a general purpose processor that is programmed with software to perform the functions described herein. For example, the software may be downloaded to the processor in electronic form over a network, or alternatively or additionally, the software may be provided and / or stored on a non-transitory tangible medium, such as a magnetic, optical or electronic memory.

[0070] Figure 2 is a flow chart schematically showing a method for protecting a security processor 20 according to an embodiment of the present application. The method begins with a capture step 60, where the capture unit 36 ​​captures one or more program code instructions from the memory 32. The acquired instructions are provided to the decoding unit 40 and the protection circuit 28. Therefore, the flow of the method is divided into two parallel branches.

[0071] At decode step 64, decode unit 40 decodes the fetched instruction. At execute step 68, execution unit 44 executes the instruction and method flow loops back to step 60 to fetch the next instruction from memory.

[0072] In an identification step 72, the protection circuit 28 identifies which program code instructions contain EDC bits and the locations of the EDC bits in those instructions. In an extraction step 76, the protection circuit 28 extracts the EDC bits from the instructions. In an EDC check step 80, the protection circuit 28 checks whether the value of the EDC bits indicates any bit errors in the program code instructions.

[0073] If the EDC bit does not indicate an error (“EDC passed”), the method flow loops back to step 60. Otherwise, if the EDC bit indicates a bit error (“EDC failed”), the protection circuit 28 initiates a corresponding action at action triggering step 84.

[0074] Figure 2 The process is an example process described purely for the purpose of clarifying the concept. In alternative embodiments, any other appropriate process may be used.

[0075] For example, the security processor 20 may support a "safe" mode of operation in which EDC insertion and checking are enabled, and a "normal" mode of operation in which EDC insertion and checking are disabled. For example, the modes may be configured based on program code address ranges.

[0076] EDC bit location

[0077] In various embodiments, the EDC schemes used by the protection circuit 28 may be different from one another, such as the location of the EDC bits in the program code instructions and the location of the EDC bits in the entire program code.

[0078] In some embodiments, one or more EDC bits are inserted (e.g., by a compiler or post-processor, or by EDC insertion circuit 48) at bit positions that are defined as "reserved" according to the processor's ISA. Bit values ​​at "reserved" positions are ignored by the instruction pipeline 24, so modifying these bit values ​​has no effect on the execution of the program code.

[0079] In some embodiments, one or more EDC bits are inserted (e.g., by a compiler or postprocessor, or by EDC insertion circuit 48) at "de-facto reserved" bit positions. In the present context, the term "de-facto reserved bit positions" refers to bit positions that are not defined as reserved in the processor's ISA, but are still ignored in the instruction pipeline 24 and have no effect on program execution. A non-limiting example is address bits that exceed the applicable address range of the processor. For example, assume that the instruction structure specifies the use of n-bit addresses, but in the actual program code, only n-1 bits of the address space are used. In this case, even if the nth bit of the address is not formally defined as a "reserved" bit in the ISA, it can be safely used as an EDC bit.

[0080] In another embodiment, some ISAs support multiple jump instructions that differ in the maximum size of the jump (the size of the jump offset). This feature helps reduce the size of instructions when performing jumps with small offsets. In some embodiments, the compiler or post-processor is configured to use jump instructions where the jump address or offset is defined in the instruction operation operand (without using a register if possible), and the offset size is larger than the actual size required so that one or more of the most significant bits (MSBs) of the offset value can be used as EDC bits. In these embodiments, the processor should also be aware of this convention so that the instruction pipeline 24 (e.g., the branch execution unit) will ignore the EDC bits.

[0081] For example, consider an ISA that supports two types of jump instructions: a "normal" jump that allows a maximum jump offset of ±24 bits, and a "close" jump that allows a maximum jump offset of ±16 bits. In one embodiment, the compiler or post-processor is configured to: (i) always allow only a maximum jump offset of ±16 bits, but (ii) always use the "normal" jump instruction type. This configuration leaves the 8 most significant bits of the jump offset unused, but in fact reserved for use as EDC bits (e.g., inserted by the compiler, post-processor, or by EDC insertion circuitry 48).

[0082] Additionally or alternatively, the compiler or postprocessor may use various other instruction allocation settings to create effectively unused bit locations that can be used for EDC. Additionally or alternatively, the compiler or postprocessor may generally be set up to favor instructions with redundancy. This feature creates more effectively unused bits that can be used for EDC. The features for such instructions may be enabled, disabled, or otherwise configured to achieve an appropriate safety / efficiency tradeoff.

[0083] In certain embodiments, a compiler or postprocessor adds one or more special program code instructions in the program code for EDC, and inserts the EDC bit into these instructions. For example, a compiler or postprocessor can regularly generate such no operation (No Operation Performed; NOP) instructions in the program code. The protection circuit 28 in these embodiments is configured to identify special instructions and extract the EDC bit therefrom. For example, the special instructions may include a "no operation" (NOP) command that is designated as ignored by the processor in the ISA, but usually has some space for the bit that is used to retain or actually retain.

[0084] In addition or as an alternative, instructions can be set as "actual NOP" or "NOP-like" by coordinating with the protection circuit 28 and with the compiler or postprocessor. For example, a certain register of the processor can be reserved and not used in the actual program code. For example, the compiler or postprocessor can regularly generate instructions in the program code that refer to this register and insert EDC bits in these instructions. The protection circuit 28 in these embodiments is configured to identify instructions related to the register and extract the EDC bit therefrom. Various other coordination schemes can be used to dedicate various instructions to EDC in a manner that does not affect the normal execution of the program code.

[0085] When NOP or NOP-like instructions are used, a hybrid scheme may also be used in which a compiler or post-processor generates NOP or NOP-like instructions (e.g., at regular intervals) but does not insert EDC bits into those instructions. In operation, EDC insertion circuitry 48 inserts EDC bits into one or more NOP or NOP-like instructions generated by the compiler or post-processor.

[0086] The above scheme is selected as an example only. In other embodiments, any other suitable bit position can be used to store the EDC bit.

[0087] Code coverage of EDC solution

[0088] In various embodiments, the EDC schemes used by the protection circuit 28 may be different from each other. For example, portions of the program codes protected by the EDC may be different.

[0089] For example, in some embodiments, the EDC scheme is "intra-instruction", that is, the EDC bits inserted into a given instruction are only calculated on one or more other bits of the same program code instruction (and thus protect the program code). For example, the EDC bits can be calculated (e.g., by a compiler or post-processor, or by EDC insertion circuitry 48) as a parity check of all other bits in the instruction, or calculated on a predefined portion of the instruction. In other embodiments, the EDC scheme crosses instruction boundaries, which means that the selected EDC bits can be calculated on multiple bits selected from multiple program code instructions (and thus protect these bits).

[0090] In certain embodiments, the EDC scheme can protect the entire program code, or at least the vast majority of the program code. For example, consider an embodiment in which the program code is divided into multiple sections, and a group of one or more EDC bits are inserted into each section (e.g., by a compiler, a postprocessor, or by an EDC insertion circuit 48). Each group of one or more EDC bits is calculated based on the entire program code section in which it is located (therefore protecting all parts of this section).

[0091] It is understandable that, in order to make the above scheme work properly, each protected program code paragraph should have deterministic (that is, not dependent on data or other variable or unpredictable) program code flow. In this context, the term "program code paragraph with deterministic program code flow" means that any execution of the program code paragraph will always follow the same instruction sequence to execute in the same order. The order in question is the order in which the instructions arrive at the protection circuit to perform the EDC check. For example, if the output of the capture unit is performed EDC check, the processor pipeline is allowed to decode and execute out-of-order instructions. On the other hand, if the capture is performed out of order, the instructions should be reordered (for example, processed by the protection circuit) before the EDC calculation and check.

[0092] In exemplary embodiments, this regulation is realized by defining each paragraph as the paragraph between continuous jump and / or jump destination instruction.So-called "jump destination" instruction is the instruction that is jumped to by jump instruction in the program code.In other words, each group of one or each group of multiple EDC bits is calculated (therefore protecting this paragraph) according to the program code paragraph that does not contain any jump or jump destination instruction.In this context, "does not contain" this term has been excluded from the first instruction and the last instruction of the paragraph, and these instructions are normally jump or jump destination instruction.

[0093] In one embodiment, conditional branch instructions, unconditional jump instructions and return instructions are all considered as jump instructions for dividing program code into sections. When divided in this way, each protected program code section will not traverse any jump instructions or jump destination instructions.

[0094] In some embodiments, each group of one or more EDC bits is calculated based on (and therefore protects) a corresponding program code section whose starting point is no earlier than (but may be later than) a previous jump or jump destination instruction and whose ending point is no later than (but may be earlier than) a next jump or jump destination instruction.

[0095] In order to consider the jump destination instruction, in some embodiments, the compiler (or post-processor) analyzes the program code and marks various possible jump destination instructions. In different embodiments, various techniques can be used to identify the jump destination instruction.

[0096] In one embodiment, a strategy can be defined in which a compiler or postprocessor ensures that all jump instructions jump to a specific type of instruction inserted into the program code specifically for this purpose (that is, all jump destination instructions are specific and recognizable types). When using this convention, any jump instruction and a specific type of instruction can be used as the boundary of a paragraph. For example, this strategy can specify that all jump destination instructions are NOP instructions, or instructions for a specific temporary register. Another example is that the strategy can specify that the compiler or postprocessor is only allowed to jump to an address subset (for example, only allow jumping to addresses with N least significant bits (Least Significant Bit; LSB) being 0). In addition or as an alternative, any other appropriate convention can be used to define the jump destination instruction. Redundant jump destination instructions can usually be defined because this definition only leads to more detailed segmentation into smaller paragraphs. However, if the jump destination instruction that is actually used for segmentation is missing, there will be problems.

[0097] In addition, other methods of dividing the program code into sections are also feasible, as long as each program code section has a deterministic program code flow.

[0098] In some embodiments, a set of one or more EDC bits (e.g., inserted by a compiler or postprocessor, or EDC insertion circuit 48) is inserted into each jump instruction and jump destination instruction, and is calculated based on the code segment (thus protecting the segment) since the previous jump / jump destination instruction. Such a scheme can protect most program code.

[0099] In some embodiments, a set of one or more EDC bits (e.g., inserted by a compiler or postprocessor, or EDC insertion circuitry 48) is inserted into at least one instruction in each code section having deterministic code flow (e.g., within each code section, anywhere between consecutive jump / jump destination instructions). The EDC bit in a given code section is calculated over (and thus protects) a plurality of selected bits in that section, which may include bits in the instruction preceding the EDC bit and / or bits in the instruction following the EDC bit.

[0100] In another embodiment, a given instruction (e.g., a jump or jump destination instruction, used to distinguish adjacent program code segments) includes two types of EDC bits. One EDC bit is calculated on the instruction itself (thereby protecting the instruction). The second EDC bit is calculated from the beginning of the program code segment since the previous jump / jump destination instruction (thereby protecting the segment).

[0101] In the above embodiment, the protection circuit 28 may use the EDC check logic 56 ( Figure 1 ) input " jump " to mark the beginning of the protected program code paragraph. In these embodiments, when each input " jump " was triggered, EDC check logic 56 would reset and restart to calculate EDC (for example: parity check).

[0102] Another reason that may cause non-deterministic program code flow is an exception in the security processor 20. Therefore, in some embodiments, the protection circuit 28 triggers the EDC check logic 56 ( Figure 1 ) in the input “abnormal event”. When the input “abnormal event” is triggered, the EDC check logic 56 suspends the current EDC calculation and suspends error checking until the next program code section with a deterministic program code flow begins (for example, until the next input “jump” is triggered).

[0103] When EDC has abnormal events

[0104] In certain embodiments, protection circuit 28 detects errors in program code when an abnormal event occurs in the processor. In the context here, "abnormal event" (or "abnormal" for short) refers to any event that interrupts the normal execution of the main program code. Some abnormal instructions processors suspend the execution of the main program code and jump to the program code that executes the predefined processing exception. Once the abnormal processing is completed, the processor will return to the point where the execution is suspended in the main program code. Typical abnormal event examples include interrupts (masked or non-masked). Other examples include faults, traps, aborts, breakpoints, etc.

[0105] When the program code section is carried out to error detection, an abnormal event may cause problems, because the abnormal event can interrupt the expected deterministic program code flow. A mode of handling exception is to terminate the error detection to the corresponding program code section, as mentioned above. Such a solution will not be able to detect the error in the program code section, but on the other hand, can prevent the warning false alarm caused by the exception. In certain embodiments, protection circuit 28 uses the technology of successfully completing the error detection to the program code section under the existence of abnormal situation. Therefore, the error detection coverage of program code will not be affected because of the abnormal event.

[0106] Figure 3 is a block diagram schematically showing a security processor 86 according to an embodiment of the present application. The security processor 86 is similar to the above Figure 1 The security handler 20 in , but it differs in the way it handles exceptions. Figure 3 The technique is best suited for exception handling (such as masked interrupts) that can tolerate some delay.

[0107] In this example, the protection circuit 28 of the security processor 86 includes an exception delay circuit 88, which delays the processing of the exception event until the error detection of the current program code segment is completed. The delay circuit 88 has the following interface:

[0108] “Exception input” – an input for receiving an exception event, such as an interrupt, sent to the instruction pipeline 24 .

[0109] “Exception output” – the output that actually passes the exception event to the instruction pipeline 24 .

[0110] The control input from the EDC check logic 56 indicates that the EDC check for the current program code segment has been completed.

[0111] In an exemplary embodiment, when the instruction pipeline 24 is executing a program code segment with a deterministic program code flow, the delay circuit 88 receives an exception event (at "Exception In"). The delay circuit 88 suppresses (e.g., latches and delays) the exception event (i.e., does not trigger the "Exception Out" output) until an indication that the EDC check for the current program code segment is complete is received from the EDC check logic 56. Only then will the delay circuit 88 trigger the "Exception Out" output, thereby allowing the instruction pipeline 24 to jump to execute the exception handling program code.

[0112] Figure 4 is a block diagram schematically showing a security processor 90 according to another embodiment of the present application. The security processor 90 is similar to Figure 1 and Figure 3 The security processor 20 and the security processor 86 in the embodiment of the present invention differ in the way they handle exceptions. Figure 4 The technique may be more suitable for exceptions that need to be handled immediately (such as non-masked interrupts) and require immediate action.

[0113] exist Figure 4 In the example of FIG. 5 , the protection circuit 28 of the security processor 90 includes an EDC check stack 92 for storing the state of the EDC check logic 56. In addition, an interface is provided for communication between the EDC check logic 56 and the instruction pipeline 24, through which the instruction pipeline notifies the EDC check logic that the exception processing has been completed.

[0114] In a typical embodiment, when an exception occurs, the EDC check logic 56 saves (pushes) the current check state (i.e., "content") to the EDC check stack 92 and suspends the check. Upon receiving an indication from the instruction pipeline 24 that the exception handling is complete, the EDC check logic 56 reads the saved state from the EDC check stack 92 (and also pops, i.e., removes the saved state from the EDC check stack 92), and resumes the EDC check from the point where it was suspended using the saved state.

[0115] After returning from the exception (e.g., until the end of the current program code paragraph), checking for errors in the program code can be performed in various ways and by various entities. In one embodiment, the check can be performed in software, such as by the exception handling program code. In such an embodiment, the exception handling program code can perform the following operations (in addition to the hardware-implemented push / pop mechanism using the EDC check stack 92 to manage the EDC check state):

[0116] (i) Read the EDC check status saved from the EDC check stack 92 (but do not pop it out, that is, do not modify the EDC check stack 92).

[0117] (ii) Associating the EDC check state with the Program Counter (PC) value immediately before the exception occurred, such as the value obtained from the processor's interrupt stack.

[0118] (iii) Read the program code as data starting from the program counter PC value obtained in stage (ii), and continue the EDC check from the saved state until the end of the program code section.

[0119] One advantage of the above flow is that the EDC check does not need to wait for the exception handling to complete. In an alternative embodiment, the error check after returning from the exception is performed by hardware, for example, by a suitable state machine in the EDC check logic 56.

[0120] Note that the above technique based on pushing and popping the EDC state onto the stack also works well for nested exceptions (e.g., nested interrupts).

[0121] It should be understood that the above-mentioned embodiments are only for illustration, and the scope of the present application is not limited to the above-mentioned particularly shown and described contents. On the contrary, the scope of the present application includes the combination and sub-combination of the above-mentioned various features, as well as the changes and modifications that those skilled in the art will think of after reading the foregoing description and are not disclosed in this article. The documents incorporated into this patent application by reference shall be deemed to be an integral part of the present application, unless any term defined in these incorporated documents in a manner that conflicts with the explicit or implicit definition in this specification, only the definition in this specification shall be considered.

Claims

1. A device for protecting a processor, characterized in that: include: an input interface configured to monitor a plurality of program code instructions processed by a processor, wherein one of the plurality of program code instructions includes an error detection bit, and A protection circuit is configured to use the error detection bit to detect an error in a program code, and in view of an abnormal event occurring in the processor, when the protection circuit detects the error, the protection circuit initiates a corresponding action.

2. The device for protecting a processor according to claim 1, characterized in that: The program code includes a program code section, the program code section has a deterministic program code flow, and includes the error detection bit calculated based on a portion of the program code section, and When the abnormal event occurs during the processing of the program code section by the processor, the protection circuit takes action.

3. The device for protecting a processor according to claim 2, characterized in that: When the abnormal event occurs, the protection circuit is configured to stop checking the program code section for the error.

4. The device for protecting a processor according to claim 2, wherein: The protection circuit is configured to delay the processor from handling the exception event until checking the program code section for the error is complete.

5. The device for protecting a processor according to claim 1, wherein: When the abnormal event occurs, the protection circuit is configured to: pausing the error check and saving a state of the check; and After the processor has processed the abnormal event, the check is restored from the saved state.

6. The device for protecting a processor according to claim 1, wherein: Upon detecting the error, the protection circuit is configured to detect a fault injection attack.

7. The device for protecting a processor according to claim 1, wherein: The error detection bits are inserted at one or more reserved bit positions of the program code instructions, and the protection circuit is configured to extract the error detection bits from the reserved bit positions.

8. The device for protecting a processor according to claim 1, wherein: The error detection bit is inserted at one or more actually reserved bit positions of the program code instructions, the bit positions do not affect the execution of the program code instructions, and the protection circuit is configured to extract the error detection bit from the actually reserved bit positions.

9. The device for protecting a processor according to claim 1, wherein: The error detection bits are inserted at a plurality of bit positions of one or more jump instructions, the plurality of bit positions being designated to indicate a jump offset, but the processor is configured to ignore the plurality of bit positions.

10. The device for protecting a processor according to claim 1, characterized in that: The error detection bits are inserted into a plurality of special program code instructions that are added to the program code for error detection, and the protection circuit is configured to identify the plurality of special program code instructions and extract the error detection bits from the plurality of special program code instructions.

11. The device for protecting a processor according to claim 1, wherein: The protection circuit is configured to save a definition of the position of the error detection bit in the plurality of program code instructions and extract the error detection bit from the plurality of program code instructions according to the definition.

12. The device for protecting a processor according to claim 1, wherein: The error detection bit is one or more, and a selected set of the one or more error detection bits is calculated over at least a portion of a selected one of the plurality of program code instructions and inserted into the selected one of the plurality of program code instructions.

13. The device for protecting a processor according to claim 1, wherein: The error detection bits are one or more, a selected group of the one or more error detection bits is calculated on multiple selected bits in the program code, and at least one of the multiple selected bit points and at least one of the error detection bits in the selected group are located in different program code instructions.

14. The device for protecting a processor according to claim 1, wherein: Also included is an insertion circuit configured to insert the error detection bit into one or more of the plurality of program code instructions provided to the processor for processing.

15. A processor, characterized in that: include: an instruction pipeline configured to fetch and execute a program code including a plurality of program code instructions, wherein one or more of the plurality of program code instructions include an error detection bit; as well as A protection circuit is configured to at least monitor the error detection bits in the plurality of program code instructions, and the protection circuit uses the error detection bits to detect one or more errors in the program code under consideration of abnormal events occurring in the processor, and initiates a corresponding action when the one or more errors are detected.

16. A method for protecting a processor, characterized in that: include: monitoring a plurality of program code instructions processed by a processor, wherein one or more of the plurality of program code instructions includes an error detection bit; Using the error detection bit to detect an error in the program code in consideration of an abnormal event occurring in the processor; as well as When the error is detected, a corresponding action is initiated.

17. The method according to claim 16, characterized in that The program code includes a program code section, the program code section has a deterministic program code flow, and includes the error detection bit calculated based on a portion of the program code section; as well as Herein, taking into account the abnormal event includes taking corresponding actions for the abnormal event that occurs when the processor is processing a program code segment.

18. The method according to claim 17, characterized in that The corresponding action to the abnormal event includes terminating the checking of the error in the program code section.

19. The method according to claim 17, characterized in that The corresponding action for the exception event includes delaying processing the exception event of the processor until the error in the program code section is checked.

20. The method of claim 16, wherein: Taking into account the abnormal event includes when the abnormal event occurs: Suspend error checking as described in the program code paragraph; and After the processor has processed the exception event, the check is restored from the saved state.

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