Trigger merging and placing method, electronic equipment and storage medium
By adopting a self-balanced binary tree-based flip-flop merging and placement method in the integrated circuit design, the problem of flip-flop merge timing degradation and poor placement matching in the prior art is solved, and the circuit performance optimization and efficiency improvement are achieved.
Patent Information
- Application Number
- CN202411644749.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-02-28
AI Technical Summary
The prior art cannot effectively reflect the interconnection between triggers during the trigger merging process, resulting in rapid timing degradation and lack of specific trigger placement and pin matching schemes, resulting in a decrease in the degree of circuit performance optimization.
Using a self-balancing binary tree-based unit storage scheme, merging triggers are identified and circuits are divided into several areas to avoid long-distance merging. Through the tree data structure and stack placement policy, the merge and placement scheme of triggers is determined and pin matched to optimize timing performance.
It effectively reduces circuit power consumption, area and clock tree complexity, improves the performance and efficiency of integrated circuits, reduces timing degradation, and improves the feasibility of flip-flop merging.
Smart Images
Figure CN119538814A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a trigger merging and placing method, electronic equipment and storage medium, and belongs to the technical field of integrated circuit design. Background Art
[0002] In the physical design process of integrated circuits, the optimization of the clock network has always been a key issue. The clock distribution network usually accounts for a large part of the chip power consumption and directly affects the timing performance of the chip. Therefore, how to effectively reduce the power consumption of the clock network and improve the transmission efficiency of the clock signal has become the focus of designers.
[0003] As one of the important optimization techniques, multi-bit trigger merging and post-processing have been studied in depth. The core idea of multi-bit triggers is to reduce the number of clock lines that drive each trigger individually in the clock network by reasonably merging multiple single-bit triggers into a single multi-bit trigger. Since the clock power consumption is directly related to the length and number of clock lines, this clustering method can significantly reduce the total length of the clock line, thereby reducing the power consumption of the clock distribution network. In addition, the merging of multi-bit triggers can also effectively reduce the wiring complexity in the chip, thereby improving the physical layout and further improving the overall performance. Therefore, this technology has become an important means of clock power optimization and is widely used in the optimization process of modern integrated circuit design.
[0004] Existing trigger fusion schemes are mostly based on distance and trigger local density clustering methods. The problems are, on the one hand, distance and trigger local density clustering cannot truly and effectively reflect the interconnection relationship between triggers, which may lead to rapid timing degradation; on the other hand, existing methods do not specifically give how the merged triggers should be placed back into the original circuit, and how the pins of the original triggers and the new multi-bit triggers should be matched, which will lead to a decrease in the degree of circuit performance optimization.
[0005] The present invention aims to solve the technical problem of merging triggers while minimizing circuit timing degradation as much as possible, and at the same time consider how to correctly and effectively place the fused triggers legally back to the original circuit. Summary of the invention
[0006] Purpose: In order to overcome the deficiencies in the prior art, the present invention provides a trigger merging and placement method, an electronic device and a storage medium, the purpose of which is to ensure the trigger merging rate while minimizing timing degradation, and to propose a feasible trigger pin matching and trigger placement scheme.
[0007] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:
[0008] In a first aspect, a trigger merging and placement method comprises the following steps:
[0009] Step S1, obtaining the netlist information of the circuit layout, and constructing a graph data structure of the circuit unit information according to the netlist information.
[0010] Step S2, divide the circuit layout into several areas, obtain the position of the circuit unit according to the graph data structure of the circuit unit information, and divide the circuit unit into circuit unit sets of corresponding areas according to the position information of the circuit unit, and construct a tree data structure for trigger maximum cluster identification based on the circuit unit sets in each area.
[0011] Step S3, identifying the maximum cluster of triggers for each region in turn according to the tree data structure, and obtaining the maximum cluster set of triggers corresponding to each region.
[0012] Step S4, according to the maximum cluster set of triggers corresponding to each region, select a set of triggers to be merged and a corresponding multi-bit trigger for each maximum cluster in the maximum cluster set of triggers under certain constraints.
[0013] Step S5, placing the multi-bit triggers on the set of triggers to be merged and the corresponding multi-bit triggers selected by each largest group in each area in turn to obtain the placed multi-bit triggers.
[0014] Step S6, performing pin matching based on the placed multi-bit triggers and the corresponding trigger set to be merged, selecting the optimal matching scheme and calculating the pin timing degradation amount. If the timing degradation amount is greater than the threshold, re-performing steps S4 and S5 on the largest group.
[0015] As a preferred solution, the step S6 further includes: if the timing degradation amount is less than a threshold, outputting the placed multi-bit trigger.
[0016] As a preferred solution, the graph data structure adopts an undirected graph express, .
[0017] in, To represent the node set of all units, , Represents graph structure data nodes, For the 1st, 2nd, ..., nodes, nodes Indicates pins; is the edge set that represents the connection relationship between units. Represents graph structure data Strip edge, is a set of node attributes. , No. Row vector For the Node Dimension attribute information.
[0018] As a preferred solution, the tree data structure for trigger maximum clique identification is defined as: .
[0019] in, A self-balancing binary search tree is used, in which the nodes of the self-balancing binary search tree , ,in, Represents a tree node The index value of Indicates the color of the tree nodes, Represents the left child node, Represents the right child node, Represents the parent node, is the feature vector of the node.
[0020] As a preferred solution, the method for constructing the self-balancing binary search tree specifically includes:
[0021] Traversal , calculate the pin of the trigger With pin The Manhattan distance d of a connected fan-in or fan-out gate defines a diamond-shaped area centered on the pin fan-out gate with a semi-diagonal length of d.
[0022] The intersection of the diamond areas defined on all pins of each flip-flop is calculated, and the overlapping area is defined as the movable region FR of this flip-flop.
[0023] In each area divided by the circuit layout, the movable area in each area The left edge coordinate of , right edge coordinate As value, based on all movable areas of Values build a self-balancing binary search tree .in, Indicates Trigger The left edge of coordinate, Indicates Trigger The right edge of coordinate.
[0024] As a preferred solution, the maximum group represents a set of single-bit triggers that may be merged.
[0025] As a preferred solution, the method for identifying the largest group of triggers specifically includes:
[0026] according to Traverse a self-balancing binary search tree in order from small to large All nodes of , record the traversed ,when When the first sequence appears, a maximum group is identified. ,definition , Indicates the area The largest group, For the region The set of triggers that appeared in the first sequence corresponding to the largest group, The right edge appears in the area The set of triggers in the first sequence corresponding to the largest group, .
[0027] Identify all the largest clusters in the region and construct the largest cluster set , defined as .
[0028] The first sequence is of the form , For triggers ,trigger , The first trigger encountered after the left edge of Right edge and trigger The trigger immediately following the right edge Right edge.
[0029] As a preferred solution, selecting a set of triggers to be merged and corresponding multi-bit triggers for each maximum group in the maximum group set of triggers specifically includes:
[0030] Select a multi-bit trigger, for Trigger library, based on formula Calculate the The power consumption cost of a multi-bit flip-flop.
[0031] in, represent Trigger Library A multi-bit flip-flop, is the proportionality coefficient, The power consumption corresponding to the m-th multi-bit flip-flop is, Corresponding to the area of the m-th multi-bit flip-flop.
[0032] A multi-bit trigger with the lowest power consumption cost is selected as the corresponding multi-bit trigger.
[0033] definition is the set of triggers to be merged, from Select the first , the corresponding trigger As The first element in .
[0034] Traversal , judge each one in turn In the y-coordinate direction, is it All triggers included overlap, and when they do not overlap, if Corresponding trigger The right edge of If it has already appeared, mark the trigger It is an isolated trigger and does not participate in any merge. Corresponding trigger The right edge of If it does not appear, the trigger Send to the next largest group .
[0035] When overlapped, the trigger is judged With trigger Whether the clocks have the same source or not, the trigger Send to the next largest group , the same source, then the trigger join in , until Maximum size reached.
[0036] in, Represents a trigger The right edge of Represents a trigger .
[0037] As a preferred solution, step S5 specifically includes:
[0038] Step S5.1: Each trigger in Overlap is performed and the overlapping area is defined as ,Will Push into the stack structure Stack, , Stack is used to store the set of unprocessed triggers to be merged.
[0039] Step S5.2: Get the trigger set to be merged at the top of the Stack , select correspond The point in the lower left corner is used as the placement point. If no point is available, mark All triggers in are non-clusterable triggers and do not participate in the subsequent merging and placement process of any region.
[0040] Step S5.3: If there is a point to choose from, place the lower left corner of the multi-bit trigger at the placement point to determine whether there is any overlap in the multi-bit trigger. If there is no overlap, determine whether the local unit area utilization rate after placement meets the requirements. If the local unit area utilization rate requirements are met, the multi-bit trigger is successfully placed. Pop the stack and get the multi-bit trigger after placement. If it does not meet the requirements of local unit area utilization, return to step S5.2 to select other placement points; if there is overlap, if the overlapping area is a gate unit, return to S5.2 to select other placement points. If the overlap is other unprocessed triggers in the same area, , then the trigger The set of triggers to be merged Push onto the stack, , return to step S5.2.
[0041] As a preferred solution, step S6 specifically includes:
[0042] Get the pin set of the placed multi-bit flip-flop ,in, bits is the number of bits of the multi-bit trigger, represents the i-th input pin, Represents the i-th output pin.
[0043] Get the set of triggers to be merged The input pin of the jth flip-flop in , Output pin ,calculate arrive The Manhattan distance is recorded as , arrive Recorded as , explore all The optimal solution of the mapping is Minimum, then the multi-bit trigger With the trigger set to be merged Matching, multi-bit trigger With the trigger set to be merged Match.
[0044] Perform a breadth-first traversal on the undirected graph G, and recalculate the delay and timing margin of the multi-bit trigger pins step by step during the traversal process to determine the pros and cons of the delay and timing margin of the multi-bit trigger and the delay and timing margin of the corresponding single-bit trigger pin in the MF. If the delay and timing margin of the merged multi-bit trigger deteriorate, the merge fails and returns to the processing of steps S4 and S5.
[0045] In a second aspect, an electronic device includes a memory and a processor, wherein the memory stores a computer program that runs on the processor, and when the processor runs the computer program, the steps of the trigger merging and placement method described in the first aspect are executed.
[0046] In a third aspect, a computer-readable storage medium stores a computer program, which, when executed, executes the steps of the trigger merging and placement method described in the first aspect.
[0047] Beneficial effects: The present invention provides a trigger merging and placement method, electronic device and storage medium, which can reduce circuit power consumption, area, and clock tree complexity, thereby improving the performance and efficiency of integrated circuits.
[0048] Compared with the prior art, it has the following beneficial effects:
[0049] (1) The present invention adopts a unit storage scheme based on a self-balancing binary tree to effectively identify the mergable triggers, divides the circuit into several areas to avoid the long-distance merging of the triggers, and determines a basic placement area based on the connection relationship and relative position of the triggers, which can ensure that the timing will not be excessively degraded.
[0050] (2) In the placement stage after the flip-flops are merged, the present invention adopts a placement strategy similar to a stack, which can improve the merging rate of the flip-flops to a certain extent, thereby improving the circuit optimization effect.
[0051] (3) The present invention proposes a feasible solution for pin matching between the original trigger and the new multi-bit trigger after the trigger is merged. This solution can reduce the difficulty of local winding to a certain extent, and further improve the feasibility of trigger merging in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] Figure 1 This is a flow chart of trigger merging and post-processing proposed by the present invention. DETAILED DESCRIPTION
[0053] The following is a clear and complete description of the technical solutions in the examples of the present invention in conjunction with the accompanying drawings in the examples of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present invention.
[0054] The present invention will be further described below in conjunction with specific embodiments.
[0055] Embodiment 1:
[0056] This embodiment introduces a trigger merging and placement method, including the following steps:
[0057] Step S1, extracting the netlist information of the circuit layout through a tool, and constructing a graph data structure of the circuit unit information according to the netlist information.
[0058] Step S2, divide the circuit layout into several areas, obtain the position of the circuit unit according to the graph data structure of the circuit unit information, and divide the circuit unit into circuit unit sets of corresponding areas according to the position information of the circuit unit, and construct a tree data structure for trigger maximum cluster identification based on the circuit unit sets in each area.
[0059] Step S3, identifying the maximum cluster of triggers for each region in turn according to the tree data structure, and obtaining the maximum cluster set of triggers corresponding to each region.
[0060] Step S4, according to the maximum cluster set of triggers corresponding to each region, select a set of triggers to be merged and a corresponding multi-bit trigger for each maximum cluster in the maximum cluster set of triggers under certain constraints.
[0061] Step S5, placing the multi-bit triggers on the set of triggers to be merged and the corresponding multi-bit triggers selected by each largest group in each area in turn to obtain the placed multi-bit triggers.
[0062] Step S6, performing pin matching based on the placed multi-bit triggers and the corresponding trigger set to be merged, selecting the optimal matching scheme and calculating the pin timing degradation amount. If the timing degradation amount is greater than the threshold, re-performing steps S4 and S5 on the largest group.
[0063] Further optimizing the scheme, the netlist information of the circuit layout includes but is not limited to SPEF file (Standard Parasitic Exchange Format, standard parasitic parameter exchange format) and lib file (static database file).
[0064] Further optimization scheme, the graph data structure of the circuit unit information adopts an undirected graph with nodes and attributes express, .
[0065] in, To represent the node set of all units, , Represents graph structure data nodes, For the 1st, 2nd, ..., nodes, nodes Indicates pins; is the edge set that represents the connection relationship between units. Represents graph structure data Strip edge, is a set of node attributes. , No. Row vector For the Node Dimensional attribute information, where the attribute information includes but is not limited to unit location, fan-in and fan-out numbers and connected pins, pin delay, pin timing margin, and placement area.
[0066] To further optimize the solution, step S2 divides the circuit layout into regions according to the circuit size and the average size of the gate units.
[0067] To further optimize the scheme, the tree data structure for trigger maximum group identification is defined as , A self-balancing binary search tree is used, in which the nodes of the self-balancing binary search tree , ,in, Represents a tree node The index value satisfies the properties of the binary search tree, that is, , Indicates the color of the tree nodes, , Represents the left child node, Represents the right child node, Represents the parent node, if is the root node, is NULL, is the feature vector of the node.
[0068] Wherein, the self-balancing binary search tree The construction method of the tree is that the nodes of the tree come from the undirected graph G constructed in step S1. The left and right edges of the placement area are used to construct a self-balancing binary search tree , the specific steps are:
[0069] Step S2.1: Traversal , calculate the pin of the trigger With pin The Manhattan distance d of a connected fan-in or fan-out gate defines a diamond-shaped area centered on the pin fan-out gate with a semi-diagonal length of d.
[0070] Step S2.2: Find the intersection of the diamond regions defined on all pins of each trigger, and define the overlapping region as the movable region FR of this trigger.
[0071] Step S2.3: In each area divided by the circuit layout, the movable area in each area The left edge coordinate of , right edge coordinate As value, based on all movable areas of Values build a self-balancing binary search tree .in, Indicates Trigger The left edge of coordinate, Indicates Trigger The right edge of coordinate.
[0072] To further optimize the solution, the maximum group represents a set of single-bit triggers that may be merged.
[0073] To further optimize the scheme, the specific method of identifying the largest group of triggers in step S3 is as follows: Traverse a self-balancing binary search tree in order from small to large All nodes of , record the traversed ,when When the first sequence appears, a maximum group is identified. ,definition , Indicates the area The largest group, For the region The set of triggers that appeared in the first sequence corresponding to the largest group, The right edge appears in the area The set of triggers in the first sequence corresponding to the largest group, ; Identify all the largest clusters in the region and construct the largest cluster set , defined as .
[0074] The first sequence is of the form , For triggers ,trigger , The first trigger encountered after the left edge of Right edge and trigger The trigger immediately following the right edge Right edge.
[0075] Further optimizing the scheme, the step S4 selects a set of triggers to be merged and a corresponding multi-bit trigger for each maximum group in the trigger maximum group set, specifically comprising: first selecting a multi-bit trigger, for Trigger library, based on formula ,in Represents Trigger Library A multi-bit flip-flop, is the proportionality coefficient, The power consumption corresponding to the m-th multi-bit flip-flop is, For the area of the m-th multi-bit trigger, we should choose The smallest multi-bit flip-flop. Definition is the set of triggers to be merged. ,and The elements in should first be Select from The size of should be equal to the number of bits of the selected multi-bit flip-flop. The selection method is as follows: First, Select the first , the corresponding trigger As The first element in, then traverse , judge each one in turn In the y coordinate direction, is it consistent with this All triggers included overlap, and when they do not overlap, if this Corresponding trigger The right edge of If it has appeared, the trigger is marked as an isolated trigger and does not participate in any merge. If it has not appeared, it is sent to the next largest group. ; When overlapping, judge and Whether the clocks have the same source, if they are not, they will be sent to the next largest group. , the same source will join in , until Maximum size reached.
[0076] To further optimize the solution, step S5 should include the following steps:
[0077] Step S5.1: Each trigger in Overlap, and define the overlapping area as ,Will Push stack structure , Stack is used to store the set of unprocessed triggers to be merged.
[0078] Step S5.2: Get the trigger set to be merged at the top of the Stack , select correspond The point in the lower left corner is used as the placement point. If no point is available, mark All triggers in are non-clusterable triggers and do not participate in the subsequent processes of any subsequent regions.
[0079] Step S5.3: Place the lower left corner of the multi-bit trigger at the placement point to determine whether there is any overlap in the multi-bit trigger. If there is no overlap, determine whether the local unit area utilization rate after placement meets the requirements. If the local unit area utilization rate requirements are met, the multi-bit trigger is successfully placed. Pop the stack. If the local unit area utilization requirement is not met, return to step S5.2 to select other placement points. If there is an overlap, if the overlapping area is a gate unit, return to S5.2 to select other placement points. If the overlap is other unprocessed triggers in the same area, , then the trigger The set of triggers to be merged Push onto the stack, , return to step S5.2.
[0080] To further optimize the solution, step S6 first obtains the pin set of the multi-bit trigger after placement , bits is the number of bits of the multi-bit trigger, represents the i-th input pin, Indicates the i-th output pin. Then get the set of triggers to be merged The input pin of the jth flip-flop in , Output pin ,calculate arrive The Manhattan distance is recorded as , arrive Recorded as , explore all The optimal solution of the mapping is minimum, then the multi-bit trigger With the trigger set to be merged Matching, multi-bit trigger With the trigger set to be merged Finally, the graph G is traversed in breadth first, and the delay and timing margin of the multi-bit trigger pins are recalculated level by level during the traversal process to determine the pros and cons of the delay and timing margin of the multi-bit trigger pins and the corresponding single-bit trigger pins in the MF. If the delay and timing margin of the merged multi-bit trigger become very poor, the merger is considered to have failed, and the process returns to step S4 to reselect a suitable multi-bit trigger for this maximum group, and re-perform the placement and legalization operations in S5 for this maximum group.
[0081] Embodiment 2:
[0082] In one embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, wherein the memory stores a computer program that runs on the processor, and the processor executes the steps of the trigger merging and placement method as described above when running the computer program.
[0083] Embodiment 3:
[0084] In one embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed, the steps of the trigger merging and placement method described above are executed.
[0085] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0086] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0087] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0088] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0089] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A trigger merging and placement method, characterized in that: The steps include: Step S1, obtaining the netlist information of the circuit layout, and constructing a graph data structure of the circuit unit information according to the netlist information; Step S2, dividing the circuit layout into several areas, obtaining the position of the circuit unit according to the graph data structure of the circuit unit information, and dividing the circuit unit into circuit unit sets of corresponding areas according to the position information of the circuit unit, and constructing a tree data structure for trigger maximum clique identification according to the circuit unit set of each area; Step S3, identifying the maximum cluster of triggers for each region in turn according to the tree data structure, and obtaining the maximum cluster set of triggers corresponding to each region; Step S4, according to the maximum cluster set of triggers corresponding to each region, selecting a set of triggers to be merged and a corresponding multi-bit trigger for each maximum cluster in the maximum cluster set of triggers under certain constraints; Step S5, placing the multi-bit triggers on the trigger sets to be merged and the corresponding multi-bit triggers selected by each largest group in each region in turn, to obtain the multi-bit triggers after placement; Step S6, performing pin matching based on the placed multi-bit triggers and the corresponding trigger set to be merged, selecting the optimal matching scheme and calculating the pin timing degradation amount. If the timing degradation amount is greater than the threshold, re-performing steps S4 and S5 on the largest group.
2. A trigger merging and placement method according to claim 1, characterized in that: The step S6 also includes: if the timing degradation amount is less than a threshold, outputting the placed multi-bit trigger.
3. A trigger merging and placement method according to claim 1 or 2, characterized in that: The graph data structure adopts an undirected graph express, ; in, To represent the node set of all units, , Represents graph structure data nodes, For the 1st, 2nd, ..., nodes, nodes Indicates pins; is the edge set that represents the connection relationship between units. Represents graph structure data Strip edge, is a set of node attributes. , No. Row vector For the Node Dimension attribute information.
4. A trigger merging and placement method according to claim 1 or 2, characterized in that: The tree data structure for trigger maximum clique identification is defined as ; in, A self-balancing binary search tree is used, in which the nodes of the self-balancing binary search tree , ,in, Represents a tree node The index value of Indicates the color of the tree nodes, Represents the left child node, Represents the right child node, Represents the parent node, is the feature vector of the node.
5. A trigger merging and placement method according to claim 4, characterized in that: The method for constructing the self-balancing binary search tree specifically includes: Traversal , calculate the pin of the trigger With pin The Manhattan distance d of the connected fan-in or fan-out gate defines a diamond-shaped area centered on the pin fan-out gate with a semi-diagonal length of d; Find the intersection of the diamond areas defined on all pins of each trigger, and the overlapping area is defined as the movable area FR of this trigger; In each area divided by the circuit layout, the movable area in each area The left edge coordinate of , right edge coordinate As value, based on all movable areas of Values build a self-balancing binary search tree ; in, Indicates Trigger The left edge of coordinate, Indicates Trigger The right edge of coordinate.
6. A trigger merging and placement method according to claim 1 or 2, characterized in that: The method for identifying the maximum group of triggers specifically includes: according to Traverse a self-balancing binary search tree in order from small to large All nodes of , record the traversed ,when When the first sequence appears, a maximum group is identified. ,definition , Indicates the area The largest group, For the region The set of triggers that appeared in the first sequence corresponding to the largest group, The right edge appears in the first The set of triggers in the first sequence corresponding to the largest group, ; Identify all the largest clusters in the region and construct the largest cluster set , defined as ; The first sequence is of the form , For triggers ,trigger , The first trigger encountered after the left edge of Right edge and trigger The trigger immediately following the right edge Right edge.
7. A trigger merging and placement method according to claim 1 or 2, characterized in that: The step of selecting a set of triggers to be merged and corresponding multi-bit triggers for each maximum group in the maximum group set of triggers specifically includes: Select a multi-bit trigger, for Trigger library, based on formula Calculate the The power consumption cost of a multi-bit flip-flop; in, represent Trigger Library A multi-bit flip-flop, is the proportionality coefficient, The power consumption corresponding to the m-th multi-bit flip-flop is, The area corresponding to the m-th multi-bit flip-flop; Select a multi-bit trigger with the lowest power consumption cost as the corresponding multi-bit trigger; definition is the set of triggers to be merged, from Select the first , the corresponding trigger As The first element in Traversal , judge each one in turn In the y-coordinate direction, is it All triggers included overlap, and when they do not overlap, if Corresponding trigger The right edge of If it has already appeared, mark the trigger It is an isolated trigger and does not participate in any merge. Corresponding trigger The right edge of If it does not appear, the trigger Send to the next largest group ; When overlapped, the trigger is judged With trigger Whether the clocks have the same source or not, the trigger Send to the next largest group , the same source, then the trigger join in , until The size limit has been reached; in, Represents a trigger The right edge of Represents a trigger .
8. A trigger merging and placement method according to claim 1 or 2, characterized in that: The step S5 specifically includes: Step S5.1: Each trigger in Overlap is performed and the overlapping area is defined as ,Will Push into the stack structure Stack, , Stack is used to store the set of unprocessed triggers to be merged; Step S5.2: Get the trigger set to be merged at the top of the Stack , select correspond The point in the lower left corner is used as the placement point. If no point is available, mark All triggers in are non-clusterable triggers and do not participate in the subsequent merging and placement of any regions; Step S5.3: If there is a point to choose from, place the lower left corner of the multi-bit trigger at the placement point to determine whether there is any unit overlap in the multi-bit trigger; if there is no overlap, determine whether the local unit area utilization rate after placement meets the requirements. If the local unit area utilization rate requirements are met, the multi-bit trigger is successfully placed. Pop the stack and get the multi-bit trigger after placement. If it does not meet the requirements of local unit area utilization, return to step S5.2 to select other placement points; if there is overlap, if the overlapping area is a gate unit, return to S5.2 to select other placement points. If the overlap is other unprocessed triggers in the same area, , then the trigger The set of triggers to be merged Push onto the stack, , return to step S5.
2.
9. A trigger merging and placement method according to claim 1 or 2, characterized in that: The step S6 specifically includes: Get the pin set of the placed multi-bit flip-flop ,in, bits is the number of bits of the multi-bit trigger, represents the i-th input pin, represents the i-th output pin; Get the set of triggers to be merged The input pin of the jth flip-flop in , Output pin ,calculate arrive The Manhattan distance is recorded as , arrive Recorded as , explore all The optimal solution of the mapping is Minimum, then the multi-bit trigger With the trigger set to be merged Matching, multi-bit trigger With the trigger set to be merged Match; Perform a breadth-first traversal on the undirected graph G, and recalculate the delay and timing margin of the multi-bit trigger pins step by step during the traversal process to determine the pros and cons of the delay and timing margin of the multi-bit trigger and the delay and timing margin of the corresponding single-bit trigger pin in the MF. If the delay and timing margin of the merged multi-bit trigger deteriorate, the merge fails and returns to the processing of steps S4 and S5.
10. An electronic device, characterized in that: It comprises a memory and a processor, wherein the memory stores a computer program that runs on the processor, and the processor executes the steps of the trigger merging and placing method as claimed in claims 1 to 9 when running the computer program.
11. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is run, the steps of the trigger merging and placing method as claimed in claims 1 to 9 are executed.