Developing an adaptive clock system with reconfigurable processor timing margins and its implementation method

Abstract

This invention provides a method and system for developing an adaptive clock implementation for timing margins in a reconfigurable processor, comprising: Step S1: A simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain delay information; the delay information is sent to the compiler, which generates and optimizes the data flow graph for the application, and simultaneously encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information; Step S2: The workload factor and the PVT factor generated by the PVT detection module are jointly input into the phase selection module, and the phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically, to the development of an adaptive clock system with reconfigurable processor timing margins and its implementation method. Background Technology

[0002] In digital VLSI circuits, static timing analysis (STA) is used to verify timing performance and ensure that timing errors do not occur on the critical path under various process, voltage, and temperature (PVT) conditions. However, in most cases, the critical path is not triggered, and worst-case PVT conditions rarely occur. Therefore, adopting this pessimistic STA approach results in considerable time relaxation. This indicates that the chip can actually operate at higher frequencies or lower voltages. Therefore, utilizing timing relaxation can significantly improve performance and reduce power consumption. Timing relaxation can be divided into two parts based on its source: PVT relaxation and workload relaxation. PVT relaxation arises because the chip rarely operates under worst-case PVT conditions, meaning that the safety margin added to ensure timing correctness becomes useless timing slack. Workload relaxation occurs because the critical path is not triggered every clock cycle, and non-critical paths do not consume all reserved logic delays.

[0003] Existing technologies employ a low-power microprocessor instruction-driven adaptive clock scheme (published on page 2327 of the August 2019 issue of the journal "IEEE JOURNAL OF SOLID-STATE CIRCUITS" as "An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assi stance for a Low Power Microprocessor"). This scheme can generate an adaptive clock based on instructions, develop timing margins caused by workload, and perform PVT calibration before each task. However, it cannot avoid timing errors caused by changes in the runtime environment, does not solve the time margin caused by PVT changes, and requires a long calibration cycle and complex process. This structure is only suitable for serial processors such as CPUs.

[0004] Patent document CN110336545B (application number: 201910514122.5) discloses a bidirectional adaptive clock circuit supporting a wide frequency range, belonging to the technical field of basic electronic circuits. This circuit consists of a phase clock generation module, a phase clock selection module, an adaptive clock stretching or compression adjustment module, and a control module. The adaptive clock stretching or compression adjustment module can monitor the delay information of critical paths in the chip in real time and feed this information back to the control module. After receiving the clock stretching or compression enable signal and the stretching or compression scale signal, the control module selects the target phase clock from the clock generated by the phase clock generation module and completes the rapid adjustment of the adaptive clock within the current cycle. This circuit can effectively reduce PVT timing margin, thereby improving the circuit's energy efficiency; however, it does not utilize the timing margin caused by workload, leaving room for further development of timing margin. Furthermore, this circuit cannot be used in array-type structures.

[0005] Patent document US20210247797A1 (application number: US17170187) discloses "COMPUTE-ADAPTIVECLOCK MANAGEMENT FOR MACHINE LEARNING ACCELERATORS", providing a globally asynchronous, locally synchronous adaptive clock chain for array-structured accelerators. However, this method is designed for fixed and regular interconnects, such as those in DNN accelerator arrays, and is not suitable for the uncertain, irregular, and complex interconnect patterns in reconfigurable processors. This scheme only addresses timing margins caused by workload, without considering timing margins caused by PVT (Progressive Virtual Transmission). Furthermore, asynchronous operation introduces complex communication problems, resulting in a complex structure and high overhead. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide an adaptive clock system and implementation method for developing reconfigurable processor timing margins.

[0007] An adaptive clock implementation method for developing timing margins in a reconfigurable processor, provided by the present invention, includes:

[0008] Step S1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain latency information; the latency information is sent to the compiler, which generates and maps the data flow graph for the application, and encodes the corresponding latency information into the configuration information. The workload factor is obtained based on the encoded configuration information.

[0009] Step S2: Input the workload factor and the PVT factor generated by the PVT detection module into the phase selection module. The phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0010] Preferably, step S1 employs: a simulation tool to perform dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case latency of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation latency and routing latency of each PE constitutes the workload latency of the current PE; by traversing all PEs in the array, the PE with the largest workload latency is identified; and the current maximum workload latency is quantified into a workload factor M.

[0011] Preferably, the compiler is optimized, including: aggregating high-latency nodes into the same time slot and minimizing interconnection distance;

[0012] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify bottleneck nodes with limited frequency, and adjust node scheduling by allocating bottleneck nodes to the same time slots as much as possible while considering resource constraints; perform routing using a fast spatial mapping algorithm and an improved Dijkstra algorithm; if the current scheduling fails to achieve the preset layout and routing results, reschedule the bottleneck nodes and repeat the above steps; if all attempts to adjust the scheduling are unsuccessful, increase the initialization interval and perform rescheduling.

[0013] Preferably, the PVT detection module includes: a tunable replication circuit (TRC) and a time-to-digital converter (TDC);

[0014] The tunable replication circuit TRC is used to track the path in which the time delay changes with the PVT.

[0015] The delay of the tunable replication circuit TRC is measured using the time-to-digital converter (TDC), and the PVT factor is obtained after quantization.

[0016] Preferably, the multiphase clock generation module includes: a phase-locked loop and a delay phase-locked loop;

[0017] The phase-locked loop generates a reference clock input to the delay phase-locked loop, and the delay phase-locked loop obtains a multi-phase clock based on the reference clock.

[0018] Preferably, the phase selection module includes: a phase calculation module and a phase switching module;

[0019] The phase calculation module calculates the clock index for the next cycle based on the PVT factor and the workload factor.

[0020]

[0021] Where k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases in the multiphase clock; and Δk represents the period factor.

[0022]

[0023] Where M represents the workload factor; N represents the PVT factor; and ε represents a positive integer introduced to ensure clock quality.

[0024] The phase switching module generates the clock signal for the next cycle based on the obtained clock index of the next cycle and the multiphase clock output generated by the multiphase clock generation module.

[0025] Preferably, the period of the next clock is calculated based on the period factor;

[0026]

[0027] Where T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multiphase clock.

[0028] An adaptive clock system for developing reconfigurable processor timing margins, according to the present invention, includes:

[0029] Module M1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain latency information; the latency information is sent to the compiler, which generates and maps the data flow graph for the application, and encodes the corresponding latency information into the configuration information, and obtains the workload factor based on the encoded configuration information;

[0030] Module M2: Inputs the workload factor and the PVT factor generated by the PVT detection module into the phase selection module. The phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0031] Preferably, module M1 employs: a simulation tool to perform dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case latency of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation latency and routing latency of each PE constitutes the workload latency of the current PE; by traversing all PEs in the array, the PE with the largest workload latency is identified; and the current maximum workload latency is quantified into a workload factor M.

[0032] The compiler is optimized, including aggregating high-latency nodes into the same time slot and minimizing interconnection distances.

[0033] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify bottleneck nodes with limited frequency, and adjust node scheduling by allocating bottleneck nodes to the same time slots as much as possible while considering resource constraints; perform routing using a fast spatial mapping algorithm and an improved Dijkstra algorithm; if the current scheduling fails to achieve the preset layout and routing results, reschedule the bottleneck nodes and repeat the above steps; if all attempts to adjust the scheduling are unsuccessful, increase the initialization interval and perform rescheduling.

[0034] Preferably, the PVT detection module includes: a tunable replication circuit (TRC) and a time-to-digital converter (TDC);

[0035] The tunable replication circuit TRC is used to track the path in which the time delay changes with the PVT.

[0036] The delay of the tunable replication circuit TRC is measured using the time-to-digital converter (TDC), and the PVT factor is obtained after quantization.

[0037] The multiphase clock generation module includes: a phase-locked loop and a delay phase-locked loop;

[0038] The phase-locked loop generates a reference clock input to the delay phase-locked loop, and the delay phase-locked loop obtains a multi-phase clock based on the reference clock.

[0039] The phase selection module includes: a phase calculation module and a phase switching module;

[0040] The phase calculation module calculates the clock index for the next cycle based on the PVT factor and the workload factor.

[0041]

[0042] Where k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases in the multiphase clock; and Δk represents the period factor.

[0043]

[0044] Where M represents the workload factor; N represents the PVT factor; and ε represents a positive integer introduced to ensure clock quality.

[0045] The phase switching module generates the clock signal for the next cycle based on the obtained clock index of the next cycle and the multiphase clock output generated by the multiphase clock generation module.

[0046] Preferably, the period of the next clock is calculated based on the period factor;

[0047]

[0048] Where T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multiphase clock.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] 1. This invention achieves the technical effect of simultaneously developing timing margins in both PVT and workload by using an adaptive clocking scheme composed of a PVT detection module, workload information encoding, and multi-phase clock selection technology.

[0051] 2. This invention solves the problem that the cycle of a reconfigurable processor is determined by the worst PE in the entire array, which leads to the unavailability of the spatial timing margin of other PEs, by using a compiler scheduling algorithm to rearrange the issue times of each operation. This achieves the technical effect of further utilizing the timing margin in the reconfigurable processor, improving performance and resource utilization, and increasing the actual operating frequency. Attached Figure Description

[0052] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0053] Figure 1 This is a schematic diagram of an adaptive clock system.

[0054] Figure 2 This is a schematic diagram of the PVT detection module.

[0055] Figure 3 This is a schematic diagram of the phase selection module.

[0056] Figure 4 This is a schematic diagram of the reconfigurable processor.

[0057] Figure 5 This is a schematic diagram illustrating the principle of an adaptive clock.

[0058] Figure 6 This is a schematic diagram illustrating the principle of clock stretching and compression through phase selection.

[0059] Figure 7 This is a schematic diagram illustrating the principle of PVT factor generation.

[0060] Figure 8 This is a diagram illustrating an example of performance improvement achieved by modifying the schedule.

[0061] Figure 9 The diagram shows the proposed software scheduling optimization algorithm. Detailed Implementation

[0062] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0063] Example 1

[0064] An adaptive clock implementation method for developing timing margins in a reconfigurable processor, provided by the present invention, includes:

[0065] Step S1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain latency information; the latency information is sent to the compiler, which generates and maps the data flow graph for the application, and encodes the corresponding latency information into the configuration information. The workload factor is obtained based on the encoded configuration information.

[0066] Step S2: Input the workload factor and the PVT factor generated by the PVT detection module into the phase selection module. The phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0067] Specifically, step S1 employs the following steps: using simulation tools to perform dynamic timing analysis on the application executed by the reconfigurable processor, and obtaining the worst-case latency of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation latency and routing latency of each PE constitutes the workload latency of the current PE; by traversing all PEs in the array, the PE with the largest workload latency is identified; and the current maximum workload latency is quantified into a workload factor M.

[0068] Specifically, the compiler is optimized, including aggregating high-latency nodes into the same time slot and minimizing interconnection distances.

[0069] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify bottleneck nodes with limited frequency, and adjust node scheduling by allocating bottleneck nodes to the same time slots as much as possible while considering resource constraints; perform routing using a fast spatial mapping algorithm and an improved Dijkstra algorithm; if the current scheduling fails to achieve the preset layout and routing results, reschedule the bottleneck nodes and repeat the above steps; if all attempts to adjust the scheduling are unsuccessful, increase the initialization interval and perform rescheduling.

[0070] Specifically, the PVT detection module includes: a tunable replication circuit (TRC) and a time-to-digital converter (TDC);

[0071] The tunable replication circuit TRC is used to track the path in which the time delay changes with the PVT.

[0072] The delay of the tunable replication circuit TRC is measured using the time-to-digital converter (TDC), and the PVT factor is obtained after quantization.

[0073] Specifically, the multiphase clock generation module includes: a phase-locked loop and a delay phase-locked loop;

[0074] The phase-locked loop generates a reference clock input to the delay phase-locked loop, and the delay phase-locked loop obtains a multi-phase clock based on the reference clock.

[0075] Specifically, the phase selection module includes: a phase calculation module and a phase switching module;

[0076] The phase calculation module calculates the clock index for the next cycle based on the PVT factor and the workload factor.

[0077]

[0078] Where k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases in the multiphase clock; and Δk represents the period factor.

[0079]

[0080] Where M represents the workload factor; N represents the PVT factor; and ε represents a positive integer introduced to ensure clock quality.

[0081] The phase switching module generates the clock signal for the next cycle based on the obtained clock index of the next cycle and the multiphase clock output generated by the multiphase clock generation module.

[0082] Specifically, the period of the next clock is calculated based on the period factor;

[0083]

[0084] Where T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multiphase clock.

[0085] An adaptive clock system for developing reconfigurable processor timing margins, according to the present invention, includes:

[0086] Module M1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain latency information; the latency information is sent to the compiler, which generates and maps the data flow graph for the application, and encodes the corresponding latency information into the configuration information, and obtains the workload factor based on the encoded configuration information;

[0087] Module M2: Inputs the workload factor and the PVT factor generated by the PVT detection module into the phase selection module. The phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0088] Specifically, module M1 employs the following methods: using simulation tools to perform dynamic timing analysis on the application executed by the reconfigurable processor, and obtaining the worst-case latency of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation latency and routing latency of each PE constitutes the workload latency of the current PE; by traversing all PEs in the array, the PE with the largest workload latency is identified; and the current maximum workload latency is quantified into a workload factor M.

[0089] The compiler is optimized, including aggregating high-latency nodes into the same time slot and minimizing interconnection distances.

[0090] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify bottleneck nodes with limited frequency, and adjust node scheduling by allocating bottleneck nodes to the same time slots as much as possible while considering resource constraints; perform routing using a fast spatial mapping algorithm and an improved Dijkstra algorithm; if the current scheduling fails to achieve the preset layout and routing results, reschedule the bottleneck nodes and repeat the above steps; if all attempts to adjust the scheduling are unsuccessful, increase the initialization interval and perform rescheduling.

[0091] Specifically, the PVT detection module includes: a tunable replication circuit (TRC) and a time-to-digital converter (TDC);

[0092] The tunable replication circuit TRC is used to track the path in which the time delay changes with the PVT.

[0093] The delay of the tunable replication circuit TRC is measured using the time-to-digital converter (TDC), and the PVT factor is obtained after quantization.

[0094] The multiphase clock generation module includes: a phase-locked loop and a delay phase-locked loop;

[0095] The phase-locked loop generates a reference clock input to the delay phase-locked loop, and the delay phase-locked loop obtains a multi-phase clock based on the reference clock.

[0096] The phase selection module includes: a phase calculation module and a phase switching module;

[0097] The phase calculation module calculates the clock index for the next cycle based on the PVT factor and the workload factor.

[0098]

[0099] Where k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases in the multiphase clock; and Δk represents the period factor.

[0100]

[0101] Where M represents the workload factor; N represents the PVT factor; and ε represents a positive integer introduced to ensure clock quality.

[0102] The phase switching module generates the clock signal for the next cycle based on the obtained clock index of the next cycle and the multiphase clock output generated by the multiphase clock generation module.

[0103] Specifically, the period of the next clock is calculated based on the period factor;

[0104]

[0105] Where T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multiphase clock.

[0106] Example 2

[0107] Example 2 is a preferred example of Example 1.

[0108] This invention is aimed at reconfigurable processors and proposes for the first time an adaptive clock implementation method and system for developing timing margins in reconfigurable processors. By comprehensively utilizing the adaptive clock scheme of timing margins caused by workload and environmental changes, performance and energy efficiency can be significantly improved.

[0109] According to the present invention, an adaptive clock implementation method for developing timing margins of reconfigurable processors is provided, such as... Figure 1 As shown, this illustrates a hardware and software co-operation scheme for developing reconfigurable processor timing margins.

[0110] On the software side, simulation tools perform dynamic timing analysis to obtain delay information, which is then sent to the compiler. The compiler generates and optimizes the data flow graph for the application, while encoding the corresponding delay information into the configuration information. The encoded configuration information is stored in the configuration memory of the reconfigurable processor 4.

[0111] On the hardware side, the adaptive module includes a multi-phase clock generation module 1, a PVT detection module 2, and a phase selection module 3, which provide timing margin development for the reconfigurable processor 4. The PVT detection module 2 detects environmental changes and outputs a PVT factor, which, along with the workload factor stored in the reconfigurable processor 4, is input to the phase selection module 3. Based on this information, the phase selection module 3 selects one of the 32 phases generated by the multi-phase clock generation module 1 as the adaptive clock and provides it to the reconfigurable processor 4.

[0112] The multiphase clock generation module 1 uses a delay phase-locked loop (DLL) to generate a multiphase clock. The DLL generates a reference clock and serves as the input to the DLL.

[0113] The structure of the PVT detection module 2 is as follows: Figure 2 As shown, it consists of a tunable copy circuit (TRC) and a time-to-digital converter (TDC). The Tunable Copy Circuit (TRC) comprises a variable-length hybrid delay chain consisting of inverters, NAND gates, NOR gates, and interconnecting delay elements, as well as an inverter chain for fine-tuning. The Time-to-Digital Converter (TDC) consists of a set of flip-flops whose data inputs are connected to the output of the TRC, and whose clock inputs are Φ5, Φ6, and Φ7 from a multi-phase clock. 10 Φ 16 Φ 21 and Φ 26 The sampling result of the trigger is encoded by the encoder and used as the PVT factor.

[0114] The structure of the phase selection module 3 is as follows: Figure 3 As shown, the system is divided into two modules: phase calculation and phase switching. The phase calculation module includes a 3-bit multiplier, a 5-bit unsigned adder, and corresponding control logic. The multiplier result is selected and then fed into an accumulator, with the accumulated result output to the phase switching module. The phase switching module includes a 5-to-32 decoder, 32 integrated gated clock (ICG) units, and a 32-input OR gate. The decoder output is passed through a register and used as the enable input of the ICG module. The ICG clock input is a 32-phase clock; the ICG result is passed to the 32-input OR gate, and the output is the final adaptive clock.

[0115] The structure of the reconfigurable processor 4 is as follows: Figure 4 As shown, it consists of an interconnected array of processing units (PEs) and a data memory. Each PE includes a configuration memory, an arithmetic logic unit, a crossbar switch, and corresponding control logic.

[0116] like Figure 1The diagram illustrates a hardware-software co-engineering approach to developing timing margins for reconfigurable processors. The minimum clock cycle is determined by both workload-related configuration and PVT conditions. The former is generated and optimized through software, while the latter is hardware-aware. On the software side, simulation tools perform dynamic timing analysis to obtain the path delay of each operation within a processing unit (PE) and the routing delay between different PEs. This delay information is then passed to the compiler. During compilation, the compiler maps the application to the target architecture and encodes the corresponding delay values ​​into the configuration information. The encoded configuration is then stored in the configuration memory and used at runtime. On the hardware side, the adaptive module includes a multi-phase clock generation module 1, a PVT detection module 2, and a phase selection module 3, which develop timing margins for the reconfigurable processor 4. The PVT detection module captures PVT changes by sampling the delay changes of the reference circuit. The monitoring results, along with the encoded configuration, are transmitted to the phase selection module. The phase selection module uses this information to select the forward or backward phase of the multi-phase clock as the rising edge of the next clock, thereby achieving rapid clock cycle adjustment. The output clock can not only serve as the main clock of the reconfigurable processor to enable timing relaxation, but also as the input clock of the adaptive clock module to provide feedback, forming a closed-loop control system and enhancing the robustness of the system.

[0117] Specifically, since clock adjustment is achieved by adjusting the phase of the next rising edge, the clock period is determined by the difference between two consecutively selected phases. Let the current phase be denoted as φ, the next phase as φ′, and the multi-phase clock period as T. ref Considering that the phase changes periodically with a period of 2π, the period of the adaptive clock can be expressed as formula (1).

[0118]

[0119] like Figure 5 As shown, the adaptive clocking scheme uses the current phase and its reverse as boundaries. When the next phase falls within the interval (φ+π, φ+2π), the clock cycle is compressed. Conversely, if the next phase falls within the interval (φ, φ+π), the clock cycle is stretched, indicating a delay of more than one cycle compared to the current phase. The adjustable range is 50% to 150% of the reference clock cycle.

[0120] A multiphase clock generator is used to generate K equidistant clock phases (Φ0, Φ1, ..., Φ). K-1 ), where the time interval between adjacent clocks is δt=T ref / K, the phase difference is δΦ=2π / K. For example... Figure 6As shown, when switching from Φ1 to Φ4 at time t1, the clock period is extended by 3δt; when switching from Φ4 to Φ3 at time t2, the clock period is compressed by δt. For the quantized phase, equation (1) can be transformed into equation (2).

[0121]

[0122] Where T represents the period of the adaptive clock.

[0123] The clock period is proportional to the increment of the phase index (Δk, also known as the period factor). Since the clock period is determined by the workload and PVT orthogonality, the period factor is proportional to the product of the workload factor (M) and the PVT factor (N), and is calculated by equation (3).

[0124]

[0125] M and N are quantized values ​​reflecting the effects of workload and PVT. The upper bound of the period factor is 3K / 2, and the lower bound is slightly greater than K / 2. This is to avoid glitches and timing errors caused by an excessively small clock cycle under optimal workload and PVT conditions. In practice, due to the periodicity of the phase, the next selected phase index k′ is calculated as shown in Equation (4).

[0126]

[0127] This behavior is similar to overflow in an unsigned adder, indicating that if the value of K is a power of 2, an unsigned adder can be used. Therefore, quantization needs to satisfy the following constraints:

[0128]

[0129] For example, K = 32, M max =8, N max =6 is a set of feasible integer solutions to the above constraints. This set of solutions corresponds to a 32-phase clock, with the workload factor quantized into 8 discrete values ​​and the PVT factor quantized into 6 discrete values. Both the workload and the PVT factor can be represented by a 3-bit binary number. During runtime, after obtaining the values ​​of M and N, the value of k′ is calculated using equations (3) and (4), and then the phase corresponding to this value is selected as the rising edge of the next clock, allowing for adaptive adjustment of the clock period.

[0130] Specifically, the multiphase clock is generated using a delay phase-locked loop (DLL). Once stabilized, the DLL's frequency is locked to the reference clock frequency, generating a 32-phase clock with equal phase spacing. Each delay stage is carefully designed to minimize phase mismatch between adjacent phases. Furthermore, to minimize phase deviation caused by routing, the DLL is placed close to the phase selection module. The overall phase mismatch is limited to a very small range and is considered within the phase selection module to prevent any potential timing errors.

[0131] Specifically, the PVT detection module 2 tracks and measures the delay change caused by PVT variations. This system consists of a tunable replica circuit (TRC) as the test path and a time-to-digital converter (TDC) as the monitor. The TDC output provides the PVT factor, reflecting the impact of PVT on delay. The TRC is used to track the path of delay variation with PVT. The TRC consists of a variable-length hybrid delay chain composed of inverters, NAND gates, NOR gates, and interconnecting delay elements, as well as an inverter chain for fine-tuning. Because the TRC uses a multi-logic-gate construction and its length can be adjusted after silicon, it can effectively match delay curves under different PVT conditions. The TDC is used to measure the delay of the TRC and quantize it to obtain the PVT factor. The TDC consists of a series of flip-flops whose D inputs are connected to the output of the TRC, and whose clk inputs are driven by a multi-phase clock. Since the PVT factor is a 3-bit binary value from 0 to 5, five clock phases Φ5, Φ6, Φ7, and Φ8 are selected from 32 available phases. 10 Φ 16 Φ 21 and Φ 26 This serves as the clk input to the trigger in the TDC. Then, the encoder generates the corresponding PVT factor based on the first "1" following a series of "0s". For example... Figure 7 As shown, the first "1" after a series of "0"s in the fourth phase indicates N=3. In the next cycle, no "1" appears after a series of "0"s, indicating N=5. The generated multi-phase clock can not only be synthesized into adaptive clocks of different periods, but also serve as a reference clock for the TDC, reducing the overall system overhead.

[0132] Specifically, the phase selection module is divided into two modules: phase calculation and phase switching, such as... Figure 3As shown. The phase calculation module calculates the next phase to be selected based on the current workload factor and PVT factor. The phase switching module selects the corresponding clock phase as the rising edge of the next clock cycle. The phase calculation module takes the current phase index, workload factor and PVT factor as input and generates the next phase index as output. The calculation method is shown in Equations (3) and (4): on the one hand, Equation (3) uses a 3-bit multiplier and control logic to calculate the phase offset; on the other hand, Equation (4) uses a 5-bit unsigned adder to calculate the next phase index based on the current phase index and the calculated phase offset. Mapping the phase calculation to an unsigned adder and multiplier is an efficient and hardware-friendly implementation. After determining the phase index of the upcoming clock cycle, the phase switching module is activated to pull the corresponding phase high. This process involves using a decoder to convert the 5-bit binary representation into a 32-bit one-hot code, which serves as the enable signal for the multiphase integrated gated clock (ICG) unit. These ICG units allow the multiphase clock to pass through and are then transmitted to a multi-input OR gate. The multi-input OR gate uses Figure 3 The structure shown, instead of using synthesized trees or gates, ensures latency balance across stages and reduces overhead.

[0133] More specifically, unlike the PVT factor, which is hardware-aware, the workload factor is derived from configuration information generated by the compiler. Therefore, the software process involves mapping the application to the architecture and optimizing it, as well as encoding the timing information obtained from the simulation into the configuration. Through dynamic timing simulation, worst-case latencies for various operations and routes are obtained. In each cycle, the sum of the operational latency of each PE and the routing latency to its consumer constitutes the workload latency of that PE. By traversing all PEs in the array, the PE with the largest workload latency is identified. This largest workload latency is then quantized into a 3-bit value, denoted as M, called the workload factor. Since all PEs share the same M, we only need to modify the relevant information for a single PE. We choose to use a constant value field to represent this information because, in most cases, not all constant fields for all PEs are valid, and the compiler is used to handle any potential error cases. Therefore, this modification has no side effects. At runtime, the load factor M is extracted and sent to the adaptive clock module to help adjust the clock cycle. This method quantizes operational and routing latency into workload factors, seamlessly integrating them into the configuration without introducing excessive overhead.

[0134] For statically scheduled reconfigurable processors, the compiler that generates the configuration is crucial for achieving high performance. Reconfigurable processor compilers typically employ modular scheduling algorithms for placement and routing and configuration generation. In modular scheduling, scheduling iterations are repeated at fixed time intervals, called the initialization interval (II). The scheduling time of a node within one iteration is represented by a timeslot, calculated as timeslot = cycle % II. Figure 8 In the example shown, the data flow graph (DFG) scheduling repeats every two cycles, indicating that II = 2. Node a is allocated in timeslot 0, and node c is allocated in timeslot 1. When implementing adaptive clocking, the compiler must consider not only minimizing II but also fully utilizing available time relaxation. Therefore, the compiler optimizes in two ways. First, it aggregates high-latency nodes into the same timeslot. For example, as... Figure 8 As shown, by simply delaying the emission time of node d, the latency of timeslot1 can be reduced, improving overall performance. Secondly, the interconnect distance should be minimized, as node latency is determined by both operations and interconnects. In summary, the compiler's goal is to allocate high-latency nodes to the same time slots as much as possible and minimize interconnect distances, especially for nodes with high operation latency.

[0135] The proposed optimization algorithm is as follows: Figure 9 Algorithm 1 is shown in the diagram. First, the initialization interval II is determined and a schedule is generated using iterative modular scheduling. Then, frequency-constrained "bottleneck" nodes are identified. Subsequently, considering resource constraints, the scheduling of these "bottleneck" nodes is adjusted by allocating them to the same time slots as much as possible. Due to the unbuffered on-chip network, this reconfigurable processor architecture provides single-cycle communication between remote PEs, effectively decoupling routing and placement. After optimizing the scheduling, we use a fast spatial mapping algorithm and an improved Dijkstra's algorithm for routing. The improved routing algorithm assigns higher priority to nodes with higher operational latency. It ensures that mapped PEs can use the unbuffered on-chip network for conflict-free routing communication and guarantees that the distance between a high-latency PE and its corresponding predecessor and successor PE is minimized. If the current scheduling fails to achieve a valid placement and routing result, the "bottleneck" node is rescheduled and the above steps are repeated. If all attempts to adjust the scheduling are unsuccessful, II is increased and rescheduling is performed. This algorithm can effectively utilize the time redundancy of the reconfigurable processor, improving processor performance and resource utilization.

[0136] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0137] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for developing an adaptive clock implementation for timing margins in a reconfigurable processor, characterized in that, include: Step S1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain latency information; The delay information is sent to the compiler, which generates and maps the data flow graph for the application and encodes the corresponding delay information into the configuration information. The workload factor is obtained based on the encoded configuration information. Step S2: Input the workload factor and the PVT factor generated by the PVT detection module into the phase selection module. The phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor. The PVT detection module includes: a tunable replication circuit (TRC) and a time-to-digital converter (TDC); The tunable replication circuit TRC is used to track the path in which the time delay changes with the PVT. The delay of the tunable replication circuit TRC is measured using the time-to-digital converter (TDC), and the PVT factor is obtained after quantization. The multiphase clock generation module includes: a phase-locked loop and a delay phase-locked loop; The phase-locked loop generates a reference clock input to the delay phase-locked loop, and the delay phase-locked loop obtains a multi-phase clock based on the reference clock. The phase selection module includes: a phase calculation module and a phase switching module; The phase calculation module calculates the clock index for the next cycle based on the PVT factor and the workload factor. （1） in, Indicates the clock index for the next cycle; Indicates the clock index of the current period; Indicates the number of phases in a multiphase clock; Indicates the periodic factor; （2） in, Indicates the workload factor; Represents the PVT factor; This represents a positive integer introduced to ensure clock quality; The phase switching module uses the following method to generate the clock signal for the next cycle based on the obtained clock index of the next cycle and the multiphase clock output generated by the multiphase clock generation module. The period of the next clock cycle is calculated based on the period factor; （3） in, Indicates the period of the adaptive clock; Indicates the periodic factor; It represents the time difference between the rising edges of adjacent phases of a multiphase clock.

2. The adaptive clock implementation method for developing timing margins of reconfigurable processors according to claim 1, characterized in that, Step S1 employs the following: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case latency of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation latency and routing latency of each PE constitutes the workload latency of the current PE; by traversing all PEs in the array, the PE with the largest workload latency is identified; and the current maximum workload latency is quantified into a workload factor M.

3. The adaptive clock implementation method for developing reconfigurable processor timing margins according to claim 1, characterized in that, The compiler is optimized, including aggregating high-latency nodes into the same time slot and minimizing interconnection distances. Determine the initialization interval and generate a schedule using iterative modular scheduling; identify bottleneck nodes with limited frequency, and adjust node scheduling by allocating bottleneck nodes to the same time slots as much as possible while considering resource constraints; perform routing using a fast spatial mapping algorithm and an improved Dijkstra algorithm; if the current scheduling fails to achieve the preset layout and routing results, reschedule the bottleneck nodes and repeat the above steps; if all attempts to adjust the scheduling are unsuccessful, increase the initialization interval and perform rescheduling.

4. An adaptive clock system for developing reconfigurable processor timing margins, characterized in that, include: Module M1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain latency information; The delay information is sent to the compiler, which generates and maps the data flow graph for the application and encodes the corresponding delay information into the configuration information. The workload factor is obtained based on the encoded configuration information. Module M2: Inputs the workload factor and the PVT factor generated by the PVT detection module into the phase selection module. The phase selection module selects one of the multiphase clocks generated by the multiphase clock generation module as an adaptive clock based on the workload factor and the PVT factor, and provides it to the reconfigurable processor. The PVT detection module includes: a tunable replication circuit (TRC) and a time-to-digital converter (TDC); The tunable replication circuit TRC is used to track the path in which the time delay changes with the PVT. The delay of the tunable replication circuit TRC is measured using the time-to-digital converter (TDC), and the PVT factor is obtained after quantization. The multiphase clock generation module includes: a phase-locked loop and a delay phase-locked loop; The phase-locked loop generates a reference clock input to the delay phase-locked loop, and the delay phase-locked loop obtains a multi-phase clock based on the reference clock. The phase selection module includes: a phase calculation module and a phase switching module; The phase calculation module calculates the clock index for the next cycle based on the PVT factor and the workload factor. （1） in, Indicates the clock index for the next cycle; Indicates the clock index of the current period; Indicates the number of phases in a multiphase clock; Indicates the periodic factor; （2） in, Indicates the workload factor; Represents the PVT factor; This represents a positive integer introduced to ensure clock quality; The phase switching module generates the clock signal for the next cycle based on the obtained clock index of the next cycle and the multiphase clock output generated by the multiphase clock generation module.

5. The adaptive clock system for developing reconfigurable processor timing margins according to claim 4, characterized in that, The module M1 employs the following methods: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case latency of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation latency and routing latency of each PE constitutes the workload latency of the current PE; by traversing all PEs in the array, the PE with the largest workload latency is identified; and the current maximum workload latency is quantified into a workload factor M. The compiler is optimized, including aggregating high-latency nodes into the same time slot and minimizing interconnection distances. Determine the initialization interval and generate a schedule using iterative modular scheduling; identify bottleneck nodes with limited frequency, and adjust node scheduling by allocating bottleneck nodes to the same time slots as much as possible while considering resource constraints; perform routing using a fast spatial mapping algorithm and an improved Dijkstra algorithm; if the current scheduling fails to achieve the preset layout and routing results, reschedule the bottleneck nodes and repeat the above steps; if all attempts to adjust the scheduling are unsuccessful, increase the initialization interval and perform rescheduling.

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