Chip design module splitting and recombining method and device, electronic equipment and storage medium
By adopting the chip design module split and reorganization method in integrated circuit chip design, the complexity and inefficiency problems in the conversion process from logical structure design to physical structure implementation are solved, and more efficient conversion and design and development efficiency are achieved.
Patent Information
- Application Number
- CN202411667519.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-02-28
AI Technical Summary
The prior art is difficult to effectively solve the problems of complexity and inefficiency in the transformation process from logical structure design to physical structure implementation in integrated circuit chip design.
Through a chip design module splitting and reorganization method, it includes obtaining logical hierarchy files, performing flattening operations, reorganizing according to preset physical hierarchy rules, and optimizing the connection structure of the tile module, and finally generating a physical hierarchy file.
It improves the conversion efficiency from logical structure design to physical structure implementation, reduces the conversion difficulty, and improves the efficiency of chip design and development by optimizing real-time feedback of content.
Smart Images
Figure CN119538819A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuit design, and in particular to a chip design module splitting and reorganization method, device, electronic device and storage medium. Background Art
[0002] As the scale of integrated circuits continues to expand, the number of internal modules in the chip is increasing, the organizational structure is becoming more and more complex, and the module functions are becoming more and more complicated. This has brought huge challenges to the design of integrated circuits today, especially the conversion between the front-end logical structure design and the back-end physical structure implementation, which has brought increasingly difficult challenges. Summary of the invention
[0003] In view of this, the present disclosure provides a chip design module splitting and reorganization method, device, electronic device and storage medium to achieve the conversion from logical view to tile view in the chip design process, help improve the conversion efficiency from logical structure design to physical structure implementation, and help reduce the difficulty of conversion.
[0004] The technical solution of the present disclosure is achieved as follows:
[0005] According to one aspect of an embodiment of the present disclosure, a chip design module splitting and reorganization method is provided, comprising:
[0006] Acquire a chip logic hierarchy file containing logic hierarchy content, wherein the logic hierarchy content includes a plurality of logic modules, each of which is composed of at least one integrated circuit unit;
[0007] Performing a flattening operation on the logic hierarchy structure content to obtain a flattened structure content, wherein the flattened structure content includes all the integrated circuit units constituting the plurality of logic modules;
[0008] According to a preset physical hierarchy rule, each of the integrated circuit units in the flattened structure content is reorganized to obtain a physical hierarchy content, wherein the physical hierarchy content includes a plurality of tile modules, and each tile module includes at least one integrated circuit unit;
[0009] According to the positional relationship between each tile module and the circuit connection relationship between each tile module in the physical hierarchy content, the connection structure of the tile module is optimized and modified to obtain the physical hierarchy content; and
[0010] A chip physical hierarchy file containing the physical hierarchy optimization content is generated.
[0011] In a possible implementation, performing a flattening operation on the logical hierarchical structure content includes:
[0012] The hierarchical structure of the logic module is removed so that all the integrated circuit units in the content of the logic hierarchy are in the same hierarchical structure.
[0013] In a possible implementation manner, the step of reorganizing the integrated circuit units in the flattened structure content to obtain the physical hierarchical structure content includes:
[0014] changing the position of at least one of the integrated circuit units;
[0015] The plurality of tile modules are established, each of which includes at least two adjacently located integrated circuit units.
[0016] In a possible implementation manner, the reorganizing the integrated circuit units in the flattened structure content according to a preset physical hierarchy rule to obtain the physical hierarchy content includes:
[0017] Rename the objects associated with each tile module in the physical hierarchy content.
[0018] In a possible implementation manner, after obtaining the physical hierarchical structure content and before optimizing and modifying the connection structure of the tile module, the chip design module splitting and reorganizing method further includes:
[0019] For at least two different tile modules with the same structure in the physical hierarchical structure content, any one of the tile modules is retained and reused to replace other tile modules with the same structure as the any one tile module.
[0020] In a possible implementation manner, after obtaining the physical hierarchical structure content and before optimizing and modifying the connection structure of the tile module, the method further includes:
[0021] Inserting a DFT interface and a DFT module into the tile module;
[0022] Alternatively, a DFT interface is inserted into the tile module and a position for the DFT module is reserved in the tile module.
[0023] In a possible implementation manner, the optimizing and modifying the connection structure of the tile module includes:
[0024] For any two tile modules that are connected but not adjacent, a feedthrough line is established to connect the any two tile modules. The feedthrough line runs through other tile modules between the any two tile modules, and the feedthrough line does not change the functions of other tile modules between the any two tile modules.
[0025] In a possible implementation manner, the optimizing and modifying the connection structure of the tile module includes:
[0026] When the communication link between any two tile modules exceeds a preset communication link length rule threshold, a pipeline register is inserted into the communication link between the any two tile modules, and the pipeline register is set in other tile modules between the any two tile modules, and the pipeline register does not change the functions of other tile modules between the any two tile modules.
[0027] In a possible implementation manner, the optimizing and modifying the connection structure of the tile module includes:
[0028] In the case where any tile module is simultaneously connected to at least two other tile modules through one port, the port is replicated according to the number of the at least two other tile modules;
[0029] The arbitrary tile module is connected to each tile module of the at least two other tile modules through the replicated ports.
[0030] In a possible implementation manner, the optimizing and modifying the connection structure of the tile module includes:
[0031] In the case that any tile module has an input constant signal, a constant module associated with the constant signal is added at a position adjacent to the any tile module, and the constant module is connected to the any tile module.
[0032] In a possible implementation manner, after obtaining the physical hierarchy optimization content, the chip design module splitting and reorganization method further includes:
[0033] The physical hierarchy optimization content is uniquely configured.
[0034] In a possible implementation manner, after generating the chip physical hierarchy file, the method further includes:
[0035] A functional consistency check is performed on the chip physical hierarchy file and the chip logical hierarchy file.
[0036] According to another aspect of an embodiment of the present disclosure, a chip design module splitting and reorganizing device is provided, comprising:
[0037] A file acquisition module is configured to execute acquisition of a chip logic hierarchy file containing logic hierarchy content, wherein the logic hierarchy content includes a plurality of logic modules, each of which is composed of a plurality of integrated circuit units;
[0038] A flattening module, configured to perform a flattening operation on the logic hierarchy structure content to obtain a flattened structure content, wherein the flattened structure content includes all the integrated circuit units constituting the plurality of logic modules;
[0039] a reorganization module configured to reorganize the integrated circuit units in the flattened structure content according to a preset physical hierarchy rule to obtain a physical hierarchy content, wherein the physical hierarchy content includes a plurality of tile modules, and each tile module includes at least one integrated circuit unit;
[0040] a structure optimization module configured to optimize and modify the connection structure of the tile modules according to the positional relationship between the tile modules and the circuit connection relationship between the tile modules in the physical hierarchy content to obtain physical hierarchy content; and
[0041] The file generation module is configured to generate a chip physical hierarchy file containing the physical hierarchy optimization content.
[0042] According to another aspect of an embodiment of the present disclosure, there is provided an electronic device, including:
[0043] processor;
[0044] a memory for storing executable instructions for the processor;
[0045] Wherein, the processor is configured to execute the executable instructions to implement the chip design module splitting and reorganization method as described in any one of the above items.
[0046] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the chip design module splitting and reorganization method as described in any one of the above items.
[0047] It can be seen from the above scheme that the chip design module splitting and reorganization method, device, electronic device and storage medium disclosed in the present invention are helpful for the conversion from logical hierarchy content to physical hierarchy content during the chip design and development process, and provide a comprehensive method platform between front-end design and back-end design. Based on the chip design module splitting and reorganization method, device, electronic device and storage medium disclosed in the present invention, in the process of executing the splitting and reorganization, optimization and modification suggestions can be fed back to the front-end designer in the first time according to the optimized content, which is helpful for timely communication between back-end design and front-end design, thereby helping to improve the design and development efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 is a schematic flow chart of a chip design module splitting and reorganizing method according to an exemplary embodiment;
[0049] Figure 2A is a schematic logical view of the content of a logical hierarchy structure according to an exemplary embodiment;
[0050] Figure 2B is a schematic flattened view of a flattened structure content according to an exemplary embodiment;
[0051] Figure 2C is a schematic tile view of physical hierarchy content according to an exemplary embodiment;
[0052] Figure 3 is a schematic diagram of a process of reorganizing each integrated circuit unit in a flattened structure content according to an exemplary embodiment;
[0053] Figure 4 is a schematic diagram showing tile module reuse according to an exemplary embodiment;
[0054] Figure 5 is a schematic diagram of a schematic tile module structure before and after the DFT interface and the DFT module are inserted according to an exemplary embodiment;
[0055] Figure 6 is a schematic tile view before and after inserting a feed-through line according to an exemplary embodiment;
[0056] Figure 7 is a schematic tile view before and after inserting a pipeline register according to an exemplary embodiment;
[0057] Figure 8 is a schematic tile view before and after port optimization according to an exemplary embodiment;
[0058] Fig. 9is a schematic tile view before and after constant signal optimization according to an exemplary embodiment;
[0059] Fig.10 is a schematic diagram of a chip design module splitting and reorganization system provided by an embodiment of the present disclosure;
[0060] Fig.11 It is a schematic diagram of an application scenario flow chart of a chip design module splitting and reorganizing method according to an exemplary embodiment;
[0061] Fig.12 is a schematic diagram of the logical structure of a chip design module splitting and reorganizing device according to an exemplary embodiment;
[0062] Fig.13 It is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0063] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.
[0064] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0065] With the continuous development of semiconductor technology, the scale of chips is getting larger and larger. Due to the limitations of tools such as synthesis, layout, and static timing analysis (STA) in electronic design automation (EDA), there may be a mismatch between the redivision of function blocks in chips and the needs of back-end design.
[0066] When designing a chip, front-end designers divide the modules according to their functions and obtain functional modules at the logic level. These functional modules are usually described by register transfer level (RTL) codes. These functional modules will be converted into specific logical implementations that can reflect the physical structure of the circuit through a synthesis process. This logical implementation that can reflect the physical structure of the circuit is usually described by a gate-level netlist (Gate-Level Netlist), also known as a netlist.
[0067] Because there is a connection between the development process of front-end design and back-end design, and chip design usually adopts an iterative process, various problems are inevitable in the design process.
[0068] For example, in the synthesis process, the data size of the functional module directly determines the duration of the synthesis process. If the data size of the functional module is too large, the synthesis process may take several days to execute. Therefore, the data size of the functional module should not be too large. If the data size of the functional module is too small, the designed chip may contain too many functional modules, which will increase the number of designers designing for different functional modules and waste human resources. Therefore, the data size of the functional module should not be too small.
[0069] For example, when designing, front-end designers usually do not consider the needs of flow planning in the back-end physical design (PD) stage. There is usually an iteration between the design provided by the front-end designer and the back-end physical design. Because the placement of modules in the physical layout is of special significance, if there is interaction (talk) between two modules in the physical layout, but the two modules are far apart in a layout and there are other modules placed between the two modules, it is necessary to feedback to the front-end designer to insert corresponding objects in other modules between the two modules, such as pipeline registers (pipeline flops), etc., to ensure normal interaction between the two modules and not change the functions of other modules. With the complexity of integrated circuits, the workload of such feedback to front-end designers for modification may become larger and larger, resulting in a reduction in the speed of R&D iteration and affecting the efficiency of chip development.
[0070] In view of this, the embodiments of the present disclosure provide a chip design module splitting and reorganization method, device, electronic device and storage medium to address the problems existing in the current chip design process, so as to help improve the efficiency of the integration stage between front-end design and back-end design.
[0071] Figure 1 FIG. 1 is a flow chart of a chip design module splitting and reorganizing method according to an exemplary embodiment. Figure 1 As shown, the chip design module splitting and reorganization method mainly includes the following steps 101 to 105.
[0072] Step 101: Obtain a chip logic hierarchy file containing logic hierarchy content, wherein the logic hierarchy content includes a plurality of logic modules, and each logic module is composed of a plurality of integrated circuit units;
[0073] Step 102: performing a flatten operation on the logic hierarchy structure content to obtain a flattened structure content, wherein the flattened structure content includes all integrated circuit units constituting a plurality of logic modules;
[0074] Step 103: reorganize the integrated circuit units in the flattened structure content according to a preset physical hierarchy rule to obtain a physical hierarchy content, wherein the physical hierarchy content includes a plurality of tile modules, and each tile module includes at least one integrated circuit unit;
[0075] Step 104: According to the positional relationship between each tile module and the circuit connection relationship between each tile module in the physical hierarchy content, the connection structure of the tile module is optimized and modified to obtain the physical hierarchy content;
[0076] Step 105: Generate a chip physical hierarchy file containing physical hierarchy optimization content.
[0077] In an exemplary embodiment, the chip logic hierarchy file containing logic hierarchy content may be, for example, an RTL file. The RTL file contains logic hierarchy content.
[0078] In the exemplary embodiment, the logic module is a module designed based on the front-end chip functions. Figure 2A Schematic logical view of the logical hierarchy content according to an exemplary embodiment. Figure 2A As shown, the logic hierarchy content is a chip chip, which includes a first logic module 11, a second logic module 12 and a third logic module 13. The first logic module 11 is composed of integrated circuit units A0, A1, B0 and B1, the second logic module 12 is composed of integrated circuit units C, D and E, and the third logic module 13 is composed of integrated circuit unit H. Figure 2AIn the logical hierarchy content shown, integrated circuit unit A0, integrated circuit unit A1, integrated circuit unit B0 and integrated circuit unit B1 belong to the level of the first logic module 11, the second logic module 12 is composed of integrated circuit unit C, integrated circuit unit D and integrated circuit unit E, which belong to the level of the second logic module 12, and integrated circuit unit H belongs to the level of the third logic module 13. It can be seen that each integrated circuit unit in the logical hierarchy content may belong to a different logic module level. In the exemplary embodiment, the division and development of each logic module is carried out in the front-end design according to the functional requirements of the module. It should be noted that, although not shown, Figure 2A There is a logical connection relationship between the logic modules and the integrated circuit units shown.
[0079] In an exemplary embodiment, performing a flattening operation on the logic hierarchy content in step 102 may include: removing the hierarchical structure of the logic module so that all integrated circuit units in the logic hierarchy content are in the same hierarchical structure.
[0080] Figure 2B is a schematic flattened view of a flattened structure content according to an exemplary embodiment. Figure 2B As shown, in the flattened structure, the chip chip includes integrated circuit unit A0, integrated circuit unit A1, integrated circuit unit B0, integrated circuit unit B1, integrated circuit unit C, integrated circuit unit D, integrated circuit unit E and integrated circuit unit H, and these integrated circuit units constitute the integrated circuit unit level. It can be seen that the chip chip only contains the integrated circuit unit level, compared with Figure 2A The logical hierarchy content shown, Figure 2B The flattened structure content shown removes the hierarchical structure of the logic module, and all integrated circuit units are flattened to the same integrated circuit unit level. Through step 102, the module level of the logical hierarchical structure content is broken, which is conducive to the subsequent adjustment of the position of each integrated circuit unit, so that when the position of a certain integrated circuit unit is adjusted, other integrated circuit units will not be constrained by the logic module and change their positions accordingly. For example, when the position of integrated circuit unit A0 is to be adjusted, integrated circuit unit A1, integrated circuit unit B0 and integrated circuit unit B1 will no longer be constrained by the first logic module 11 and change their positions along with integrated circuit unit A0.
[0081] The execution of the chip design module splitting and reorganization method of the embodiment of the present disclosure depends on the computer device. The computer device requires certain grammatical standards when executing the program. Based on this, in the exemplary embodiment, before executing the reorganization, it can further include: performing a grammatical check on the data of the flattened structure content, and deleting the grammatical part that affects the execution of the reorganization process.
[0082] Figure 3 is a schematic diagram of a process of reorganizing each integrated circuit unit in a flattened structure content according to an exemplary embodiment, such as Figure 3 As shown, in the exemplary embodiment, the step 103 of reorganizing the integrated circuit units in the flattened structure content to obtain the physical hierarchical structure content mainly includes the following steps 301 to 302.
[0083] Step 301, changing the position of at least one integrated circuit unit;
[0084] Step 302: Establish a plurality of tile modules, each of which includes at least two adjacent integrated circuit units.
[0085] After the above steps 301 to 302, the physical hierarchical structure content can be obtained. In the exemplary embodiment, the tile module is a module based on the physical layout design of the back-end chip. Figure 2C is a schematic tile view of the physical hierarchical content according to an exemplary embodiment, such as Figure 2C Combined with Figure 2B As shown, in step 301, the positions of integrated circuit unit A1, integrated circuit unit B0, integrated circuit unit B1, integrated circuit unit C, integrated circuit unit D, integrated circuit unit E and integrated circuit unit H are mainly changed, that is, these integrated circuit units are moved, wherein the positions of these integrated circuit units are changed according to preset physical hierarchy rules, and the changed positions need to meet the relevant requirements of the physical hierarchy rules.
[0086] In step 302, the tile module is established according to the preset physical hierarchy rules. Figure 2C As shown, after changing the positions of each integrated circuit unit, in step 302, three tile modules are established according to the preset physical hierarchy rules, namely the first tile module 21, the second tile module 22 and the third tile module 23, wherein the first tile module 21 includes the integrated circuit unit A0, the integrated circuit unit B0 and the integrated circuit unit C, the second tile module 22 includes the integrated circuit unit A1, the integrated circuit unit B1 and the integrated circuit unit D, and the third tile module 23 includes the integrated circuit unit H and the integrated circuit unit E. Figure 2C The tile view shown is the same as Figure 2A Compared to the logical view shown in the figure, the hierarchy has changed significantly, among which, Figure 2A In the logic view shown, each logic module is a different logic function module designed according to the functional requirements in the front-end design. Figure 2C In the tile view shown, each tile module is a regional module arranged according to the requirements of the physical space layout of each part of the chip during chip preparation. This regional module will be arranged at various positions in the physical layout of the chip. Therefore, adjacent tile modules are arranged side by side (ABUT, also known as adjacent, adjacent or close).
[0087] It should be noted that during the execution of step 301 and step 302, the connection relationship (interaction relationship) between the various integrated circuit units does not change, so as to ensure the consistency between the circuits of the physical hierarchical structure content and the circuits of the logical hierarchical structure content.
[0088] The execution of the chip design module splitting and reorganization method of the embodiment of the present disclosure depends on computer equipment. Therefore, when reorganizing the various integrated circuit units in the flattened structure content, it is also necessary to name the reorganized related content accordingly to meet the needs of further processing. Based on this, in the exemplary embodiment, step 103 can further include: renaming the objects associated with each tile module in the physical hierarchical structure content.
[0089] In an exemplary embodiment, objects associated with a tile module may include, for example, an instance (inst), a port (port), and a network (net).
[0090] Due to the complexity of large-scale integrated circuits, there will be circuit structure parts with the same functions between multiple logic modules designed in the front end, and then there will be different tile modules with the same structure in the multiple tile modules obtained after flattening and reorganization, because each tile module will eventually occupy a part of the data space in the chip physical hierarchy file finally generated, which will eventually lead to a large amount of data in the chip physical hierarchy file, resulting in data resources and subsequent processing resource consumption, and will reduce processing efficiency. Based on this, in an illustrative embodiment, after obtaining the physical hierarchy content in step 103 and before optimizing and modifying the connection structure of the tile module in step 104, the chip design module splitting and reorganization method of the embodiment of the present disclosure can further include: for at least two different tile modules with the same structure in the physical hierarchy content, retain any one of the tile modules and reuse the any one tile module to replace other tile modules with the same structure as the any one tile module.
[0091] Figure 4is a schematic diagram showing tile module reuse according to an exemplary embodiment, such as Figure 4 As shown, the second tile module 22 and the third tile module 23 are both connected (interacted) with the first tile module 21, and the second tile module 22 and the third tile module 23 are respectively located on different sides of the first tile module 21, wherein the second tile module 22 and the third tile module 23 have the same structure, for example, both include an integrated circuit unit A and an integrated circuit unit B, in which case, any one of the tile modules can be retained and reused, for example, the second tile module 22 is retained and reused to replace the third tile module 23. This can save the amount of data of the physical hierarchical structure file, is conducive to saving data resources and processing resources, and helps to improve processing efficiency.
[0092] In an illustrative embodiment, after completing step 103 to obtain the physical hierarchy content, and before executing step 104 to optimize and modify the connection structure of the tile module, the chip design module splitting and reorganization method of the disclosed embodiment may further include: inserting a DFT (Design for Test) interface and a DFT module into the tile module; or, inserting a DFT interface into the tile module and reserving a position for the DFT module in the tile module.
[0093] Among them, the DFT module is a test circuit that can be introduced during the integrated circuit design stage. The purpose of inserting the DFT module is to improve the testability of the chip and ensure that defects generated during the manufacturing process can be effectively detected. It plays an important role in improving chip testing efficiency, reducing testing costs, and improving product quality. Using the DFT module, the testing needs can be taken into account during the chip design stage, so that problems can be discovered and corrected more efficiently during the subsequent manufacturing and testing processes.
[0094] Because the DFT module is a module independent of the integrated circuit unit, inserting the DFT interface and the DFT module or inserting the DFT and reserving the position of the DFT module will not change the original circuit function of the tile module and will help with subsequent testing. Among them, the DFT interface is an interface for connecting the DFT module. In order to facilitate the subsequent connection of related test circuits, the DFT interface can be inserted here. The DFT module can be inserted into the physical hierarchy content together with the DFT interface as needed, or it can be inserted into the reserved position in the subsequent stage as appropriate.
[0095] Figure 5 is a schematic diagram of a schematic tile module structure before and after the DFT interface and the DFT module are inserted according to an exemplary embodiment, such as Figure 5As shown, in the exemplary embodiment, the tile module originally includes an integrated circuit unit A and an integrated circuit unit B, the integrated circuit unit A and the integrated circuit unit B are connected (interacted), and the tile module also includes corresponding ports connected to the integrated circuit unit A and the integrated circuit unit B. In the exemplary embodiment, the inserted DFT interface and DFT module 201 can be placed in an area of the tile module that does not affect the integrated circuit unit A and the integrated circuit unit B, for example Figure 5 The DFT module 201 is located below the integrated circuit unit A and the integrated circuit unit B in the embodiment, and the DFT interface and the DFT module 201 are independent of the integrated circuit unit A and the integrated circuit unit B and the corresponding interface. In the exemplary embodiment, the DFT module 201 may further include a DFT client module and a DFT server module.
[0096] When adjusting the positions of the integrated circuit units, since the connection relationship (interaction relationship) between the integrated circuit units is not changed, after the multiple tile modules are reorganized, the existence of flying wires connected between non-adjacent tile modules and across other tile modules will be caused by this connection relationship. However, since the adjacent tile modules are arranged side by side (ABUT, which can be called adjacent, adjacent or close), the structure with flying wires is usually not allowed. It is necessary to eliminate such flying wires and connect the non-adjacent tile modules through feedthrough lines passing through other tile modules. Based on this, in the exemplary embodiment, the optimization and modification of the connection structure of the tile module in step 104 may include:
[0097] For any two tile modules that are connected but not adjacent, a feedthrough line is established to connect the two tile modules. The feedthrough line runs through other tile modules between the two tile modules, and the feedthrough line does not change the functions of other tile modules between the two tile modules.
[0098] Figure 6 FIG. 1 is a schematic tile view before and after inserting a feedthrough line according to an exemplary embodiment. Figure 6 Although not specifically shown, in fact, the first tile module 21, the second tile module 22, the third tile module 23 and the fourth tile module 24 are arranged side by side in sequence. Figure 6As shown, the second tile module 22 is located between the first tile module 21 and the third tile module 23, and the third tile module 23 is located between the second tile module 22 and the fourth tile module 24. Before the feedthrough line is inserted, the third tile module 23 sends information to the first tile module 21 through the flying line, and the first tile module 21 sends information to the third tile module 23 and the fourth tile module 24 through the flying line. According to the connection (interaction) relationship of the flying line, the feedthrough line is inserted into the second tile module 22 and the third tile module 23. After the feedthrough line is inserted, the third tile module 23 sends information to the first tile module 21 through the feedthrough line (indicated by the dotted line) in the second tile module 22, the first tile module 21 sends information to the third tile module 23 through the feedthrough line (indicated by the dotted line) in the second tile module 22, and the first tile module 21 sends information to the fourth tile module 24 through the feedthrough line in the second tile module 22 and the feedthrough line in the third tile module 23 (indicated by the dotted line). After the feed-through line is inserted, the feed-through line replaces the original flying line to connect the tile modules, and the original flying line is deleted accordingly after the feed-through line is inserted.
[0099] In logic design, the communication between two logic modules or between two integrated circuit units is not limited by distance. However, in actual physical links, if the distance between two tile modules or between two integrated circuit units is too far, there is a delay in the signal or even failure to communicate because the communication link between the two is too long, resulting in failure to transmit information normally. In the embodiment of the present disclosure, after flattening and reorganization, there may be communication between tile modules that are far away, which may cause the above-mentioned problem. In this case, it can be optimized by inserting pipeline registers in the communication link. Therefore, in the exemplary embodiment, the optimization and modification of the connection structure of the tile module in step 104 may include:
[0100] When the communication link between any two tile modules exceeds the preset communication link length rule threshold, a pipeline register is inserted into the communication link between the any two tile modules, and the pipeline register is set in other tile modules between the any two tile modules, and the pipeline register does not change the functions of other tile modules between the any two tile modules.
[0101] Among them, after the pipeline register is inserted, the pipeline register may affect the function of the circuit associated with the inserted tile module. Therefore, in the exemplary embodiment, after the pipeline register is inserted, it can further include performing a functional test on the circuit associated with the tile module after the pipeline register is inserted to ensure that the function of the circuit associated with the tile module after the pipeline register is inserted remains unchanged.
[0102] In an illustrative embodiment, the pipeline register can be directly inserted into the tile module, or it can be inserted into the logical hierarchy content associated with the tile module. When the method of inserting into the logical hierarchy content associated with the tile module is adopted, the chip design module splitting and reorganization method of the embodiment of the present disclosure may further include: after inserting the pipeline register into the logical hierarchy content associated with the tile module, by performing a flattening operation on the logical hierarchy content again, and reorganizing the various integrated circuit units in the flattened structure content, an updated physical hierarchy content is obtained. Because when inserting the pipeline register into the logical hierarchy content associated with the tile module, it is necessary to ensure that the functions of the various logic modules in the original logical hierarchy content are not changed, therefore, doing so helps to ensure that the circuit function of the physical hierarchy content after the pipeline register is inserted will not be changed, and helps to ensure the consistency between the chip circuit in the physical hierarchy content and the chip circuit in the logical hierarchy content.
[0103] Figure 7 is a schematic tile view before and after inserting a pipeline register according to an exemplary embodiment, wherein it should be noted that although Figure 7 Although not specifically shown, in fact, the first tile module 21, the second tile module 22, the third tile module 23 and the fourth tile module 24 are arranged side by side in sequence, the second tile module 22 is located between the first tile module 21 and the third tile module 23, and the third tile module 23 is located between the second tile module 22 and the fourth tile module 24. Before inserting the pipeline register 202, the third tile module 23 sends information to the first tile module 21 through the flying wire, and the first tile module 21 sends information to the fourth tile module 24 through the flying wire. The pipeline register 202 is inserted according to the connection (interaction) relationship of the flying wire, wherein three pipeline registers 202 are inserted in the second tile module 22 and one pipeline register 202 is inserted in the third tile module 23. Among them, the third tile module 23 sends information to the first tile module 21 through the flying wire, and the third tile module 23 sends information through the three pipeline registers 202 inserted in the second tile module 22. Figure 7 The upper pipeline register 202 shown in FIG. sends information to the first tile module 21; the first tile module 21 sends information to the fourth tile module 24 through a flying line, and the first tile module 21 sends information to the fourth tile module 24 through the three pipeline registers 202 inserted in the second tile module 22. Figure 7The following two pipeline registers 202 shown in FIG. 1 and a pipeline register 202 inserted in the third tile module 23 send information to the fourth tile module 24. Correspondingly, the clock signal input terminal clk connected to each tile module is also connected to the clock port of each inserted pipeline register 202. After the pipeline register is inserted to replace the original flying wire, the original flying wire is deleted accordingly.
[0104] Through the above-mentioned method, by utilizing the inserted pipeline register, the signal delay in a longer communication link can be reduced or even eliminated, which helps to improve the communication quality between various tile modules, especially tile modules that are far apart.
[0105] Since there is no need to consider the structural connection form between modules in logic design, the same signal or connection form output by a logic module to other two logic modules is usually expressed by separating two lines from a signal output port of a logic module and connecting to the respective signal input ports of the other two logic modules. However, in physical implementation, tile modules cannot be connected in this way. When a tile module needs to output the same signal to other two tile modules, the tile module must send out the same signal through two signal output ports respectively, that is, the tile module must be connected to the respective signal input ports of the other two tile modules through two signal output ports. Therefore, the chip design module splitting and reorganization method of the embodiment of the present disclosure may also include the optimization of ports. Based on this, in the illustrative embodiment, the optimization and modification of the connection structure of the tile module in step 104 may include:
[0106] In the case where any tile module is simultaneously connected to at least two other tile modules through one port, the port is replicated according to the number of the at least two other tile modules;
[0107] The arbitrary tile module is connected to each tile module of the at least two other tile modules through the replicated ports.
[0108] Figure 8 is a schematic tile view before and after port optimization according to an exemplary embodiment, such as Figure 8As shown, before the port optimization, the first tile module 21 is connected to the second tile module 22, the third tile module 23 and the fourth tile module 24 through one of its signal output ports. During the optimization, because the signal output port of the first tile module 21 is simultaneously connected to three other tile modules (the second tile module 22, the third tile module 23 and the fourth tile module 24), the signal output port is copied to two identical signal output ports, so the number of signal output ports becomes three, and the first tile module 21 is connected to each of the second tile module 22, the third tile module 23 and the fourth tile module 24 through these three signal output ports. It should be noted that Figure 8 This is only a schematic illustration of the port optimization. In practice, the tile modules are arranged side by side, and the communication links between the tile modules are also optimized through the above-mentioned feedthrough lines and pipeline registers 202.
[0109] There are constant signals in the chip (for example, a high-level signal that always expresses 1 and a low-level signal that always expresses 0). These constant signals are only indicated by marks in the front-end design. However, in hardware implementation, the constant signal is generated by the corresponding hardware circuit that can generate the constant signal. Therefore, it is also necessary to optimize and modify the connection structure of the tile module for the constant signal. Based on this, in the exemplary embodiment, the optimization and modification of the connection structure of the tile module in step 104 may include:
[0110] In the case that any tile module has an input constant signal, a constant module associated with the constant signal is added at a position adjacent to the any tile module, and the constant module is connected to the any tile module.
[0111] In an illustrative embodiment, the added constant module is arranged side by side with the tile module. In an illustrative embodiment, the constant module can be, for example, a module composed of a voltage clamping unit (Tie Cell). The voltage clamping unit is a special standard cell (Standard Cell) that has no input pin (input pin) but only an output pin (output pin). The voltage clamping unit mainly includes a high voltage clamping unit (Tie High Cell) and a low voltage clamping unit (TieLow Cell), wherein the high voltage clamping unit outputs a high level signal for representing "1", and the low voltage clamping unit outputs a low level for representing "0".
[0112] Fig. 9 is a schematic tile view before and after constant signal optimization according to an exemplary embodiment, such as Fig. 9As shown, before the constant signal is optimized, the first tile module 21 has an input constant signal 3'd0, and 3'd0 indicates that it is a low-level signal. During optimization, according to the input constant signal 3'd0, a constant module 26 associated with the constant signal 3'd0 is added at a position adjacent to the first tile module 21, and the constant module 26 is connected to the first tile module 21, and the constant module 26 inputs a low-level signal to the first tile module 21, wherein the constant module 26 and the first tile module 21 are arranged side by side.
[0113] In an exemplary embodiment, after completing step 104 to obtain the physical hierarchy optimization content, the chip design module splitting and reorganization method of the embodiment of the present disclosure further includes:
[0114] Uniquify the physical hierarchy optimization content.
[0115] Uniqueness can be understood as the uniqueness of the names of each object (such as a module) in the physical hierarchy optimization content, ensuring that each object in the physical hierarchy optimization content has a unique identifier, for example, ensuring that the register name and signal line name in the design are unique in the entire design. Uniqueness of the names of each object in the physical hierarchy optimization content can ensure that any specified object can be modified without affecting other modules in the subsequent further modification and optimization.
[0116] In addition, different logic modules designed by different personnel in the front-end design may also call different memories. The memories in the physical hierarchy content are usually automatically generated all at once. Therefore, different logic modules may also call different memories to be unique, which can avoid conflicts in different logic modules calling the same memory.
[0117] In order to ensure that the chip circuit in the chip physical hierarchy file finally generated after the chip design module is split and reorganized does not have functional errors due to the split and reorganization. In an illustrative embodiment, after completing step 105 of generating the chip physical hierarchy file, the chip design module split and reorganization method of the embodiment of the present disclosure may further include:
[0118] Perform functional consistency check on the chip physical hierarchy file and the chip logical hierarchy file.
[0119] In the exemplary embodiment, if the functional consistency check passes, it indicates that the functions of the circuit content in the chip physical hierarchy file and the circuit content in the chip logical hierarchy file are consistent and meet the design requirements, so that the subsequent design stage can be entered.
[0120] According to each step of the embodiment of the present disclosure, a corresponding TCL (Tool Command Language) script may be designed and implemented through automated operation.
[0121] Fig.10 FIG. 1 is a schematic diagram of a chip design module splitting and reorganization system provided by an embodiment of the present disclosure. Fig.10 As shown, the chip design system 100 includes a processor 110 and a storage device 120, the storage device 120 is coupled to the processor 110, and in an exemplary embodiment, the chip design system 100 may be, for example, a server system, and the storage device 120 and the processor 110 are coupled via a bus system in the server system. In an exemplary embodiment, the storage device 120 is used to store programs, scripts, files, data, etc. In an exemplary embodiment, the processor 110 may execute electronic design automation programs and scripts to perform chip design module splitting and reorganization for chip logic hierarchy files. Files and data may include chip logic hierarchy files, chip physical hierarchy files, and intermediate file data and temporary file data generated during the execution of chip design module splitting and reorganization.
[0122] In an illustrative embodiment, the processor 110 may obtain corresponding results by calling the content (at least one of a program, a script, a file, and data) stored in the storage device 120 and performing corresponding processing. For example, the processor 110 may perform a flattening operation on the logical hierarchy content in the chip logical hierarchy file by calling the chip logical hierarchy file and the script and / or file for performing the flattening operation stored in the storage device 120, and the obtained flattened structure content may be temporarily stored in the storage device 120 as intermediate data or a file. The processor 110 may perform a reorganization operation on the flattened structure content by calling the physical hierarchy rule data and the relevant script and / or file for performing the reorganization operation stored in the storage device 120, and the obtained physical hierarchy content may be temporarily stored in the storage device 120 as intermediate data or a file. The processor 110 may perform an optimization modification operation on the physical hierarchy content by calling the relevant script and / or file for performing the optimization modification stored in the storage device 120, generate a chip physical hierarchy file containing the physical hierarchy optimization content, and store the chip physical hierarchy file in the storage device 120. Before performing the optimization modification, the processor 110 can check and perform multiplexing on the tile modules in the physical hierarchy content by calling the relevant scripts and / or files for performing the multiplexing operation stored in the storage device 120. Before performing the optimization modification, the processor 110 can insert the DFT interface and the DFT module into the tile module of the physical hierarchy content, or insert the DFT interface into the tile module and reserve the position of the DFT module by calling the relevant scripts and / or files for performing the DFT insertion operation stored in the storage device 120. In the process of performing the optimization modification, the processor 110 can call the relevant data, scripts and / or files for performing the corresponding optimization modification projects from the storage device 120 according to different optimization modification projects, such as feedthrough line connection optimization, pipeline register optimization, port optimization, constant module optimization and other optimization modification projects, and perform the corresponding optimization modification. The obtained physical hierarchy optimization content can be temporarily stored in the storage device 120 as intermediate data or files. The processor 110 may perform a functional consistency check on the chip physical hierarchy file and the chip logical hierarchy file by calling the chip physical hierarchy file, the chip logical hierarchy file, and the script and / or file for consistency check stored in the storage device 120 .
[0123] In an exemplary embodiment, the processor 110 may be a central processing unit (CPU), other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD), other similar processing devices, or a combination of these devices. In an exemplary embodiment, the storage device 120 may be a computer-readable storage medium, on which computer-readable instructions are stored, and when the computer-readable instructions are executed by the processor 110, the steps in the chip design module splitting and reorganization method of the embodiment of the present disclosure may be executed. In an exemplary embodiment, the computer-readable storage medium may be, for example, a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories, wherein the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory, and the volatile memory may be a random access memory (RAM), which is used as an external cache. By way of exemplary but not limiting description, various forms of RAM may be used, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), direct memory bus random access memory (DR RAM), etc. The storage device 120 may store data, scripts, programs, software, algorithms, etc. required for implementing each step of the chip design module splitting and reorganizing method according to the embodiment of the present disclosure, and provide the processor 110 with execution.
[0124] The chip design module splitting and reorganization method of the disclosed embodiment helps to convert the logical hierarchy content to the physical hierarchy content during the chip design and development process, and provides a comprehensive method platform between the front-end design and the back-end design. Based on the chip design module splitting and reorganization method of the disclosed embodiment, during the process of executing the splitting and reorganization, optimization and modification suggestions can be fed back to the front-end designers in the first time according to the optimized content, which helps to communicate in time between the back-end design and the front-end design, thereby helping to improve the design and development efficiency of the chip.
[0125] Fig.11 FIG. 1 is a schematic flow chart of an application scenario of a chip design module splitting and reorganizing method according to an exemplary embodiment. Fig.11 As shown, the application scenario process mainly includes the following steps 1101 to 1115.
[0126] Step 1101: Obtain a chip logic hierarchy file containing logic hierarchy content.
[0127] The logic hierarchy content is obtained from the chip logic hierarchy file.
[0128] Step 1102: Generate a TCL script for splitting and reorganizing chip design modules.
[0129] The relevant TCL script can be automatically generated by splitting and reorganizing the relevant instructions and configuration parameters according to the preset chip design module. The TCL script is used to execute the subsequent steps.
[0130] Step 1103: Perform a flattening operation on the logical hierarchical structure content to obtain a flattened structure content.
[0131] Step 1104: Perform a syntax check on the data of the flattened structure content, and delete the syntax part that affects the execution of the reorganization process.
[0132] Step 1105: reorganize the integrated circuit units in the flattened structure content according to the preset physical hierarchy rule to obtain the physical hierarchy content.
[0133] Step 1106: Rename the objects associated with each tile module in the physical hierarchy content.
[0134] Step 1107: For different tile modules with the same structure in the physical hierarchical structure content, retain one of the tile modules and reuse it.
[0135] Step 1108: Generate a chip physical hierarchy intermediate file containing physical hierarchy content.
[0136] After that, subsequent optimization and modification steps can be performed on the connection structure of the tile module based on the intermediate file of the chip physical hierarchy.
[0137] Step 1109: Insert the DFT structure into the physical hierarchy content.
[0138] The DFT structure includes a DFT interface and a DFT module, or the DFT structure includes a DFT interface and a reserved position of the DFT module.
[0139] Step 1110: For the flying wires existing in the physical hierarchy content, insert feedthroughs into the relevant tile modules in the physical hierarchy content to replace the flying wires.
[0140] Step 1111: For the long-distance communication link existing in the physical hierarchy content, insert a pipeline register into the relevant tile module in the physical hierarchy content.
[0141] Step 1112: perform signal segmentation on the tile module.
[0142] Among them, signal segmentation includes the duplication of signal ports of multiple tile modules by one tile module and the setting of constant modules.
[0143] Step 1113: Unique the physical hierarchy optimization content.
[0144] Step 1114: Generate a chip physical hierarchy file containing physical hierarchy optimization content.
[0145] Step 1115: Perform a functional consistency check on the chip physical hierarchy file and the chip logical hierarchy file.
[0146] For further description of the above steps, please refer to the description of the above exemplary embodiments, which will not be repeated here.
[0147] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.
[0148] Fig.12 FIG. 1 is a schematic diagram showing a logical structure of a chip design module splitting and reorganizing device according to an exemplary embodiment. Fig.12As shown, the chip design module splitting and reorganization device includes a file acquisition module 1201, a flattening module 1202, a reorganization module 1203, a structure optimization module 1204 and a file generation module 1205. The file acquisition module 1201 is configured to execute the acquisition of a chip logic hierarchy file containing a logic hierarchy content, wherein the logic hierarchy content includes a plurality of logic modules, and each logic module is composed of a plurality of integrated circuit units. The flattening module 1202 is configured to perform a flattening operation on the logic hierarchy content to obtain a flattened structure content, wherein the flattened structure content includes all integrated circuit units that constitute the plurality of logic modules. The reorganization module 1203 is configured to execute the reorganization of each integrated circuit unit in the flattened structure content according to a preset physical hierarchy rule to obtain a physical hierarchy content, wherein the physical hierarchy content includes a plurality of tile modules, and each tile module includes at least one integrated circuit unit. The structure optimization module 1204 is configured to optimize and modify the connection structure of the tile modules according to the position relationship between the tile modules in the physical hierarchy content and the circuit connection relationship between the tile modules to obtain the physical hierarchy content. The file generation module 1205 is configured to generate a chip physical hierarchy file containing the physical hierarchy content.
[0149] In an exemplary embodiment, the flattening module 1202 is further configured to perform: removing the hierarchical structure of the logic module so that all integrated circuit units in the logic hierarchy content are in the same hierarchical structure.
[0150] In the exemplary embodiment, the reorganization module 1203 is further configured to execute: changing the position of at least one integrated circuit unit; establishing a plurality of tile modules, each tile module including at least two integrated circuit units located adjacently.
[0151] In the exemplary embodiment, the reorganization module 1203 is further configured to execute: renaming objects associated with each tile module in the physical hierarchical structure content.
[0152] In an illustrative embodiment, a multiplexing module is also included between the reorganization module 1203 and the structure optimization module 1204, which is configured to execute: for at least two different tile modules having the same structure in the physical hierarchical content, retain any one of the tile modules and reuse the any one of the tile modules to replace other tile modules having the same structure as the any one of the tile modules.
[0153] In an illustrative embodiment, a DFT insertion module is also included between the reorganization module 1203 and the structure optimization module 1204, which is configured to perform: inserting a DFT interface and a DFT module into the physical hierarchy content; or, inserting a DFT interface into the physical hierarchy content and reserving a position for the DFT module in the physical hierarchy content.
[0154] In an illustrative embodiment, the structural optimization module 1204 is further configured to perform: for any two tile modules that are connected but not adjacent, a feedthrough line is established for connecting the any two tile modules, the feedthrough line runs through other tile modules between the any two tile modules, and the feedthrough line does not change the functions of other tile modules between the any two tile modules.
[0155] In an illustrative embodiment, the structure optimization module 1204 is further configured to execute: when the communication link between any two tile modules exceeds a preset communication link length rule threshold, a pipeline register is inserted into the communication link between the any two tile modules, the pipeline register is set in other tile modules between the any two tile modules, and the pipeline register does not change the functions of other tile modules between the any two tile modules.
[0156] In the exemplary embodiment, the structure optimization module 1204 is further configured to perform: when any tile module is simultaneously connected to at least two other tile modules through one port, duplicating the port according to the number of the at least two other tile modules;
[0157] The arbitrary tile module is connected to each tile module of the at least two other tile modules through the replicated ports.
[0158] In the exemplary embodiment, the structure optimization module 1204 is further configured to perform: when there is an input constant signal in any tile module, add a constant module associated with the constant signal at a position adjacent to the any tile module, and connect the constant module to the any tile module.
[0159] In the exemplary embodiment, a uniqueness module is further included between the structure optimization module 1204 and the file generation module 1205, and is configured to execute: uniqueness of the physical hierarchical structure optimization content.
[0160] In an exemplary embodiment, the chip design module splitting and reassembling device further includes a consistency check module configured to execute: performing a functional consistency check on the chip physical hierarchy file and the chip logical hierarchy file.
[0161] Regarding the chip design module splitting and reorganizing device in the above embodiment, the specific manner in which each unit performs operations has been described in detail in the embodiment of the chip design module splitting and reorganizing method, and will not be elaborated here.
[0162] It should be noted that: the above embodiment only illustrates the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.
[0163] Fig.13 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. In some embodiments, the electronic device is a server. The electronic device 1300 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1301 and one or more memories 1302, wherein at least one program code is stored in the memory 1302, and the at least one program code is loaded and executed by the processor 1301 to implement the chip design module splitting and reorganization method provided in each of the above embodiments. Of course, the electronic device 1300 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The electronic device 1300 may also include other components for implementing device functions, which will not be repeated here.
[0164] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction. The at least one instruction can be executed by a processor in a computer device to complete the chip design module splitting and reorganization method in the above embodiment.
[0165] Optionally, the above-mentioned computer-readable storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may include ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk and optical data storage device, etc.
[0166] In an exemplary embodiment, a computer program product is also provided, including a computer program, which, when executed by a processor, implements the chip design module splitting and reorganization methods provided in the above-mentioned embodiments.
[0167] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.
Claims
1. A chip design module splitting and reorganization method, comprising: Acquire a chip logic hierarchy file containing logic hierarchy content, wherein the logic hierarchy content includes a plurality of logic modules, each of which is composed of at least one integrated circuit unit; Performing a flattening operation on the logic hierarchy structure content to obtain a flattened structure content, wherein the flattened structure content includes all the integrated circuit units constituting the plurality of logic modules; According to a preset physical hierarchy rule, each of the integrated circuit units in the flattened structure content is reorganized to obtain a physical hierarchy content, wherein the physical hierarchy content includes a plurality of tile modules, and each tile module includes at least one integrated circuit unit; According to the positional relationship between each tile module and the circuit connection relationship between each tile module in the physical hierarchy content, the connection structure of the tile module is optimized and modified to obtain the physical hierarchy content; and A chip physical hierarchy file containing the physical hierarchy optimization content is generated.
2. The chip design module splitting and reorganization method according to claim 1, characterized in that: The performing a flattening operation on the content of the logical hierarchy structure includes: The hierarchical structure of the logic module is removed so that all the integrated circuit units in the content of the logic hierarchy are in the same hierarchical structure.
3. The chip design module splitting and reorganization method according to claim 1, characterized in that: The step of reorganizing the integrated circuit units in the flattened structure content to obtain the physical hierarchical structure content includes: changing the position of at least one of the integrated circuit units; The plurality of tile modules are established, each of which includes at least two adjacently located integrated circuit units.
4. The chip design module splitting and reorganization method according to claim 1, characterized in that: The step of reorganizing the integrated circuit units in the flattened structure content according to a preset physical hierarchy rule to obtain the physical hierarchy content includes: Rename the objects associated with each tile module in the physical hierarchical structure content.
5. The chip design module splitting and reorganization method according to claim 1, characterized in that: After obtaining the physical hierarchy content and before optimizing and modifying the connection structure of the tile module, the chip design module splitting and reorganizing method further includes: For at least two different tile modules with the same structure in the physical hierarchical structure content, any one of the tile modules is retained and reused to replace other tile modules with the same structure as the any one tile module.
6. The chip design module splitting and reorganization method according to claim 1, characterized in that: After obtaining the physical hierarchy content and before optimizing and modifying the connection structure of the tile module, the method further includes: Inserting a DFT interface and a DFT module into the tile module; Alternatively, a DFT interface is inserted into the tile module and a position for the DFT module is reserved in the tile module.
7. The chip design module splitting and reorganization method according to claim 1, characterized in that: The optimizing and modifying the connection structure of the tile module includes: For any two tile modules that are connected but not adjacent, a feedthrough line is established to connect the any two tile modules. The feedthrough line runs through other tile modules between the any two tile modules, and the feedthrough line does not change the functions of other tile modules between the any two tile modules.
8. The chip design module splitting and reorganization method according to claim 1, characterized in that: The optimizing and modifying the connection structure of the tile module includes: When the communication link between any two tile modules exceeds a preset communication link length rule threshold, a pipeline register is inserted into the communication link between the any two tile modules, and the pipeline register is set in other tile modules between the any two tile modules, and the pipeline register does not change the functions of other tile modules between the any two tile modules.
9. The chip design module splitting and reorganization method according to claim 1, characterized in that: The optimizing and modifying the connection structure of the tile module includes: In the case where any tile module is simultaneously connected to at least two other tile modules through one port, the port is replicated according to the number of the at least two other tile modules; The arbitrary tile module is connected to each tile module of the at least two other tile modules through the replicated ports.
10. The chip design module splitting and reorganization method according to claim 1, characterized in that: The optimizing and modifying the connection structure of the tile module includes: In the case that any tile module has an input constant signal, a constant module associated with the constant signal is added at a position adjacent to the any tile module, and the constant module is connected to the any tile module.
11. The chip design module splitting and reorganization method according to claim 1, characterized in that: After obtaining the physical hierarchy optimization content, the chip design module splitting and reorganization method further includes: The physical hierarchy optimization content is uniquely configured.
12. The chip design module splitting and reorganization method according to claim 1, characterized in that: After generating the chip physical hierarchy file, the method further includes: A functional consistency check is performed on the chip physical hierarchy file and the chip logical hierarchy file.
13. A chip design module splitting and reorganization device, characterized in that: include: A file acquisition module is configured to execute acquisition of a chip logic hierarchy file containing logic hierarchy content, wherein the logic hierarchy content includes a plurality of logic modules, each of which is composed of a plurality of integrated circuit units; A flattening module, configured to perform a flattening operation on the logic hierarchy structure content to obtain a flattened structure content, wherein the flattened structure content includes all the integrated circuit units constituting the plurality of logic modules; a reorganization module configured to reorganize the integrated circuit units in the flattened structure content according to a preset physical hierarchy rule to obtain a physical hierarchy content, wherein the physical hierarchy content includes a plurality of tile modules, and each tile module includes at least one integrated circuit unit; a structure optimization module configured to optimize and modify the connection structure of the tile modules according to the positional relationship between the tile modules and the circuit connection relationship between the tile modules in the physical hierarchy content to obtain physical hierarchy content; and The file generation module is configured to generate a chip physical hierarchy file containing the physical hierarchy optimization content.
14. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute the executable instructions to implement the chip design module splitting and reorganization method as described in any one of claims 1 to 12.
15. A computer-readable storage medium, characterized in that: When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device is enabled to implement the chip design module splitting and reorganization method as described in any one of claims 1 to 12.