Modeling method and device of analog circuit, equipment and medium

Abstract

The invention provides a modeling method and device for an analog circuit, equipment and a medium. The modeling method comprises the following steps: generating a clock signal; modeling the clock signal to generate an analog signal waveform with adjustable parameters; and building a hybrid simulation model, and integrating the hybrid simulation model to a verification environment to realize simulation verification of an input analog signal waveform. By modeling a clock signal, rapid simulation verification of a digital-analog hybrid circuit can be realized in the early stage of chip verification, and an analog signal waveform with adjustable parameters is used as input, so that the signal input into a hybrid simulation model is more authentic, and the reliability of hybrid simulation is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a modeling method, device, equipment and medium for analog circuits. Background Art

[0002] SerDes is the abbreviation of SERializer (serializer) / DESerializer (deserializer). In high-speed SerDes digital-to-analog systems, an Adaptation dynamic adjustment circuit is often required between digital circuits and analog circuits to ensure that the digital and analog parts can respond to link signals in different working stages in real time, so as to make further processing. Since the signals of analog circuits are usually nonlinear, any component in the circuit may affect other components, so it is difficult to simulate the digital-to-analog system. Because in the verification process, how to model the behavior of the analog circuit will directly affect the correctness of the simulation results, and the closer the simulation is to the actual circuit behavior, the more accurate the possible problems in the system can be found.

[0003] At present, there are two commonly used methods for simulating such mixed analog and digital circuits. One is to use the hardware description language Verilog or VerilogA to simply simulate the circuit functions, and the other is to use EDA tools to extract component parasitic parameters for simulation in post-simulation. The first method is difficult to achieve high accuracy when modeling some analog circuits. For example, it is impossible to make a reliable model for the behavior of components such as resistors and capacitors, thereby reducing the credibility of mixed simulation. The problem with the second method is that there are many component parasitic parameters, and multiple components affect each other, resulting in too high simulation complexity, making the simulation speed very slow, and not suitable for simulation of larger-scale circuits.

[0004] Therefore, there is an urgent need for a modeling method, device, equipment and medium for analog circuits to improve the above problems. Summary of the invention

[0005] The object of the present invention is to provide a modeling method, device, equipment and medium for analog circuits, which can realize rapid simulation verification of digital-analog mixed circuits and improve the credibility of mixed simulations.

[0006] In a first aspect, the present invention provides a modeling method for an analog circuit, comprising: Generate a clock signal; Modeling the clock signal to generate an analog signal waveform with adjustable parameters; Build a hybrid model and integrate it into the verification environment to simulate and verify the input analog signal waveform.

[0007] The method of the present invention has the following beneficial effects: by generating a clock signal; modeling the clock signal to generate a parameter-adjustable analog signal waveform; building a hybrid simulation model and integrating it into a verification environment to achieve simulation verification of the input analog signal waveform. By modeling the clock signal, rapid simulation verification of the digital-analog hybrid circuit can be achieved in the early stage of chip verification, and the parameter-adjustable analog signal waveform is used as input to make the signal input to the hybrid simulation model more realistic, thereby improving the credibility of the hybrid simulation.

[0008] Optionally, modeling the clock signal includes: The clock signal is modeled through Interface.

[0009] Optionally, build a hybrid model including: Use the power supply, resistance and capacitance models modeled by EEnet to build the Adaptation hybrid model.

[0010] Optionally, generating a simulated signal waveform with adjustable parameters includes: The first step length of the analog signal is obtained according to the rise time and the amplitude, and the second step length of the analog signal is obtained according to the fall time and the amplitude; The third step length is calculated according to the rising slope, and the fourth step length is calculated according to the falling slope; The number of iterations is calculated according to the rise time and the set time precision, and the output analog signal is accumulated from zero at the rising edge of the input clock signal, with the step length being the first step length. After the iteration is completed, the output analog signal is accumulated to a maximum value according to the third step length; At the falling edge of the input clock signal, the output analog signal is cumulatively reduced from the maximum value according to the second step length. After the iteration is completed, the output analog signal is cumulatively reduced to zero according to the fourth step length, and finally an analog signal waveform with adjustable parameters is generated.

[0011] Optionally, the parameters include rise time, fall time, rise slope and fall slope.

[0012] Optionally, simulation verification of the input analog signal waveform includes: The hybrid model removes the interference of high-frequency components from the input model signal waveform through the gain value fed back in real time, and retains the low-frequency signal to achieve simulation verification.

[0013] Optionally, generating a clock signal includes: Generates a single-bit standard clock signal of a set frequency.

[0014] In a second aspect, the present invention provides a modeling device for analog circuits, the device comprising modules / units for executing any possible design method of the first aspect. These modules / units can be implemented by hardware, or by executing corresponding software implementations by hardware.

[0015] In a third aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the program is executed by the processor, the electronic device implements a method for executing any possible design of any of the above aspects.

[0016] In a fourth aspect, the present invention provides a readable storage medium, wherein the readable storage medium stores a program, and when the program is executed, it implements any possible design method of any of the above aspects.

[0017] For the beneficial effects of the second to fourth aspects, reference may be made to the description of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a flow chart of a modeling method for an analog circuit provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of a modeling device for an analog circuit provided by an embodiment of the present invention; Figure 3 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention; Figure 4 A schematic diagram of a signal generated by an Interface provided in an embodiment of the present invention; Figure 5 A schematic diagram of an Adaptation input signal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0020] In view of the inconvenience of current simulation verification of mixed analog circuits, the modeling method of analog circuits provided by the present invention can realize rapid simulation verification of mixed analog circuits and improve the credibility of mixed simulation. The technical scheme in the embodiment of the present invention is described below in conjunction with the drawings in the embodiment of the present invention. Among them, in the description of the embodiment of the present invention, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present invention. The singular expressions "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present invention, "at least one", "one or more" refer to one or more than two (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0021] References to "one embodiment" or "some embodiments" described in this specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", and "in some other embodiments" that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connected" includes direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0022] In the embodiments of the present invention, "exemplarily" or "for example" is used to indicate an example, illustration or description. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of "exemplarily" or "for example" is intended to present the relevant concepts in a specific way.

[0023] like Figure 1 As shown, the present invention provides a modeling method for an analog circuit, comprising: S101, generate a clock signal.

[0024] In some embodiments, generating a clock signal includes: generating a single-bit standard clock signal of a set frequency. Exemplarily, generating a single-bit standard clock signal of a certain frequency, such as Figure 4 Signal D is shown.

[0025] S102, modeling the clock signal to generate an analog signal waveform with adjustable parameters.

[0026] In some embodiments, modeling the clock signal includes: modeling the clock signal through an interface.

[0027] In some embodiments, the parameters include rise time, fall time, rise slope, and fall slope.

[0028] Exemplarily, the clock signal is modeled through an interface to output a flexible and configurable analog signal waveform with a rise time, a fall time, and a slope control.

[0029] In some embodiments, generating an analog signal waveform with adjustable parameters includes: obtaining the first step length of the analog signal based on the rise time and amplitude, and obtaining the second step length of the analog signal based on the fall time and amplitude; calculating the third step length based on the rising slope, and calculating the fourth step length based on the falling slope; calculating the number of iterations based on the rise time and the set time accuracy, and accumulating the output analog signal from zero at the rising edge of the input clock signal, with the step length being the first step length. After the iteration is completed, accumulating the output analog signal to a maximum value according to the third step length; and decreasing the output analog signal from the maximum value according to the second step length at the falling edge of the input clock signal. After the iteration is completed, decreasing the output analog signal to zero according to the fourth step length, and finally generating an analog signal waveform with adjustable parameters.

[0030] S103, building a hybrid simulation model and integrating it into a verification environment to implement simulation verification of the input analog signal waveform.

[0031] In some embodiments, building a hybrid model includes: using the power supply, resistance and capacitance models modeled by EEnet to build an Adaptation hybrid model, thereby achieving rapid simulation verification of mixed analog and digital circuits in the early stages of chip verification.

[0032] In some embodiments, simulation verification of the input analog signal waveform includes: the hybrid model uses the real-time feedback gain value to strip off the interference of high-frequency components from the input model signal waveform and retain the low-frequency signal to achieve simulation verification, thereby enabling rapid simulation verification of the digital-analog hybrid circuit in the early stages of chip verification, and using the parameter-adjustable analog signal waveform as input to make the signal input to the hybrid model more realistic, thereby improving the credibility of the hybrid simulation.

[0033] For ease of understanding, this embodiment further describes the specific implementation process of the above method in combination with a specific application scenario system. Figure 4-5 As shown, Figure 4 Taking the signal D shown in the figure as an example, the specific steps include: Step a, first generate a single-bit standard clock signal with a certain frequency (the specific frequency can be adjusted according to actual needs), such as Figure 4 Signal D is shown.

[0034] Step b: Model the generated clock signal through the interface, and output a flexible and configurable analog signal waveform with rise and fall time and slope control. The interface port is as follows: interface trans2_if#(CKP=0.001)(input intT_RISE,input int T_FALL,input real v,input real slope0,input real slopel, input bit sin,output realsout); Among them, CKP is the time accuracy, T_RISE is the rise time, T_FALL is the fall time, v is the maximum signal amplitude, slope0 is the rise slope, slope1 is the fall slope, sin is the input reference clock signal, and sout is the output analog signal. The specific implementation process is as follows: (1) obtaining the first step length step1 of the analog signal according to the rise time and amplitude, and obtaining the second step length step2 of the analog signal according to the fall time and amplitude; (2) Calculate the third step length step3 according to the rising slope, and calculate the fourth step length step4 according to the falling slope; (3) The number of iterations is calculated according to the rise time and the set time accuracy. When the input clock signal sin rises, the output analog signal sout is accumulated from 0, with the step length being the first step length step1. After the iteration is completed, the output analog signal sout is accumulated to the maximum value according to the third step length step3; (4) When the input clock signal sin falls, the signal sout starts to decrease from the maximum value according to the second step length step2. After the iteration, the output signal sout is decreased to 0 according to the fourth step length step4. The final analog signal generated is as follows Figure 4 Signal D_ANA in; Step c: According to the circuit diagram of the Adaptation simulation part, and using the power supply, resistor and capacitor models modeled by EEnet, build the Adaptation hybrid model. Input the analog signal after the above Interface model into the circuit, and the gain value can be fed back in real time by the digital module. Figure 5 The input clock signal shown in the figure removes the influence of high-frequency components and retains the low-frequency signal, thereby realizing the simulation verification of the Adaptation function.

[0035] The beneficial effect of the embodiment of the present invention is that a digital model is established for the Adaptation digital-analog mixed circuit based on the EEnet model, thereby realizing rapid simulation verification of the digital-analog mixed circuit in the early stage of chip verification. Moreover, the Interface model proposed in the present invention supports flexible adjustment of the slope, rise time and fall time of the input signal, and can accurately simulate the signal of the analog circuit, so that the input signal in the mixed simulation is more realistic. The modeling method proposed in the present invention effectively improves the reliability of the Adaptation digital-analog mixed circuit simulation, and provides key support for the debugging of the digital-analog system at a low cost. This method can also be used as a reference in the process of digital modeling of other more complex analog circuits.

[0036] like Figure 2As shown, based on the above-mentioned modeling method of an analog circuit, the present invention provides a modeling device for an analog circuit, including: a generating unit 201, used to generate a clock signal; a processing unit 202, used to model the clock signal and generate an analog signal waveform with adjustable parameters; an integration unit 203, used to build a hybrid model and integrate it into a verification environment to realize simulation verification of the input analog signal waveform. Exemplarily, the generating unit 201 is used to generate a single-bit standard clock signal of a set frequency; the processing unit 202 is used to model the clock signal through an interface, obtain the first step length of the analog signal according to the rise time and amplitude, and obtain the second step length of the analog signal according to the fall time and amplitude; calculate the third step length according to the rise slope, and calculate the fourth step length according to the fall slope; calculate the number of iterations according to the rise time and the set time accuracy, and at the rising edge of the input clock signal, the output analog signal starts to accumulate from zero, and the step length is the first step length. After the iteration ends, the output analog signal is accumulated to the maximum value according to the third step length; at the falling edge of the input clock signal, the output analog signal is accumulated from the maximum value according to the second step length, and the iteration ends. Afterwards, the output analog signal is accumulated to zero according to the fourth step length, and finally an analog signal waveform with adjustable parameters is generated, wherein the parameters include rise time, fall time, rise slope and fall slope; the integrated unit 203 is used to build an Adaptation hybrid model using the power supply, resistance and capacitance models modeled by EEnet, and integrate it into the verification environment, so that the hybrid model can remove the interference of high-frequency components from the input model signal waveform through the real-time feedback gain value, and retain the low-frequency signal to achieve simulation verification, so that rapid simulation verification of the digital-analog hybrid circuit can be achieved in the early stage of chip verification, and the analog signal waveform with adjustable parameters is used as input to make the signal input to the hybrid model more realistic, thereby improving the credibility of the hybrid simulation.

[0037] It should be understood that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here. In addition, the use of suffixes such as "module", "component" or "unit" used to represent elements is only for the purpose of facilitating the description of the present invention, and has no specific meaning in itself. Therefore, "module", "component" or "unit" can be used in a mixed manner. The terminal can be implemented in various forms. For example, the terminal described in the present invention may include mobile terminals such as mobile phones, tablet computers, laptops, PDAs, portable media players (PMP), navigation devices, wearable devices, smart bracelets, pedometers, and fixed terminals such as digital TVs and desktop computers. The subsequent description will be described by taking the mobile terminal as an example, and those skilled in the art will understand that, in addition to components specifically used for mobile purposes, the construction according to the embodiment of the present invention can also be applied to fixed types of terminals.

[0038] In some other embodiments of the present invention, an electronic device 300 is disclosed. Figure 3 As shown, it may include: one or more processors 301; memory 302; display 303; one or more applications (not shown); and one or more computer programs 304. The above-mentioned components may be connected via one or more communication buses 305. The one or more computer programs 304 are stored in the above-mentioned memory 302 and configured to be executed by the one or more processors 301. The one or more computer programs 304 include instructions, which may be used to execute the following instructions: Figure 1 The various steps in the corresponding embodiments.

[0039] The processor 301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0040] The memory 302 may be an internal storage unit of the electronic device 300, such as a hard disk or memory of the electronic device 300. The memory 302 may also be an external storage device of the electronic device 300, such as a plug-in hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash card (FlashCard), etc. equipped on the electronic device 300. Further, the memory 302 may also include both an internal storage unit of the electronic device 300 and an external storage device. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 may also be used to temporarily store data that has been output or is to be output.

[0041] The computer program 304 may be divided into one or more modules / units. The one or more modules / units may be a series of computer program instruction segments capable of performing specific functions. The instruction segments are used to describe the execution process of the computer program 304 in the electronic device 300 .

[0042] In addition to the above structure, those skilled in the art can understand that Figure 3 It is only an example of the electronic device 300 and does not constitute a limitation of the electronic device 300. The electronic device 300 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0043] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0044] Based on the above embodiments, the present invention further discloses a computer-readable storage medium having at least one computer program stored thereon, and when the computer program is executed by a processor, the modeling method of the analog circuit in the above embodiments is implemented.

[0045] A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disk, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state disk (SSD)), etc.

[0046] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0047] In summary, the modeling method, device, equipment and medium of analog circuits disclosed in the present invention can achieve rapid simulation verification of digital-analog mixed circuits in the early stage of chip verification by modeling clock signals, and use parameter-adjustable analog signal waveforms as input to make the signal input into the mixed-simulation model more realistic, thereby improving the credibility of the mixed simulation.

[0048] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A modeling method for an analog circuit, characterized in that: include: Generate a clock signal; Modeling the clock signal to generate an analog signal waveform with adjustable parameters; Build a hybrid model and integrate it into the verification environment to simulate and verify the input analog signal waveform.

2. The method according to claim 1, characterized in that Modeling the clock signal includes: The clock signal is modeled through Interface.

3. The method according to claim 1, characterized in that Building a hybrid model includes: Use the power supply, resistance and capacitance models modeled by EEnet to build the Adaptation hybrid model.

4. The method according to claim 1, characterized in that: Generate analog signal waveforms with adjustable parameters including: The first step length of the analog signal is obtained according to the rise time and the amplitude, and the second step length of the analog signal is obtained according to the fall time and the amplitude; The third step length is calculated according to the rising slope, and the fourth step length is calculated according to the falling slope; The number of iterations is calculated according to the rise time and the set time precision, and the output analog signal is accumulated from zero at the rising edge of the input clock signal, with the step length being the first step length. After the iteration is completed, the output analog signal is accumulated to a maximum value according to the third step length; At the falling edge of the input clock signal, the output analog signal is cumulatively reduced from the maximum value according to the second step length. After the iteration is completed, the output analog signal is cumulatively reduced to zero according to the fourth step length, and finally an analog signal waveform with adjustable parameters is generated.

5. The method according to claim 1, characterized in that The parameters include rise time, fall time, rise slope and fall slope.

6. The method according to claim 1, characterized in that The simulation verification of the input analog signal waveform includes: The hybrid model removes the interference of high-frequency components from the input model signal waveform through the gain value fed back in real time, and retains the low-frequency signal to achieve simulation verification.

7. The method according to claim 1, characterized in that Generating a clock signal includes: Generates a single-bit standard clock signal of a set frequency.

8. A modeling device for analog circuits, used in the method according to any one of claims 1 to 7, characterized in that: include: A generating unit, used for generating a clock signal; A processing unit, used for modeling the clock signal and generating an analog signal waveform with adjustable parameters; The integrated unit is used to build a hybrid model and integrate it into the verification environment to simulate and verify the input analog signal waveform.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores a program executable on the processor, and when the program is executed by the processor, the electronic device implements the method according to any one of claims 1 to 7.

10. A readable storage medium, wherein a program is stored in the readable storage medium, characterized in that: When the program is executed, the method according to any one of claims 1 to 7 is implemented.

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