Sensing driver, method of driving sensing driver, and display device

Abstract

The invention relates to a sensing driver, a method of driving the sensing driver, and a display device. The sensing driver includes: a sensing channel sampling a first sensing voltage of a first sensing line in a first sampling period, the sensing channel sampling a second sensing voltage of a second sensing line in a second sampling period, and the sensing channel including a sampling capacitor; a first line selection switch connecting the first sensing line to the sensing channel in a first sub-sensing period; and a second line selection switch connecting the second sensing line to the sensing channel in a second sub-sensing period. In a first capacitor initialization period, a voltage having a first initialization level is applied to a first electrode of the sampling capacitor, and in a second capacitor initialization period, a voltage having a second initialization level different from the first initialization level is applied to the first electrode of the sampling capacitor.

Description

Technical Field

[0001] Embodiments relate to a sensing driver, a method of driving the sensing driver, and a display device. More particularly, embodiments relate to a sensing driver that performs a sensing operation on a sensing line, a method of driving the sensing driver, and a display device including the sensing driver. Background Art

[0002] The display device may include a plurality of pixels, and each of the plurality of pixels may include a driving transistor that generates a driving current and a light emitting element that emits light based on the driving current.

[0003] Although the pixels are manufactured by the same process, the driving transistors may have different driving characteristics (e.g., threshold voltages), and therefore, the pixels may emit light with different brightness. In addition, as the driving time of the display device accumulates, the pixels may degrade, and the driving characteristics of the driving transistors may degrade.

[0004] To compensate for the brightness non-uniformity and degradation of pixels, the display device may include a sensing driver that performs a sensing operation to sense the driving characteristics of a driving transistor of the pixel. To reduce the size of the sensing driver, the sensing driver may perform a sensing operation on two or more sensing lines using one sensing channel. Summary of the invention

[0005] The embodiment provides a sensing driver for improving sensing accuracy.

[0006] The embodiment provides a method of driving a sensing driver to improve sensing accuracy.

[0007] The embodiment provides a display device including a sensing driver for improving sensing accuracy.

[0008] According to an embodiment, a sensing driver that performs a sensing operation on a first sensing line and a second sensing line in a sensing period including a first sub-sensing period and a second sub-sensing period may include: a sensing channel that samples a first sensing voltage of the first sensing line in a first sampling period of the first sub-sensing period, the sensing channel that samples a second sensing voltage of the second sensing line in a second sampling period of the second sub-sensing period, and the sensing channel includes a sampling capacitor having a first electrode and a second electrode; a first line selection switch that connects the first sensing line to the sensing channel in the first sub-sensing period; and a second line selection switch that connects the second sensing line to the sensing channel in the second sub-sensing period. In a first capacitor initialization period of the first sub-sensing period, a voltage having a first initialization level may be applied to the first electrode of the sampling capacitor. In a second capacitor initialization period of the second sub-sensing period, a voltage having a second initialization level different from the first initialization level may be applied to the first electrode of the sampling capacitor.

[0009] In an embodiment, the second initialization level may be higher than the first initialization level.

[0010] In an embodiment, before the sensing period, the second initialization level may be preset.

[0011] In an embodiment, the second initialization level may be set based on the first sensing voltage and the second sensing voltage.

[0012] In an embodiment, the sensing channel may further include: a first sampling switch, connecting the first line selection switch and the second line selection switch to the first electrode of the sampling capacitor in response to a sampling signal; a first reference switch, applying a reference voltage to the second electrode of the sampling capacitor in response to a reference signal; a first initialization voltage switch, applying an initialization voltage to a first intermediate node in response to a first capacitor initialization signal; and a first capacitor initialization switch, connecting the first intermediate node to the first electrode of the sampling capacitor in response to the reference signal.

[0013] In an embodiment, the sensing driver may further include: a reference channel. The reference channel may include: a reference capacitor having a first electrode and a second electrode; a second sampling switch applying the initialization voltage to the first electrode of the reference capacitor in response to the sampling signal; a second reference switch applying the reference voltage to the second electrode of the reference capacitor in response to the reference signal; a second initialization voltage switch applying the initialization voltage to a second intermediate node in response to the first capacitor initialization signal; and a second capacitor initialization switch connecting the second intermediate node to the first electrode of the reference capacitor in response to the reference signal.

[0014] In an embodiment, the initialization voltage may have a first voltage level in the first capacitor initialization period, and may have a second voltage level different from the first voltage level in the second capacitor initialization period.

[0015] In an embodiment, the sensing channel may further include a first reference voltage switch, the first reference voltage switch applying the reference voltage to the first intermediate node in response to a second capacitor initialization signal. The reference channel may further include a second reference voltage switch, the second reference voltage switch applying the reference voltage to the second intermediate node in response to the second capacitor initialization signal.

[0016] In an embodiment, the reference voltage may have a third voltage level in the first capacitor initialization period, and may have a fourth voltage level different from the third voltage level in the second capacitor initialization period.

[0017] In an embodiment, the sensing channel may further include a first external voltage switch, the first external voltage switch applying an external voltage to the first intermediate node in response to a third capacitor initialization signal. The reference channel may further include a second external voltage switch, the second external voltage switch applying the external voltage to the second intermediate node in response to the third capacitor initialization signal.

[0018] In an embodiment, the external voltage may have a fifth voltage level in the first capacitor initialization period, and may have a sixth voltage level different from the fifth voltage level in the second capacitor initialization period.

[0019] In an embodiment, the sensing driver may further include a sensing line initialization circuit that simultaneously initializes the first sensing line and the second sensing line in the first sub-sensing period.

[0020] In an embodiment, the sensing driver may further include: an analog-to-digital converter; and a switch matrix connecting the sensing channels to the analog-to-digital converter.

[0021] In an embodiment, the sensing period may include: the first sub-sensing period, in which a first sensing operation is performed on the first sensing line; the second sub-sensing period, in which a second sensing operation is performed on the second sensing line; and a data output period, in which a first sensing data corresponding to the first sensing voltage and a second sensing data corresponding to the second sensing voltage are output. The first sub-sensing period may include: a sensing line initialization period, in which the first sensing line and the second sensing line are initialized at the same time; the first capacitor initialization period, in which the sampling capacitor is initialized; the first sampling period, in which the first sensing voltage is sampled; and a first analog-to-digital conversion period, in which the first analog-to-digital conversion period, the first sensing voltage is converted into the first sensing data. The second sub-sensing period may include: the second capacitor initialization period, in which the sampling capacitor is initialized; the second sampling period, in which the second sensing voltage is sampled; and a second analog-to-digital conversion period, in which the second sensing voltage is converted into the second sensing data.

[0022] In an embodiment, the sensing driver may perform a sensing operation on N odd sensing lines including the first sensing line and N even sensing lines including the second sensing line in the sensing period, wherein N is a natural number greater than or equal to 2. The sensing driver may include: N sensing channels including the sensing channel; N first line selection switches including the first line selection switch, the N first line selection switches connecting the N odd sensing lines to the N sensing channels in the first sub-sensing period; N second line selection switches including the second line selection switch, the N second line selection switches connecting the N even sensing lines to the N sensing channels in the second sub-sensing period; an analog-to-digital converter; and a switch matrix sequentially connecting the N sensing channels to the analog-to-digital converter in a first analog-to-digital conversion period of the first sub-sensing period, and the switch matrix sequentially connecting the N sensing channels to the analog-to-digital converter in a second analog-to-digital conversion period of the second sub-sensing period. The analog-to-digital converter may sequentially convert the N first sensing voltages of the N odd sensing lines into N first sensing data in the first analog-to-digital conversion period, and may sequentially convert the N second sensing voltages of the N even sensing lines into N second sensing data in the second analog-to-digital conversion period.

[0023] In an embodiment, the second initialization level may be set to an average value of the N first sensing voltages and the N second sensing voltages.

[0024] In an embodiment, the sensing driver may further include a data output unit that sequentially stores the N first sensing data in the first analog-to-digital conversion period, the data output unit sequentially stores the N second sensing data in the second analog-to-digital conversion period, and the data output unit outputs the N first sensing data and the N second sensing data in a data output period of the sensing period.

[0025] In an embodiment, the data output unit may rearrange the N first sensing data and the N second sensing data such that each of the N second sensing data is disposed between two adjacent first sensing data of the N first sensing data.

[0026] According to an embodiment, a method for driving a sensing driver that performs a sensing operation on a first sensing line and a second sensing line in a sensing period including a first sub-sensing period and a second sub-sensing period may include: in the first sub-sensing period, connecting the first sensing line to a sensing channel; in a first capacitor initialization period of the first sub-sensing period, applying a voltage having a first initialization level to a first electrode of a sampling capacitor of the sensing channel; in a first sampling period of the first sub-sensing period, sampling a first sensing voltage of the first sensing line; in a second capacitor initialization period of the second sub-sensing period, applying a voltage having a second initialization level different from the first initialization level to the first electrode of the sampling capacitor; in the second sub-sensing period, connecting the second sensing line to the sensing channel; and in a second sampling period of the second sub-sensing period, sampling a second sensing voltage of the second sensing line.

[0027] In an embodiment, the second initialization level may be higher than the first initialization level.

[0028] In an embodiment, before the sensing period, the second initialization level may be preset.

[0029] In an embodiment, the second initialization level may be set based on the first sensing voltage and the second sensing voltage.

[0030] According to an embodiment, a display device may include: a display panel including a first pixel and a second pixel; a scan driver providing a scan signal and a sensing signal to each of the first pixel and the second pixel; a data driver providing a data signal to each of the first pixel and the second pixel; and a sensing driver performing a sensing operation on a first sensing line connected to the first pixel and a second sensing line connected to the second pixel in a sensing period including a first sub-sensing period and a second sub-sensing period. The sensing driver may include: a sensing channel sampling a first sensing voltage of the first sensing line in a first sampling period of the first sub-sensing period, the sensing channel sampling a second sensing voltage of the second sensing line in a second sampling period of the second sub-sensing period, and the sensing channel including a sampling capacitor; a first line selection switch connecting the first sensing line to the sensing channel in the first sub-sensing period; and a second line selection switch connecting the second sensing line to the sensing channel in the second sub-sensing period. In a first capacitor initialization period of the first sub-sensing period, a voltage having a first initialization level may be applied to a first electrode of the sampling capacitor. In a second capacitor initialization period of the second sub-sensing period, a voltage having a second initialization level different from the first initialization level may be applied to the first electrode of the sampling capacitor.

[0031] In the sensing driver, the method of driving the sensing driver, and the display device according to the embodiment, the second initialization level of the voltage of the sampling capacitor initialized in the second sub-sensing period may be different from the first initialization level of the voltage of the sampling capacitor initialized in the first sub-sensing period, so that the deviation between the first sensing data and the second sensing data can be reduced. Therefore, the sensing accuracy of the sensing driver can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0034] Figure 2 is a circuit diagram showing a pixel according to an embodiment of the present disclosure.

[0035] Figure 3 is a block diagram illustrating a sensing driver according to an embodiment of the present disclosure.

[0036] Figure 4 is a diagram for describing charge sharing between the second line capacitor and the sampling capacitor.

[0037] Figure 5 is a timing diagram for describing the operation of the sensing driver according to an embodiment of the present disclosure.

[0038] Figure 6 is a diagram for describing an operation of a sensing driver in a sensing line initialization period.

[0039] Figure 7 is a diagram for describing an operation of a sensing driver in a first capacitor initialization period.

[0040] Figure 8 is a diagram for describing an operation of the sensing driver in a first sampling period.

[0041] Fig. 9 is a diagram for describing an operation of a sensing driver in a first analog-to-digital conversion period.

[0042] Fig.10 is a diagram for describing an operation of the sensing driver in a second capacitor initialization period.

[0043] Fig.11 is a diagram for describing the operation of the sensing driver in the second sampling period.

[0044] Fig.12 is a diagram for describing an operation of the sensing driver in the second analog-to-digital conversion period.

[0045] Fig.13 is a diagram for describing rearrangement of first sensing data and second sensing data.

[0046] Fig.14 is a diagram illustrating images displayed by a display device according to a comparative example and an embodiment of the present disclosure.

[0047] Fig.15 is a block diagram illustrating a sensing driver according to an embodiment of the present disclosure.

[0048] Fig.16 is a timing diagram for describing the operation of the sensing driver according to an embodiment of the present disclosure.

[0049] Fig.17 is a diagram for describing an operation of the sensing driver in a second capacitor initialization period.

[0050] Fig.18 is a timing diagram for describing the operation of the sensing driver according to an embodiment of the present disclosure.

[0051] Fig.19 is a diagram for describing an operation of the sensing driver in a second capacitor initialization period.

[0052] Fig. 20 is a timing diagram for describing the operation of the sensing driver according to an embodiment of the present disclosure.

[0053] Fig.21 is a diagram for describing an operation of the sensing driver in a second capacitor initialization period.

[0054] Fig. 22 is a flowchart illustrating a method of driving a sensing driver according to an embodiment of the present disclosure.

[0055] Fig.23 is a flowchart illustrating a method of driving a sensing driver according to an embodiment of the present disclosure.

[0056] Fig.24 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] Hereinafter, a sensing driver, a method of driving the sensing driver, and a display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals will be used for the same elements.

[0058] Figure 1 is a block diagram showing a display device 100 according to an embodiment of the present disclosure.

[0059] refer to Figure 1 , the display device 100 may include: a display panel 110, including a plurality of pixels PX1 and PX2; a scan driver 120, providing a scan signal SC and a sensing signal SS to each of the plurality of pixels PX1 and PX2; a data driver 130, providing a data signal DS to each of the plurality of pixels PX1 and PX2; a sensing driver 140, connected to the plurality of pixels PX1 and PX2 through a plurality of sensing lines SL1 and SL2; and a controller 150, controlling the scan driver 120, the data driver 130, and the sensing driver 140.

[0060] The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of sensing signal lines, a plurality of sensing lines SL1 and SL2, and a plurality of pixels PX1 and PX2 connected to the plurality of data lines, the plurality of scan lines, the plurality of sensing signal lines, and the plurality of sensing lines SL1 and SL2. In an embodiment, each of the plurality of pixels PX1 and PX2 may include a light emitting element, and the display panel 110 may be a light emitting display panel. For example, the light emitting element may be an organic light emitting diode (OLED), and the display panel 110 may be an OLED display panel. For example, the light emitting element may be a nano-light emitting diode (nano-LED), a quantum dot (QD) light emitting diode, a micro light emitting diode, or an inorganic light emitting diode.

[0061] Figure 2 is a circuit diagram showing a pixel PX according to an embodiment of the present disclosure. Figure 2 The pixel PX may correspond to a pixel included in Figure 1 One of the multiple pixels PX1 and PX2 in the display device 100.

[0062] refer to Figure 2 , also refer to Figure 1 , the pixel PX may include: a first switching transistor TSW1, transmitting a data signal DS (or a sensing reference voltage VSENREF) of a data line DL to a storage capacitor CST in response to a scan signal SC; a storage capacitor CST, storing the data signal DS transmitted by the first switching transistor TSW1; a driving transistor TDR, generating a driving current based on the data signal DS stored in the storage capacitor CST; a light emitting element EL, emitting light based on a driving current flowing from a first power voltage ELVDD to a second power voltage ELVSS; and a second switching transistor TSW2, connecting a terminal (e.g., a source) of the driving transistor TDR to a sensing line SL in response to a sensing signal SS. The sensing line SL may have a line capacitor CL (e.g., a first line capacitor CL1 (see Figure 6 or Figure 7 ) and the second line capacitor CL2 (see Figure 6 or Figure 7 )).

[0063] In the sensing period, the scan driver 120 may provide a scan signal SC and a sense signal SS to each pixel PX in the selected pixel row, and the data driver 130 may provide a sense reference voltage VSENREF to each pixel PX in the selected pixel row. The first switch transistor TSW1 may transmit the sense reference voltage VSENREF to the gate of the drive transistor TDR in response to the scan signal SC. When the sense reference voltage VSENREF is applied to the gate of the drive transistor TDR, the voltage of the terminal (e.g., source) of the drive transistor TDR may be saturated to a voltage VSENREF-VTH obtained by subtracting a threshold voltage VTH of the drive transistor TDR from the sense reference voltage VSENREF. The second switch transistor TSW2 may transmit the voltage VSENREF-VTH of the terminal of the drive transistor TDR to the sense line SL in response to the sense signal SS, and the sense driver 140 may sense the voltage VSENREF-VTH as the sense voltage VSEN of the sense line SL.

[0064] Reference again Figure 1, the scan driver 120 may generate a scan signal SC and a sensing signal SS based on a scan control signal SCTRL received from the controller 150, and may sequentially provide the scan signal SC and the sensing signal SS to a plurality of pixels PX1 and PX2 on a row-by-row basis. In an embodiment, the scan control signal SCTRL may include a scan start signal and a scan clock signal, but is not limited thereto. In an embodiment, the scan driver 120 may be integrated or formed in / on a peripheral portion of the display panel 110. In an embodiment, the scan driver 120 may be implemented with one or more integrated circuits.

[0065] The data driver 130 may generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 150, and may provide the data signal DS to a plurality of pixels PX1 and PX2. In an embodiment, the data driver 130 may provide a sensing reference voltage VSENREF to a plurality of pixels PX1 and PX2 in a selected pixel row during a sensing period. In an embodiment, the data control signal DCTRL may include a horizontal start signal, an output data enable signal, and a load signal, but is not limited thereto. In an embodiment, the data driver 130 may be implemented with one or more integrated circuits. In an embodiment, the data driver 130 and the controller 150 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED).

[0066] The sensing driver 140 may sense characteristics (e.g., threshold voltage VTH and / or mobility of the driving transistor TDR) of a plurality of pixels PX1 and PX2 in a pixel row selected by a plurality of sensing lines SL1 and SL2. The sensing driver 140 may provide sensing data SD generated by sensing the plurality of pixels PX1 and PX2 to the controller 150. In an embodiment, the sensing driver 140 may be implemented as an integrated circuit separate from that of the data driver 130. In an embodiment, the data driver 130 and the sensing driver 140 may be implemented as a single integrated circuit.

[0067] The controller 150 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In an embodiment, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal, but is not limited thereto. The controller 150 may compensate the input image data IDAT based on the sensing data SD, and may generate output image data ODAT. The controller 150 may generate a data control signal DCTRL and a scan control signal SCTRL based on the control signal CTRL. The controller 150 may control the operation of the scan driver 120 by providing the scan control signal SCTRL to the scan driver 120, and may control the operation of the data driver 130 by providing the output image data ODAT and the data control signal DCTRL to the data driver 130.

[0068] The sensing driver 140 may perform a sensing operation on a plurality of sensing lines SL1 and SL2 connected to a plurality of pixels PX1 and PX2 in a selected pixel row in each sensing period. In an embodiment, the sensing driver 140 may perform a sensing operation when the display device 100 is powered off. For example, when the display device 100 is powered off, the sensing driver 140 may sequentially perform a sensing operation on a plurality of sensing lines connected to a plurality of pixel rows of the display panel 110 in a plurality of sensing periods. In an embodiment, the sensing driver 140 may perform a sensing operation while driving the display device 100. For example, when driving the display device 100, the sensing driver 140 may perform a sensing operation on a sensing line connected to at least one pixel row in at least one sensing period within a vertical blanking period.

[0069] The sensing driver 140 may perform a sensing operation on two or more sensing lines (e.g., sensing lines SL1 and SL2) in a time-division manner using one sensing channel. For example, each sensing period may include a first sub-sensing period and a second sub-sensing period, and the sensing driver 140 may perform a sensing operation on the first sensing line SL1 using one sensing channel in the first sub-sensing period, and may perform a sensing operation on the second sensing line SL2 using the one sensing channel in the second sub-sensing period. Therefore, the size of the sensing driver 140 may be reduced compared to a sensing driver including one sensing channel for each sensing line.

[0070] Figure 3 is a block diagram illustrating a sensing driver 300 according to an embodiment of the present disclosure. Figure 3 The sensing driver 300 may correspond to the one included in Figure 1 The sensing driver 140 in the display device 100.

[0071] refer to Figure 3 , the sensing driver 300 may perform a sensing operation on 2N sensing lines SL1, SL2, ..., SL2N-1, SL2N, where N is a natural number of 2 or more. The sensing driver 300 may include N first line selection switches LSSW1-1, ..., LSSW1-N, N second line selection switches LSSW2-1, ..., LSSW2-N, a sensing line initialization circuit 320, N sensing channels 340-1, ..., 340-N, N reference channels 350-1, ..., 350-N, a switch matrix 360, an analog-to-digital converter (ADC) 380, and a data output unit 390.

[0072] The first line selection switches LSSW1-1, ..., LSSW1-N may connect the N odd-numbered sensing lines SL1, ..., SL2N-1 to the sensing channels 340-1, ..., 340-N, respectively, in the first sub-sensing period of the sensing period. For example, in at least a portion of the first sub-sensing period, the first line selection signal LSS1 may have an activation level, and the first line selection switches LSSW1-1, ..., LSSW1-N may connect the odd-numbered sensing lines SL1, ..., SL2N-1 to the sensing channels 340-1, ..., 340-N, respectively, in response to the first line selection signal LSS1 having the activation level.

[0073] The second line selection switches LSSW2-1, ..., LSSW2-N may connect the N even-numbered sensing lines SL2, ..., SL2N to the sensing channels 340-1, ..., 340-N, respectively, in the second sub-sensing period of the sensing period. For example, in at least a portion of the second sub-sensing period, the second line selection signal LSS2 may have an activation level, and the second line selection switches LSSW2-1, ..., LSSW2-N may connect the even-numbered sensing lines SL2, ..., SL2N to the sensing channels 340-1, ..., 340-N, respectively, in response to the second line selection signal LSS2 having the activation level.

[0074] The sensing line initialization circuit 320 may initialize the sensing lines SL1, SL2, ..., SL2N-1, SL2N. In an embodiment, the sensing line initialization circuit 320 may include 2N sensing line initialization switches SLISW1, SLISW2, ..., SLISW2N-1, SLISW2N to initialize the sensing lines SL1, SL2, ..., SL2N-1, SL2N. For example, the first sensing line initialization switch SLISW1 may apply an initialization voltage VINT to the first sensing line SL1 in response to the sensing line initialization signal SLIS, the second sensing line initialization switch SLISW2 may apply an initialization voltage VINT to the second sensing line SL2 in response to the sensing line initialization signal SLIS, the 2N-1 sensing line initialization switch SLISW2N-1 may apply an initialization voltage VINT to the 2N-1 sensing line SL2N-1 in response to the sensing line initialization signal SLIS, and the 2N sensing line initialization switch SLISW2N may apply an initialization voltage VINT to the 2N sensing line SL2N in response to the sensing line initialization signal SLIS. Therefore, the sensing lines SL1 , SL2 , . . . , SL2N- 1 , SL2N may be initialized based on the initialization voltage VINT.

[0075] The sensing channels 340-1, ..., 340-N can sample the N first sensing voltages of the odd sensing lines SL1, ..., SL2N-1 in the first sampling period of the first sub-sensing period, and can sample the N second sensing voltages of the even sensing lines SL2, ..., SL2N in the second sampling period of the second sub-sensing period. In an embodiment, each of the sensing channels 340-1, ..., 340-N may include a sampling capacitor SAMC, a first sampling switch SAMSW1, a first reference switch RSW1, a first initialization voltage switch IVSW1, and a first capacitor initialization switch CISW1. For example, the sampling capacitor SAMC may have a first electrode and a second electrode. The first sampling switch SAMSW1 may connect the corresponding first line selection switch LSSW1-1 and the second line selection switch LSSW2-1 to the first electrode of the sampling capacitor SAMC in response to the sampling signal SAMS. The first reference switch RSW1 may apply a reference voltage VREF to the second electrode of the sampling capacitor SAMC in response to the reference signal SREF. The first initialization voltage switch IVSW1 may apply the initialization voltage VINT to the first intermediate node NI1 in response to the first capacitor initialization signal CIS1. The first capacitor initialization switch CISW1 may connect the first intermediate node NI1 to the first electrode of the sampling capacitor SAMC in response to the reference signal SREF.

[0076] A voltage having a first initialization level may be applied to the first electrode of the sampling capacitor SAMC in a first capacitor initialization period of the first sub-sensing period, and a voltage having a second initialization level different from the first initialization level may be applied to the first electrode of the sampling capacitor SAMC in a second capacitor initialization period of the second sub-sensing period. In an embodiment, the second initialization level may be higher than the first initialization level.

[0077] In an embodiment, Figure 5 An initialization voltage VINT having a first voltage level LV1 may be applied to a first electrode of the sampling capacitor SAMC in a first capacitor initialization period of the first sub sensing period, and Figure 5 The initialization voltage VINT having the second voltage level LV2 may be applied to the first electrode of the sampling capacitor SAMC in the second capacitor initialization period of the second sub-sensing period. In an embodiment, the initialization voltage VINT may have a first voltage level LV1 in the first sub-sensing period, and may have a second voltage level LV2 different from the first voltage level LV1 in the second capacitor initialization period and the second sampling period of the second sub-sensing period.

[0078] The reference channel 350-1, ..., 350-N can store a voltage (e.g., initialization voltage VINT) used as a reference for the first sensing voltage or the second sensing voltage sampled by the sensing channel 340-1, ..., 340-N, so that the analog-to-digital converter 380 performs an analog-to-digital conversion operation on the voltage difference between the voltage output from the sensing channel 340-1, ..., 340-N and the voltage output from the reference channel 350-1, ..., 350-N. In an embodiment, each of the reference channels 350-1, ..., 350-N may include a reference capacitor REFC, a second sampling switch SAMSW2, a second reference switch RSW2, a second initialization voltage switch IVSW2, and a second capacitor initialization switch CISW2. For example, the reference capacitor REFC may have a first electrode and a second electrode. The second sampling switch SAMSW2 may apply the initialization voltage VINT to the first electrode of the reference capacitor REFC in response to the sampling signal SAMS. The second reference switch RSW2 may apply the reference voltage VREF to the second electrode of the reference capacitor REFC in response to the reference signal SREF. The second initialization voltage switch IVSW2 may apply the initialization voltage VINT to the second intermediate node NI2 in response to the first capacitor initialization signal CIS1. The second capacitor initialization switch CISW2 may connect the second intermediate node NI2 to the first electrode of the reference capacitor REFC in response to the reference signal SREF.

[0079] The switch matrix 360 and the analog-to-digital converter 380 may sequentially convert the first sensing voltages of the odd sensing lines SL1, ..., SL2N-1 sampled by the sensing channels 340-1, ..., 340-N into N first sensing data, and may sequentially convert the second sensing voltages of the even sensing lines SL2, ..., SL2N sampled by the sensing channels 340-1, ..., 340-N into N second sensing data. For example, in a first analog-to-digital conversion period of a first sub-sensing period, the switch matrix 360 may sequentially connect the sensing channels 340-1, ..., 340-N to the analog-to-digital converter 380, the switch matrix 360 may sequentially connect the reference channels 350-1, ..., 350-N to the analog-to-digital converter 380, and the analog-to-digital converter 380 may sequentially convert the first sensing voltages of the odd sensing lines SL1, ..., SL2N-1 into first sensing data. In addition, in the second analog-to-digital conversion period of the second sub-sensing period, the switch matrix 360 may sequentially connect the sensing channels 340-1, ..., 340-N to the analog-to-digital converter 380, the switch matrix 360 may sequentially connect the reference channels 350-1, ..., 350-N to the analog-to-digital converter 380, and the analog-to-digital converter 380 may sequentially convert the second sensing voltages of the even sensing lines SL2, ..., SL2N into second sensing data. In an embodiment, the switch matrix 360 may include a first N-to-1 switch NTOSW1 that connects one of the sensing channels 340-1, ..., 340-N to a first input terminal (e.g., a positive input terminal) of the analog-to-digital converter 380 and a second N-to-1 switch NTOSW2 that connects one of the reference channels 350-1, ..., 350-N to a second input terminal (e.g., a negative input terminal) of the analog-to-digital converter 380.

[0080] The data output unit 390 may sequentially store the first sensing data in the first analog-to-digital conversion period, may sequentially store the second sensing data in the second analog-to-digital conversion period, and may output the first sensing data and the second sensing data in the output period of the sensing period. In an embodiment, the data output unit 390 may rearrange the first sensing data and the second sensing data so that each second sensing data is disposed between two adjacent first sensing data. For example, the data output unit 390 may rearrange the first sensing data and the second sensing data so that 2N sensing data of the sensing lines SL1, SL2, ..., SL2N-1, SL2N are sequentially output.

[0081] Figure 4 is a diagram for describing charge sharing between the second line capacitor CL2 and the sampling capacitor SAMC.

[0082] refer to Figure 4 , also refer to Figure 1, between the second capacitor initialization period of the second sub-sensing period and the second sampling period, the second sensing voltage VSEN2 may be stored in the second line capacitor CL2 of the second sensing line SL2, and the initialization voltage VINT may be applied to the first electrode of the sampling capacitor SAMC. The sum QT of the amount of charge accumulated in the second line capacitor CL2 and the amount of charge accumulated in the sampling capacitor SAMC before the second sampling period may be calculated by Equation 1.

[0083] [Equation 1]

[0084] QT=CL2×VSEN2+SAMC×VINT

[0085] The first sampling switch SAMSW1 may be turned on in the second sampling period, and the sum of the amount of charge accumulated in the second line capacitor CL2 and the amount of charge accumulated in the sampling capacitor SAMC in the second sampling period may be equal to the sum QT of the amount of charge accumulated in the second line capacitor CL2 and the amount of charge accumulated in the sampling capacitor SAMC before the second sampling period of the second sub-sensing period. The voltage VSEN2' of the first electrode of the sampling capacitor SAMC due to charge sharing between the second line capacitor CL2 and the sampling capacitor SAMC in the second sampling period may be calculated by Equation 2.

[0086] [Equation 2]

[0087]

[0088] When the initialization voltage VINT is different from the second sensing voltage VSEN2, the voltage VSEN2' of the first electrode of the sampling capacitor SAMC may be different from the second sensing voltage VSEN2, and the voltage sampled by the sensing channel in the second sampling period may be different from the second sensing voltage VSEN2. For example, when the voltage level of the initialization voltage VINT is lower than the voltage level of the second sensing voltage VSEN2, the voltage level of the voltage VSEN2' of the first electrode of the sampling capacitor SAMC may be lower than the voltage level of the second sensing voltage VSEN2, and the voltage level of the voltage sampled by the sensing channel in the second sampling period may be lower than the voltage level of the second sensing voltage VSEN2. Therefore, although the first sensing voltage is equal to the second sensing voltage VSEN2, a deviation corresponding to the difference between the second sensing voltage VSEN2 and the voltage VSEN2' of the first electrode of the sampling capacitor SAMC may occur between the first sensing data and the second sensing data. In the comparative example of the present disclosure, the voltage level of the initialization voltage VINT may be equal in the first sub-sensing period and the second sub-sensing period, and although the first sensing voltage is equal to the second sensing voltage VSEN2, a deviation may occur between the first sensing data and the second sensing data due to the difference between the initialization voltage VINT and the second sensing voltage VSEN2. However, as described above, in the embodiment of the present disclosure, the initialization voltage VINT may have a first voltage level in the first sub-sensing period, and may have a second voltage level different from the first voltage level (e.g., higher than the first voltage level) in at least a portion of the second sub-sensing period. Therefore, the difference between the initialization voltage VINT and the second sensing voltage VSEN2 may be substantially absent or reduced, and the deviation between the first sensing data and the second sensing data may be reduced.

[0089] Figure 5 is used to describe the sensing driver 300 (see Figure 3 ) operation timing diagram. Figure 6 is a diagram for describing an operation of the sensing driver 300 in the sensing line initialization period SLIP. Figure 7 is a diagram for describing an operation of the sensing driver 300 in the first capacitor initialization period CIP1 . Figure 8 is a diagram for describing an operation of the sensing driver 300 in the first sampling period SAMP1. Fig. 9 is a diagram for describing an operation of the sensing driver 300 in the first analog-to-digital conversion period ADCP1 . Fig.10 is a diagram for describing an operation of the sensing driver 300 in the second capacitor initialization period CIP2 . Fig.11 is a diagram for describing an operation of the sensing driver 300 in the second sampling period SAMP2. Fig.12is a diagram for describing an operation of the sensing driver 300 in the second analog-to-digital conversion period ADCP2 . Fig.13 is a diagram for describing rearrangement of first sensing data and second sensing data.

[0090] refer to Figure 3 and Figures 5 to 13 , the sensing period SP may include a first sub-sensing period SUBP1 for performing a first sensing operation on the odd sensing lines SL1, ..., SL2N-1, a second sub-sensing period SUBP2 for performing a second sensing operation on the even sensing lines SL2, ..., SL2N, and a data output period DOP for outputting sensing data SD. Hereinafter, for ease of description, a first sensing operation on the first sensing line SL1 among the odd sensing lines SL1, ..., SL2N-1 and a second sensing operation on the second sensing line SL2 among the even sensing lines SL2, ..., SL2N will be described. The first sensing operation on the other sensing lines among the odd sensing lines SL1, ..., SL2N-1 may be substantially the same as the first sensing operation on the first sensing line SL1, and the second sensing operation on the other sensing lines among the even sensing lines SL2, ..., SL2N may be substantially the same as the second sensing operation on the second sensing line SL2.

[0091] The first sub sensing period SUBP1 may include a sensing line initialization period SLIP, a first capacitor initialization period CIP1, a first sampling period SAMP1, and a first analog-to-digital conversion period ADCP1. In an embodiment, the first capacitor initialization period CIP1 may overlap with the sensing line initialization period SLIP. In an embodiment, the initialization voltage VINT may have a first voltage level LV1 in the first sub sensing period SUBP1.

[0092] In the sensing line initialization period SLIP, the sensing line initialization circuit 320 may substantially simultaneously initialize the first sensing line SL1 and the second sensing line SL2. Figure 5 and Figure 6 As shown in, in the sensing line initialization period SLIP, the sensing line initialization signal SLIS may have an activation level, and the first sensing line initialization switch SLISW1 may apply the initialization voltage VINT to the first sensing line SL1 in response to the sensing line initialization signal SLIS having the activation level, the second sensing line initialization switch SLISW2 may apply the initialization voltage VINT to the second sensing line SL2 in response to the sensing line initialization signal SLIS having the activation level, and the first sensing line SL1 and the second sensing line SL2 may be initialized based on the initialization voltage VINT.

[0093] In the sensing line initialization period SLIP, the first reference switch RSW1 and the second reference switch RSW2 can be turned on in response to the reference signal SREF having an activation level, the reference voltage VREF can be applied to the second electrode of the sampling capacitor SAMC through the first reference switch RSW1, and the reference voltage VREF can be applied to the second electrode of the reference capacitor REFC through the second reference switch RSW2.

[0094] In the first capacitor initialization period CIP1, the sampling capacitor SAMC and the reference capacitor REFC may be initialized. In an embodiment, the first capacitor initialization period CIP1 may overlap a portion of the sensing line initialization period SLIP (eg, an end portion of the sensing line initialization period SLIP). Figure 5 and Figure 7 As shown in, in the first capacitor initialization period CIP1, the sampling signal SAMS, the sensing line initialization signal SLIS, and the first line selection signal LSS1 may have an activation level. The first sampling switch SAMSW1 and the second sampling switch SAMSW2 may be turned on in response to the sampling signal SAMS having an activation level, the first sensing line initialization switch SLISW1 may be turned on in response to the initialization signal SLIS having an activation level, and the first line selection switch LSSW1-1 may be turned on in response to the first line selection signal LSS1 having an activation level. Therefore, the initialization voltage VINT having a first voltage level LV1 may be applied to the first electrode of the sampling capacitor SAMC through the first sensing line initialization switch SLISW1, the first line selection switch LSSW1-1, and the first sampling switch SAMSW1, and may be applied to the first electrode of the reference capacitor REFC through the second sampling switch SAMSW2. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the initialization voltage VINT having the first voltage level LV1 and the reference voltage VREF.

[0095] In an embodiment, the sampling signal SAMS may have an activation level after a delay time TDLY from the first sub sensing period SUBP1. Since the activation time point of the sampling signal SAMS is delayed by the delay time TDLY, the first sensing operation may be more stably performed.

[0096] In the first sampling period SAMP1, the voltage of the first sensing line SL1 may be saturated to the first sensing voltage VSEN1, the voltage of the second sensing line SL2 may be saturated to the second sensing voltage VSEN2, and the sensing channel 340-1 may sample the first sensing voltage VSEN1 of the first sensing line SL1. Figure 5 and Figure 8As shown in, in the first sampling period SAMP1, the first line selection signal LSS1 and the sampling signal SAMS may have an activation level, and the second line selection signal LSS2 may have an inactive level. The first line selection switch LSSW1-1 may be turned on in response to the first line selection signal LSS1 having an activation level, and the first sampling switch SAMSW1 and the second sampling switch SAMSW2 may be turned on in response to the sampling signal SAMS having an activation level. Therefore, the first sensing voltage VSEN1 of the first sensing line SL1 may be applied to the first electrode of the sampling capacitor SAMC through the first line selection switch LSSW1-1 and the first sampling switch SAMSW1, and the initialization voltage VINT may be applied to the first electrode of the reference capacitor REFC through the second sampling switch SAMSW2.

[0097] In the first analog-to-digital conversion period ADCP1, the switch matrix 360 and the analog-to-digital converter 380 may sequentially convert the first sensing voltage VSEN1 of the odd sensing lines SL1, ..., SL2N-1 sampled by the sensing channels 340-1, ..., 340-N (or the sensing channels CH1, CH2, ..., CHN) into the first sensing data. The second electrode of the sampling capacitor SAMC and the second electrode of the reference capacitor REFC may have a first voltage difference VSEN1-VINT from which the initialization voltage VINT is subtracted from the first sensing voltage VSEN1. The switch matrix 360 may connect the second electrode of the sampling capacitor SAMC and the second electrode of the reference capacitor REFC to the first input terminal and the second input terminal of the analog-to-digital converter 380, respectively, and the analog-to-digital converter 380 may convert the first voltage difference VSEN1-VINT into the first sensing data. The analog-to-digital conversion operation by the switch matrix 360 and the analog-to-digital converter 380 may be sequentially performed from the first sensing channel 340-1 (or the first sensing channel CH1) to the Nth sensing channel 340-N (or the Nth sensing channel CHN).

[0098] The data output unit 390 may sequentially store the first sensing data generated by the analog-to-digital converter 380 in the first analog-to-digital conversion period ADCP1 .

[0099] The second sub-sensing period SUBP2 may include a second capacitor initialization period CIP2, a second sampling period SAMP2, and a second analog-to-digital conversion period ADCP2. In an embodiment, the initialization voltage VINT may have a second voltage level LV2 different from the first voltage level LV1 in the second capacitor initialization period CIP2 and the second sampling period SAMP2 of the second sub-sensing period SUBP2. For example, Figure 5 As shown in , the second voltage level LV2 of the initialization voltage VINT may be higher than the first voltage level LV1 of the initialization voltage VINT.

[0100] In an embodiment, a second initialization level (eg, a second voltage level LV2 of the initialization voltage VINT) may be set before the sensing period SP. For example, the second initialization level may be set to a pre-calculated value to reduce a deviation between the first sensing data and the second sensing data.

[0101] In an embodiment, the second initialization level may be set based on the first sensing voltage VSEN1 of the odd sensing lines SL1, ..., SL2N-1 and the second sensing voltage VSEN2 of the even sensing lines SL2, ..., SL2N. For example, the second initialization level may be set to an average value of the first sensing voltage VSEN1 and the second sensing voltage VSEN2. Therefore, the sensing voltages of the sensing lines SL1, SL2, ..., SL2N-1, SL2N saturated in the first sampling period SAMP1 of the first sub-sensing period SUBP1 may be used to calculate the second initialization level in the second sub-sensing period SUBP2.

[0102] In an embodiment, the second initialization level may be set based on the sensing voltages of some sensing lines (e.g., sensing lines in a specific area) among the sensing lines SL1, SL2, ..., SL2N-1, SL2N. Since it takes a long time to calculate the second initialization level based on the sensing voltages of all the sensing lines SL1, SL2, ..., SL2N-1, SL2N, the second initialization level may be set based on the sensing voltages of some sensing lines among the sensing lines SL1, SL2, ..., SL2N-1, SL2N.

[0103] In the second capacitor initialization period CIP2, the sampling capacitor SAMC and the reference capacitor REFC may be initialized. Figure 5 and Fig.10As shown in, in the second capacitor initialization period CIP2, the first capacitor initialization signal CIS1 and the reference signal SREF may have an activation level. The first initialization voltage switch IVSW1 and the second initialization voltage switch IVSW2 may be turned on in response to the first capacitor initialization signal CIS1 having an activation level, and the first capacitor initialization switch CISW1 and the second capacitor initialization switch CISW2 may be turned on in response to the reference signal SREF having an activation level. Therefore, the initialization voltage VINT having the second voltage level LV2 may be applied to the first electrode of the sampling capacitor SAMC through the first initialization voltage switch IVSW1 and the first capacitor initialization switch CISW1, and may be applied to the first electrode of the reference capacitor REFC through the second initialization voltage switch IVSW2 and the second capacitor initialization switch CISW2. In addition, the first reference switch RSW1 and the second reference switch RSW2 may be turned on in response to the reference signal SREF having an activation level, the reference voltage VREF may be applied to the second electrode of the sampling capacitor SAMC through the first reference switch RSW1, and the reference voltage VREF may be applied to the second electrode of the reference capacitor REFC through the second reference switch RSW2. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the initialization voltage VINT having the second voltage level LV2 and the reference voltage VREF.

[0104] In the second sampling period SAMP2, the sensing channel 340-1 may sample the second sensing voltage VSEN2 of the second sensing line SL2. The second sensing line SL2 may maintain the second sensing voltage VSEN2 saturated in the first sampling period SAMP1 until the second sampling period SAMP2. Figure 5 and Fig.11 As shown in, in the second sampling period SAMP2, the second line selection signal LSS2 and the sampling signal SAMS may have an activation level, and the first line selection signal LSS1 may have an inactive level. The second line selection switch LSSW2-1 may be turned on in response to the second line selection signal LSS2 having an activation level, and the first sampling switch SAMSW1 and the second sampling switch SAMSW2 may be turned on in response to the sampling signal SAMS having an activation level. Therefore, the second sensing voltage VSEN2 of the second sensing line SL2 may be applied to the first electrode of the sampling capacitor SAMC through the second line selection switch LSSW2-1 and the first sampling switch SAMSW1, and the initialization voltage VINT may be applied to the first electrode of the reference capacitor REFC through the second sampling switch SAMSW2.

[0105] In the second analog-to-digital conversion period ADCP2, the switch matrix 360 and the analog-to-digital converter 380 may sequentially convert the second sensing voltage VSEN2 of the even sensing lines SL2, ..., SL2N sampled by the sensing channels 340-1, ..., 340-N (or the sensing channels CH1, CH2, ..., CHN) into second sensing data. The second electrode of the sampling capacitor SAMC and the second electrode of the reference capacitor REFC may have a second voltage difference VSEN2-VINT from which the initialization voltage VINT is subtracted from the second sensing voltage VSEN2. The switch matrix 360 may connect the second electrode of the sampling capacitor SAMC and the second electrode of the reference capacitor REFC to the first input terminal and the second input terminal of the analog-to-digital converter 380, respectively, and the analog-to-digital converter 380 may convert the second voltage difference VSEN2-VINT into second sensing data. The analog-to-digital conversion operation by the switch matrix 360 and the analog-to-digital converter 380 may be sequentially performed from the first sensing channel 340-1 (or the first sensing channel CH1) to the Nth sensing channel 340-N (or the Nth sensing channel CHN).

[0106] The data output unit 390 may sequentially store the second sensing data generated by the analog-to-digital converter 380 in the second analog-to-digital conversion period ADCP2.

[0107] In the data output period DOP, the data output unit 390 may output the first sensing data generated in the first sub-sensing period SUBP1 and the second sensing data generated in the second sub-sensing period SUBP2. Fig.13 As shown in, the first sensing data SD1, SD3, ..., SD2N-1 about the odd sensing lines SL1, ..., SL2N-1 may be generated in the first sub sensing period SUBP1, and the second sensing data SD2, SD4, ..., SD2N about the even sensing lines SL2, ..., SL2N may be generated in the second sub sensing period SUBP2. In an embodiment, the data output unit 390 may rearrange the first sensing data SD1, SD3, ..., SD2N-1 and the second sensing data SD2, SD4, ..., SD2N, and may output the rearranged sensing data SD1, SD2, SD3, SD4, ..., SD2N-1, SD2N. For example, the data output unit 390 can output the sensing data SD1, SD2, SD3, SD4,..., SD2N-1, SD2N which are rearranged in the order of sensing data SD1 of the first sensing line SL1, sensing data SD2 of the second sensing line SL2, sensing data SD3 of the third sensing line SL3, sensing data SD4 of the fourth sensing line SL4,..., sensing data SD2N-1 of the 2N-1 sensing line SL2N-1, and sensing data SD2N of the 2N sensing line SL2N.

[0108] Figure 5 An embodiment in which each of the scan signal SC and the sense signal SS transitions from the on voltage level to the off voltage level within the second analog-to-digital conversion period ADCP2 is shown, however, the present disclosure is not limited thereto. In an embodiment, each of the scan signal SC and the sense signal SS may transition from the on voltage level to the off voltage level within a period from the start of the first analog-to-digital conversion period ADCP1 to the end of the second analog-to-digital conversion period ADCP2.

[0109] Fig.14 is a diagram illustrating images displayed by a display device according to a comparative example and an embodiment of the present disclosure.

[0110] refer to Fig.14 , the controller can generate output image data provided to the odd pixel columns C_OD by compensating the input image data based on the first sensing data, and can generate output image data provided to the even pixel columns C_EV by compensating the input image data based on the second sensing data. In a comparative example of the present disclosure, when a deviation occurs between the first sensing data and the second sensing data, a deviation may occur between the output image data provided to the odd pixel columns C_OD and the output image data provided to the even pixel columns C_EV. Therefore, the input image data may not be accurately compensated based on the sensing data, and the vertical line may be visible in the image displayed by the display device. However, in an embodiment of the present disclosure, as the deviation between the first sensing data and the second sensing data decreases, the deviation between the output image data provided to the odd pixel columns C_OD and the output image data provided to the even pixel columns C_EV can be reduced. Therefore, the input image data can be accurately compensated based on the sensing data, and the vertical line may not be visible in the image displayed by the display device.

[0111] Fig.15 is a block diagram illustrating a sensing driver 400 according to an embodiment of the present disclosure. Fig.15 The sensing driver 400 may correspond to the one included in Figure 1 The sensing driver 140 in the display device 100.

[0112] refer to Fig.15, the sensing driver 400 may perform sensing operations on 2N sensing lines SL1, SL2, ..., SL2N-1, SL2N. The sensing driver 400 may include N first line selection switches LSSW1-1, ..., LSSW1-N, N second line selection switches LSSW2-1, ..., LSSW2-N, a sensing line initialization circuit 420, N sensing channels 440-1, ..., 440-N, N reference channels 450-1, ..., 450-N, a switch matrix 460, an analog-to-digital converter 480, and a data output unit 490. Reference channels 440-1, ..., 440-N, and reference channels 450-1, ..., 450-N may be omitted. Fig.15 The sensing driver 400 described in reference Figure 3 The components of the sensing driver 300 described are substantially the same as or similar to the components described herein.

[0113] In an embodiment, each of the sensing channels 440-1, ..., 440-N may include a sampling capacitor SAMC, a first sampling switch SAMSW1, a first reference switch RSW1, a first initialization voltage switch IVSW1, a first reference voltage switch RVSW1, a first external voltage switch EVSW1, and a first capacitor initialization switch CISW1. For example, the first reference voltage switch RVSW1 may apply a reference voltage VREF to the first intermediate node NI1 in response to the second capacitor initialization signal CIS2. The first external voltage switch EVSW1 may apply an external voltage VEXT to the first intermediate node NI1 in response to the third capacitor initialization signal CIS3.

[0114] A voltage having a first initialization level may be applied to the first electrode of the sampling capacitor SAMC in a first capacitor initialization period of the first sub-sensing period, and a voltage having a second initialization level different from the first initialization level may be applied to the first electrode of the sampling capacitor SAMC in a second capacitor initialization period of the second sub-sensing period. In an embodiment, the second initialization level may be higher than the first initialization level. In an embodiment, the initialization voltage VINT may have a voltage of 0.01% in the first sub-sensing period. Fig.16 and may have a first voltage level LV1 in the second capacitor initialization period and the second sampling period in the second sub-sensing period. Fig.16 The reference voltage VREF may have a second voltage level LV2 different from the first voltage level LV1 in the first sub-sensing period. Fig.16 The third voltage level LV3 in the second sub-sensing period and the second capacitor initialization period and the second sampling period may have Fig.16 The external voltage VEXT may have a fourth voltage level LV4 different from the third voltage level LV3 in the first sub-sensing period. Fig.16The fifth voltage level LV5 in the second sub-sensing period and the second capacitor initialization period and the second sampling period may have Fig.16 A sixth voltage level LV6 different from the fifth voltage level LV5.

[0115] In an embodiment, each of the reference channels 450-1, ..., 450-N may include a reference capacitor REFC, a second sampling switch SAMSW2, a second reference switch RSW2, a second initialization voltage switch IVSW2, a second reference voltage switch RVSW2, a second external voltage switch EVSW2, and a second capacitor initialization switch CISW2. For example, the second reference voltage switch RVSW2 may apply a reference voltage VREF to the second intermediate node NI2 in response to a second capacitor initialization signal CIS2. The second external voltage switch EVSW2 may apply an external voltage VEXT to the second intermediate node NI2 in response to a third capacitor initialization signal CIS3.

[0116] Fig.16 is used to describe the sensing driver 400 (see Fig.15 ) operation timing diagram. Fig.17 is a diagram for describing an operation of the sensing driver 400 in the second capacitor initialization period CIP2 .

[0117] References will be omitted Fig.16 and Fig.17 The operation of the sensing driver 400 is described with reference to Figures 5 to 13 The steps of describing the operation of the sensing driver 300 are substantially the same as or similar to the steps described above.

[0118] refer to Fig.16 and Fig.17, in the second capacitor initialization period CIP2, the sampling capacitor SAMC and the reference capacitor REFC may be initialized. For example, in the second capacitor initialization period CIP2, the first capacitor initialization signal CIS1 and the reference signal SREF may have an activation level, and the second capacitor initialization signal CIS2 and the third capacitor initialization signal CIS3 may have an inactive level. The first initialization voltage switch IVSW1 and the second initialization voltage switch IVSW2 may be turned on in response to the first capacitor initialization signal CIS1 having an activation level, and the first capacitor initialization switch CISW1 and the second capacitor initialization switch CISW2 may be turned on in response to the reference signal SREF having an activation level. Therefore, the initialization voltage VINT having the second voltage level LV2 may be applied to the first electrode of the sampling capacitor SAMC through the first initialization voltage switch IVSW1 and the first capacitor initialization switch CISW1, and may be applied to the first electrode of the reference capacitor REFC through the second initialization voltage switch IVSW2 and the second capacitor initialization switch CISW2. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the initialization voltage VINT having the second voltage level LV2.

[0119] Fig.18 is used to describe the sensing driver 400 (see Fig.15 ) operation timing diagram. Fig.19 is a diagram for describing an operation of the sensing driver 400 in the second capacitor initialization period CIP2 .

[0120] References will be omitted Fig.18 and Fig.19 The operation of the sensing driver 400 is described with reference to Figures 5 to 13 The steps described for the operation of the sensing driver 300 are substantially the same as or similar to the steps described herein.

[0121] refer to Fig.18 and Fig.19, in the second capacitor initialization period CIP2, the sampling capacitor SAMC and the reference capacitor REFC may be initialized. For example, in the second capacitor initialization period CIP2, the second capacitor initialization signal CIS2 and the reference signal SREF may have an activation level, and the first capacitor initialization signal CIS1 and the third capacitor initialization signal CIS3 may have an inactive level. The first reference voltage switch RVSW1 and the second reference voltage switch RVSW2 may be turned on in response to the second capacitor initialization signal CIS2 having an activation level, and the first capacitor initialization switch CISW1 and the second capacitor initialization switch CISW2 may be turned on in response to the reference signal SREF having an activation level. Therefore, the reference voltage VREF having a fourth voltage level LV4 may be applied to the first electrode of the sampling capacitor SAMC through the first reference voltage switch RVSW1 and the first capacitor initialization switch CISW1, and may be applied to the first electrode of the reference capacitor REFC through the second reference voltage switch RVSW2 and the second capacitor initialization switch CISW2. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the reference voltage VREF having a fourth voltage level LV4.

[0122] Fig. 20 is used to describe the sensing driver 400 (see Fig.15 ) operation timing diagram. Fig.21 is a diagram for describing an operation of the sensing driver 400 in the second capacitor initialization period CIP2 .

[0123] References will be omitted Fig. 20 and Fig.21 The operation of the sensing driver 400 is described with reference to Figures 5 to 13 The steps of describing the operation of the sensing driver 300 are substantially the same as or similar to the steps described above.

[0124] refer to Fig. 20 and Fig.21, in the second capacitor initialization period CIP2, the sampling capacitor SAMC and the reference capacitor REFC may be initialized. For example, in the second capacitor initialization period CIP2, the third capacitor initialization signal CIS3 and the reference signal SREF may have an activation level, and the first capacitor initialization signal CIS1 and the second capacitor initialization signal CIS2 may have a non-activation level. The first external voltage switch EVSW1 and the second external voltage switch EVSW2 may be turned on in response to the third capacitor initialization signal CIS3 having an activation level, and the first capacitor initialization switch CISW1 and the second capacitor initialization switch CISW2 may be turned on in response to the reference signal SREF having an activation level. Therefore, the external voltage VEXT having the sixth voltage level LV6 may be applied to the first electrode of the sampling capacitor SAMC through the first external voltage switch EVSW1 and the first capacitor initialization switch CISW1, and may be applied to the first electrode of the reference capacitor REFC through the second external voltage switch EVSW2 and the second capacitor initialization switch CISW2. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the external voltage VEXT having the sixth voltage level LV6.

[0125] Fig. 22 FIG. 2 is a diagram showing the driving sensing drivers 300 and 400 (see FIG. 2 ) according to an embodiment of the present disclosure. Figure 3 and Fig.15 ) is a flow chart of a method.

[0126] refer to Figure 3 , Figure 5 , Fig.15 , Fig.16 , Fig.18 , Fig. 20 and Fig. 22 , in the method of driving the sensing drivers 300 and 400, the sensing period SP may include a first sub-sensing period SUBP1 for performing a first sensing operation on the odd sensing lines SL1, ..., SL2N-1 including the first sensing line SL1, a second sub-sensing period SUBP2 for performing a second sensing operation on the even sensing lines SL2, ..., SL2N including the second sensing line SL2, and a data output period DOP for outputting sensing data. The first sub-sensing period SUBP1 may include a first capacitor initialization period CIP1 and a first sampling period SAMP1, and the second sub-sensing period SUBP2 may include a second capacitor initialization period CIP2 and a second sampling period SAMP2. Hereinafter, for ease of description, a first sensing operation on the first sensing line SL1 among the odd sensing lines SL1, ..., SL2N-1 and a second sensing operation on the second sensing line SL2 among the even sensing lines SL2, ..., SL2N will be described.

[0127] In the first sub sensing period SUBP1, the first line selection switch LSSW1-1 may connect the first sensing line SL1 to the sensing channels 340-1 and 440-1 in operation S1510. For example, the first line selection signal LSS1 may have an activation level in the first sampling period SAMP1, and the first line selection switch LSSW1-1 may connect the first sensing line SL1 to the sensing channels 340-1 and 440-1 in response to the first line selection signal LSS1 having the activation level.

[0128] In the first capacitor initialization period CIP1, in operation S1520, the sensing channels 340-1 and 440-1 and the reference channels 350-1 and 450-1 may apply a voltage having a first initialization level to a first electrode of the sampling capacitor SAMC and a first electrode of the reference capacitor REFC. In an embodiment, in the first capacitor initialization period CIP1, the sensing channels 340-1 and 440-1 and the reference channels 350-1 and 450-1 may apply an initialization voltage VINT having a first voltage level LV1 to a first electrode of the sampling capacitor SAMC and a first electrode of the reference capacitor REFC. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the initialization voltage VINT having the first voltage level LV1.

[0129] In the first sampling period SAMP1, the voltage of the first sensing line SL1 may be saturated to the first sensing voltage VSEN1, and in operation S1530, the sensing channels 340-1 and 440-1 may sample the first sensing voltage VSEN1 of the first sensing line SL1. The sampling capacitor SAMC may store the first sensing voltage VSEN1. The first sensing voltage VSEN1 sampled by the sensing channels 340-1 and 440-1 may be provided to the analog-to-digital converters 380 and 480, and the analog-to-digital converters 380 and 480 may convert the first sensing voltage VSEN1 into first sensing data.

[0130] In the second capacitor initialization period CIP2, in operation S1540, the sensing channels 340-1 and 440-1 and the reference channels 350-1 and 450-1 may apply a voltage having a second initialization level to a first electrode of the sampling capacitor SAMC and a first electrode of the reference capacitor REFC. In an embodiment, in the second capacitor initialization period CIP2, the sensing channels 340-1 and 440-1 and the reference channels 350-1 and 450-1 may apply an initialization voltage VINT having a second voltage level LV2, a reference voltage VREF having a fourth voltage level LV4, or an external voltage VEXT having a sixth voltage level LV6 to a first electrode of the sampling capacitor SAMC and a first electrode of the reference capacitor REFC. Therefore, the sampling capacitor SAMC and the reference capacitor REFC may be initialized or discharged based on the initialization voltage VINT having a second voltage level LV2, the reference voltage VREF having a fourth voltage level LV4, or the external voltage VEXT having a sixth voltage level LV6.

[0131] In the second sub sensing period SUBP2, the second line selection switch LSSW2-1 may connect the second sensing line SL2 to the sensing channels 340-1 and 440-1 in operation S1550. For example, the second line selection signal LSS2 may have an activation level in the second sampling period SAMP2, and the second line selection switch LSSW2-1 may connect the second sensing line SL2 to the sensing channels 340-1 and 440-1 in response to the second line selection signal LSS2 having the activation level.

[0132] In the second sampling period SAMP2, the voltage of the second sensing line SL2 may be saturated to the second sensing voltage VSEN2, and in operation S1560, the sensing channels 340-1 and 440-1 may sample the second sensing voltage VSEN2 of the second sensing line SL2. The sampling capacitor SAMC may store the second sensing voltage VSEN2. The second sensing voltage VSEN2 sampled by the sensing channels 340-1 and 440-1 may be provided to the analog-to-digital converters 380 and 480, and the analog-to-digital converters 380 and 480 may convert the second sensing voltage VSEN2 into second sensing data.

[0133] In the data output period DOP, the sensing drivers 300 and 400 may output the first sensing data and the second sensing data to the controller in operation S1570. The controller may generate output image data by compensating the input image data based on the first sensing data and the second sensing data.

[0134] In the method of driving the sensing drivers 300 and 400, the second initialization level of the voltage applied to the first electrode of the sampling capacitor SAMC in the second capacitor initialization period CIP2 may be different from the first initialization level of the voltage applied to the first electrode of the sampling capacitor SAMC in the first capacitor initialization period CIP1. For example, the second initialization level may be higher than the first initialization level. In an embodiment, the initialization voltage VINT may have a first voltage level LV1 in the first sub-sensing period SUBP1, and may have a second voltage level LV2 in the second sub-sensing period SUBP2. The reference voltage VREF may have a third voltage level LV3 in the first sub-sensing period SUBP1, and may have a fourth voltage level LV4 in the second sub-sensing period SUBP2. The external voltage VEXT may have a fifth voltage level LV5 in the first sub-sensing period SUBP1, and may have a sixth voltage level LV6 in the second sub-sensing period SUBP2.

[0135] In an embodiment, a second initialization level (e.g., a second voltage level LV2 of the initialization voltage VINT, a fourth voltage level LV4 of the reference voltage VREF, and a sixth voltage level LV6 of the external voltage VEXT) may be set before the sensing period SP. In an embodiment, the second initialization level may be set based on the first sensing voltage VSEN1 and the second sensing voltage VSEN2. For example, the second initialization level may be set to an average value of the first sensing voltage VSEN1 of the odd sensing lines SL1, ..., SL2N-1 and the second sensing voltage VSEN2 of the even sensing lines SL2, ..., SL2N.

[0136] Fig.23 FIG. 2 is a diagram showing the driving sensing drivers 300 and 400 (see FIG. 2 ) according to an embodiment of the present disclosure. Figure 3 and Fig.15 ) is a flow chart of a method.

[0137] refer to Figure 3 , Figure 5 , Fig.15 , Fig.16 , Fig.18 , Fig. 20 and Fig.23 In the method of driving the sensing drivers 300 and 400, the sensing period SP may include a first sub-sensing period SUBP1 in which a first sensing operation is performed on the odd sensing lines SL1, ..., SL2N-1 including the first sensing line SL1, a second sub-sensing period SUBP2 in which a second sensing operation is performed on the even sensing lines SL2, ..., SL2N including the second sensing line SL2, a data comparison period in which sensing data is compared, and a data output period DOP in which sensing data is output. Reference will be omitted Fig.23The method of driving the sensing drivers 300 and 400 described in reference Fig. 22 The operations of the methods of driving the sensing drivers 300 and 400 described are substantially the same as or similar to the description of the operations (eg, Fig.23 The operations S1610, S1620, S1630, S1640, S1650, and S1660 in Fig. 22 Operations S1510, S1520, S1530, S1540, S1550 and S1560).

[0138] In the data comparison period, the first sensing data may be compared with the second sensing data in operation S1680. When the deviation between the first sensing data and the second sensing data is approximately 0 (e.g., when the difference between the deviation and 0 is within a predetermined error range), the sensing drivers 300 and 400 may output the first sensing data and the second sensing data to the controller in the data output period DOP in operation S1670.

[0139] When the deviation between the first sensing data and the second sensing data is not approximately 0 (e.g., when the difference between the deviation and 0 is outside the predetermined error range), in operation S1690, the second initialization level may be changed. In an embodiment, the second voltage level LV2 of the initialization voltage VINT, the fourth voltage level LV4 of the reference voltage VREF, and the sixth voltage level LV6 of the external voltage VEXT may be changed. In an embodiment, the second initialization level (e.g., the second voltage level LV2 of the initialization voltage VINT, the fourth voltage level LV4 of the reference voltage VREF, and the sixth voltage level LV6 of the external voltage VEXT) may be increased or decreased by a predetermined amount so that the deviation between the first sensing data and the second sensing data is reduced.

[0140] Fig.24 is a block diagram illustrating an electronic device 1700 including a display device 1760 according to an embodiment of the present disclosure.

[0141] refer to Fig.24 , the electronic device 1700 may include a processor 1710, a memory device 1720, a storage device 1730, an input / output ("I / O") device 1740, a power supply 1750, and a display device 1760. The display device 1760 may correspond to Figure 1 The electronic device 1700 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, and the like.

[0142] The processor 1710 may perform specific calculations or tasks. In an embodiment, the processor 1710 may be a microprocessor or a central processing unit ("CPU"), etc. The processor 1710 may be coupled to other components via an address bus, a control bus, or a data bus, etc. In an embodiment, the processor 1710 may be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus.

[0143] The memory device 1720 may store data used for the operation of the electronic device 1700. In an embodiment, the memory device 1720 may include a non-volatile memory device (such as an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, a ferroelectric random access memory ("FRAM") device, etc.) and / or a volatile memory device (such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a mobile DRAM device, etc.).

[0144] The storage device 1730 may include a solid state drive ("SSD") device, a hard disk drive ("HDD") device, or a compact disk read-only memory (CD-ROM) device, etc. The I / O device 1740 may include an input device such as a keyboard, a keypad, a touch pad, a touch screen, a mouse device, etc., and an output device such as a speaker, a printer, etc. The power supply 1750 may supply power required for the operation of the electronic device 1700. The display device 1760 may be coupled to other components via a bus or other communication link.

[0145] In the display device 1760, the second initialization level of the voltage of the sampling capacitor initialized in the second sub-sensing period may be different from the first initialization level of the voltage of the sampling capacitor initialized in the first sub-sensing period, so that the deviation between the first sensing data and the second sensing data can be reduced. Thus, the sensing accuracy of the sensing driver included in the display device 1760 can be improved.

[0146] The display device according to the embodiment can be applied to a display device included in a computer (such as a notebook computer), a mobile phone, a smart phone, a smart tablet, a portable media player (PMP), a personal digital assistant (PDA), or a Moving Picture Experts Group Audio Layer 3 (MP3) player, etc.

[0147] Although the sensing driver, the method of driving the sensing driver and the display device according to the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by an ordinary technician in the relevant technical field without departing from the technical spirit described in the appended claims.

Claims

1. A sensing driver that performs a sensing operation on a first sensing line and a second sensing line in a sensing period including a first sub-sensing period and a second sub-sensing period, wherein: The sensing driver comprises: a sensing channel that samples a first sensing voltage of the first sensing line in a first sampling period of the first sub-sensing period, samples a second sensing voltage of the second sensing line in a second sampling period of the second sub-sensing period, and includes a sampling capacitor having a first electrode and a second electrode; a first line selection switch that connects the first sensing line to the sensing channel in the first sub-sensing period; and a second line selection switch, connecting the second sensing line to the sensing channel in the second sub-sensing period, wherein, in a first capacitor initialization period of the first sub-sensing period, a voltage having a first initialization level is applied to the first electrode of the sampling capacitor, and Wherein, in a second capacitor initialization period of the second sub-sensing period, a voltage having a second initialization level different from the first initialization level is applied to the first electrode of the sampling capacitor.

2. The sensing driver according to claim 1, wherein: The second initialization level is higher than the first initialization level.

3. The sensing driver according to claim 1, wherein: Before the sensing period, the second initialization level is preset.

4. The sensing driver according to claim 1, wherein: The second initialization level is set based on the first sensing voltage and the second sensing voltage.

5. The sensing driver according to claim 1, wherein: The sensing channel also includes: a first sampling switch connecting the first line selection switch and the second line selection switch to the first electrode of the sampling capacitor in response to a sampling signal; a first reference switch, applying a reference voltage to the second electrode of the sampling capacitor in response to a reference signal; a first initialization voltage switch that applies an initialization voltage to the first intermediate node in response to a first capacitor initialization signal; and A first capacitor initialization switch connects the first intermediate node to the first electrode of the sampling capacitor in response to the reference signal.

6. The sensing driver according to claim 5, wherein: The sensing driver further includes: a reference channel, Wherein, the reference channel includes: a reference capacitor having a first electrode and a second electrode; a second sampling switch, applying the initialization voltage to the first electrode of the reference capacitor in response to the sampling signal; a second reference switch, applying the reference voltage to the second electrode of the reference capacitor in response to the reference signal; a second initialization voltage switch, applying the initialization voltage to a second intermediate node in response to the first capacitor initialization signal; and A second capacitor initialization switch connects the second intermediate node to the first electrode of the reference capacitor in response to the reference signal.

7. The sensing driver according to claim 6, wherein: The initialization voltage has a first voltage level in the first capacitor initialization period, and has a second voltage level different from the first voltage level in the second capacitor initialization period.

8. The sensing driver according to claim 6, wherein: The sensing channel further includes a first reference voltage switch that applies the reference voltage to the first intermediate node in response to a second capacitor initialization signal, and The reference channel further includes a second reference voltage switch, and the second reference voltage switch applies the reference voltage to the second intermediate node in response to the second capacitor initialization signal.

9. The sensing driver according to claim 8, wherein: The reference voltage has a third voltage level in the first capacitor initialization period, and has a fourth voltage level different from the third voltage level in the second capacitor initialization period.

10. The sensing driver according to claim 8, wherein: The sensing channel further includes a first external voltage switch that applies an external voltage to the first intermediate node in response to a third capacitor initialization signal, and The reference channel further includes a second external voltage switch, and the second external voltage switch applies the external voltage to the second intermediate node in response to the third capacitor initialization signal.

11. The sensing driver according to claim 10, wherein: The external voltage has a fifth voltage level in the first capacitor initialization period, and has a sixth voltage level different from the fifth voltage level in the second capacitor initialization period.

12. The sensing driver according to claim 1, wherein: The sensing driver further comprises: The sensing line initialization circuit initializes the first sensing line and the second sensing line simultaneously in the first sub-sensing period.

13. The sensing driver according to claim 1, wherein: The sensing driver further comprises: analog-to-digital converters; and A switch matrix connects the sensing channels to the analog-to-digital converter.

14. The sensing driver according to claim 1, wherein: The sensing period includes: the first sub-sensing period, in which a first sensing operation is performed on the first sensing line; the second sub-sensing period, in which a second sensing operation is performed on the second sensing line; and a data output period in which first sensing data corresponding to the first sensing voltage and second sensing data corresponding to the second sensing voltage are output, The first sub-sensing period includes: a sensing line initialization period, in which the first sensing line and the second sensing line are initialized simultaneously; the first capacitor initialization period, during which the sampling capacitor is initialized; the first sampling period, during which the first sensing voltage is sampled; and a first analog-to-digital conversion period, in which the first sensing voltage is converted into the first sensing data, The second sub-sensing period includes: the second capacitor initialization period, during which the sampling capacitor is initialized; the second sampling period, during which the second sensing voltage is sampled; and A second analog-to-digital conversion period, in which the second sensing voltage is converted into the second sensing data.

15. The sensing driver according to claim 1, wherein: The sensing driver performs a sensing operation on N odd-numbered sensing lines including the first sensing line and N even-numbered sensing lines including the second sensing line in the sensing period, wherein N is a natural number greater than or equal to 2, Wherein, the sensing driver comprises: N sensing channels, including the sensing channel; N first line selection switches, including the first line selection switch, the N first line selection switches connecting the N odd-numbered sensing lines to the N sensing channels in the first sub-sensing period; N second line selection switches, including the second line selection switch, the N second line selection switches connecting the N even-numbered sensing lines to the N sensing channels in the second sub-sensing period; analog-to-digital converters; and a switch matrix that sequentially connects the N sensing channels to the analog-to-digital converter in a first analog-to-digital conversion period of the first sub-sensing period, and that sequentially connects the N sensing channels to the analog-to-digital converter in a second analog-to-digital conversion period of the second sub-sensing period, and The analog-to-digital converter sequentially converts the N first sensing voltages of the N odd sensing lines into N first sensing data in the first analog-to-digital conversion period, and sequentially converts the N second sensing voltages of the N even sensing lines into N second sensing data in the second analog-to-digital conversion period.

16. The sensing driver according to claim 15, wherein: The second initialization level is set to an average value of the N first sensing voltages and the N second sensing voltages.

17. The sensing driver according to claim 15, wherein: The sensing driver further comprises: A data output unit sequentially stores the N first sensing data in the first analog-to-digital conversion period, the data output unit sequentially stores the N second sensing data in the second analog-to-digital conversion period, and the data output unit outputs the N first sensing data and the N second sensing data in a data output period of the sensing period.

18. The sensing driver according to claim 17, wherein: The data output unit rearranges the N first sensing data and the N second sensing data such that each of the N second sensing data is disposed between two adjacent first sensing data of the N first sensing data.

19. A method of driving a sensing driver, the sensing driver performing a sensing operation on a first sensing line and a second sensing line in a sensing period including a first sub-sensing period and a second sub-sensing period, wherein: The method comprises: In the first sub-sensing period, connecting the first sensing line to a sensing channel; In a first capacitor initialization period of the first sub-sensing period, applying a voltage having a first initialization level to a first electrode of a sampling capacitor of the sensing channel; In a first sampling period of the first sub-sensing period, sampling a first sensing voltage of the first sensing line; applying a voltage having a second initialization level different from the first initialization level to the first electrode of the sampling capacitor in a second capacitor initialization period of the second sub-sensing period; In the second sub-sensing period, connecting the second sensing line to the sensing channel; and In a second sampling period of the second sub-sensing period, a second sensing voltage of the second sensing line is sampled.

20. The method according to claim 19, wherein: The second initialization level is higher than the first initialization level.

21. The method according to claim 19, wherein: Before the sensing period, the second initialization level is preset.

22. The method according to claim 19, wherein: The second initialization level is set based on the first sensing voltage and the second sensing voltage.

23. A display device, wherein: The display device comprises: A display panel including a first pixel and a second pixel; a scan driver providing a scan signal and a sensing signal to each of the first pixel and the second pixel; a data driver that provides a data signal to each of the first pixel and the second pixel; and a sensing driver that performs a sensing operation on a first sensing line connected to the first pixel and a second sensing line connected to the second pixel in a sensing period including a first sub-sensing period and a second sub-sensing period, Wherein, the sensing driver comprises: a sensing channel that samples a first sensing voltage of the first sensing line in a first sampling period of the first sub-sensing period, samples a second sensing voltage of the second sensing line in a second sampling period of the second sub-sensing period, and includes a sampling capacitor; a first line selection switch that connects the first sensing line to the sensing channel in the first sub-sensing period; and a second line selection switch, connecting the second sensing line to the sensing channel in the second sub-sensing period, wherein, in a first capacitor initialization period of the first sub-sensing period, a voltage having a first initialization level is applied to a first electrode of the sampling capacitor, and Wherein, in a second capacitor initialization period of the second sub-sensing period, a voltage having a second initialization level different from the first initialization level is applied to the first electrode of the sampling capacitor.

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