Gate driving circuit, driving method of display panel and display panel

Abstract

Embodiments of the present application provide a gate drive circuit, a driving method of a display panel and the display panel. The gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, each of which corresponds to control of a row of sub-pixels. Each gate drive sub-circuit comprises a pull-up module, a pull-down module and an output control module. The pull-up module controls the potential of the first node according to the first level signal and the clock signal. The pull-down module controls the potential of the first node according to the preset low potential and the second level signal. The output control module outputs the corresponding driving signal to the corresponding sub-pixel through the output port according to the control signal, the preset low potential and the potential of the first node. Through the above setting, at least the problem that the power consumption of the smart device with the high refresh rate display panel is high and the endurance is poor is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit, a driving method of a display panel and the display panel. BACKGROUND

[0002] At present, high refresh rate screens have become a standard configuration of medium and high-end intelligent devices, but high resolution and high refresh rate also bring high power consumption, resulting in high power consumption and poor endurance of intelligent devices with high refresh rate display panels. SUMMARY

[0003] Embodiments of the present application provide a gate driving circuit, a driving method of a display panel and the display panel to at least solve the problem of high power consumption and poor endurance of intelligent devices with high refresh rate display panels.

[0004] In one aspect, the embodiments of the present application provide a gate driving circuit, comprising a plurality of cascaded gate driving sub-circuits, each of which corresponds to control a row of sub-pixels, the Nth gate driving sub-circuit comprising: a pull-up module connected to a first level transmission signal and a clock signal, and connected to a first node, the pull-up module being configured to control the potential of the first node according to the first level transmission signal and the clock signal; wherein the first level transmission signal is a scanning signal output by the N-Kth gate driving sub-circuit, N>K>0; a pull-down module connected to a preset low potential and a second level transmission signal, and connected to the first node, the pull-down module being configured to control the potential of the first node according to the preset low potential and the second level transmission signal; wherein the second level transmission signal is a scanning signal output by the N+Mth gate driving sub-circuit, M>0; and an output control module connected to a control signal and the preset low potential, and connected to the first node and an output port, the output control module being configured to output a driving signal to the sub-pixel corresponding to the gate driving sub-circuit through the output port according to the control signal, the preset low potential and the potential of the first node.

[0005] In some embodiments, the output control module is further configured to control the output port to output a preset low potential to the pixel row corresponding to the gate driving sub-circuit when the control signal is a preset high potential, and to control the output port to output the potential of the first node to the pixel row corresponding to the gate driving sub-circuit when the control signal is a preset low potential.

[0006] In some embodiments, the output control module comprises: a first transistor comprising a control electrode connected to the first node, a first electrode connected to the first node, and a second electrode connected to a second node; a second transistor comprising a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the output port; a third transistor comprising a control electrode connected to the control signal, a first electrode connected to the second node, and a second electrode connected to the preset low potential; and a fourth transistor comprising a control electrode connected to the control signal, a first electrode connected to the output port, and a second electrode connected to the preset low potential.

[0007] In some embodiments, during a first time t1, the gate drive sub-circuits of the kth to mth stages are connected to the control signal of the first type, and the gate drive sub-circuits of the m+1th to nth stages are connected to the control signal of the first type; during a second time t2, the gate drive sub-circuits of the kth to mth stages are connected to the control signal of the first type, and the gate drive sub-circuits of the m+1th to nth stages are connected to the control signal of the second type; wherein n>m>k, t1>0, t2>0, one of the control signal of the first type and the control signal of the second type is a preset high potential, and the other is a preset low potential.

[0008] In some embodiments, during a first time t1, the gate drive sub-circuits of the n+1th to xth stages are connected to the control signal of the first type; during a second time t2, the gate drive sub-circuits of the n+1th to xth stages are connected to the control signal of the first type; wherein x>n.

[0009] In some embodiments, during a third time t3, the gate drive sub-circuits of the kth to mth stages are connected to the control signal of the first type, the gate drive sub-circuits of the m+1th to nth stages are connected to the control signal of the second type, and the gate drive sub-circuits of the n+1th to xth stages are connected to the control signal of the second type; wherein t3>0.

[0010] In another aspect, the embodiments of the present application also provide a driving method of a display panel, the display panel comprising a plurality of cascaded gate drive sub-circuits, each of the gate drive sub-circuits corresponding to control of a row of sub-pixels, the driving method of the display panel comprising: generating a potential of a first node according to a first stage transmission signal, a second stage transmission signal, a clock signal, and a preset low potential by the gate drive sub-circuit; and outputting a driving signal to a pixel row corresponding to the gate drive sub-circuit according to the potential of the first node and a control signal.

[0011] In some embodiments, the generating and outputting the driving signal to the pixel row corresponding to the gate drive sub-circuit according to the potential of the first node and the control signal comprises: outputting a preset low potential to the pixel row corresponding to the gate drive sub-circuit when the control signal is a preset high potential.

[0012] In some embodiments, the generating and outputting the driving signal to the pixel row corresponding to the gate drive sub-circuit according to the potential of the first node and the control signal comprises: outputting the potential of the first node to the pixel row corresponding to the gate drive sub-circuit when the control signal is a preset low potential.

[0013] In some embodiments, the outputting the driving signal to the pixel row corresponding to the gate drive sub-circuit according to the potential of the first node and the control signal comprises: inputting the control signal of the first type to the gate drive sub-circuit of the kth to mth stage and inputting the control signal of the first type to the gate drive sub-circuit of the m+1th to nth stage within a first time t1, so as to output the driving signal of the first type to the kth to nth row of pixels; inputting the control signal of the first type to the gate drive sub-circuit of the kth to mth stage within a second time t2, so as to output the driving signal of the first type to the kth to mth row of pixels; inputting the control signal of the second type to the gate drive sub-circuit of the m+1th to nth stage, so as to output the driving signal of the second type to the m+1th to nth row of pixels; wherein n>m>k, t1>0, t2>0, one of the control signal of the first type and the control signal of the second type is a preset high potential, and the other is a preset low potential.

[0014] In some embodiments, the inputting the control signal of the first type to the gate drive sub-circuit of the n+1th to xth stage within a first time t1, so as to output the driving signal of the first type to the n+1th to xth row of pixels; inputting the control signal of the first type to the gate drive sub-circuit of the n+1th to xth stage within a second time t2, so as to output the driving signal of the first type to the n+1th to xth row of pixels; wherein x>n.

[0015] In some embodiments, the inputting the control signal of the first type to the gate drive sub-circuit of the kth to mth stage within a third time t3, so as to output the driving signal of the first type to the kth to mth row of pixels; inputting the control signal of the second type to the gate drive sub-circuit of the m+1th to nth stage, so as to output the driving signal of the second type to the m+1th to nth row of pixels; and inputting the control signal of the second type to the gate drive sub-circuit of the n+1th to xth stage, so as to output the driving signal of the second type to the n+1th to xth row of pixels; wherein t3>0.

[0016] In another aspect, another embodiment of the present application also provides a display panel, comprising the gate drive circuit of any of the above embodiments.

[0017] The embodiments of the present application provide at least the following beneficial effects:

[0018] The embodiments of the present application provide a gate drive circuit, a driving method of a display panel and the display panel, wherein the gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, each of which corresponds to control a row of sub-pixels, and each of the gate drive sub-circuits comprises a pull-up module, a pull-down module and an output control module. The pull-up module controls the potential of the first node according to the first level signal and the clock signal; the pull-down module controls the potential of the first node according to the preset low potential and the second level signal; and the output control module outputs the corresponding driving signal to the corresponding pixel row through the output port according to the control signal, the preset low potential and the potential of the first node. Through the above setting, the output control module can selectively output the valid gate control signal or the invalid gate control signal for a certain row of pixels, so as to control different display areas of the same display panel to have different refresh rates. For the display row which does not need high refresh rate, the refresh rate of the corresponding display row can be reduced by outputting the invalid gate control signal, thereby at least solving the problem that the intelligent device with a high refresh rate display panel has high power consumption and poor endurance, and further effectively reducing the power consumption of the display panel and prolonging the endurance of the intelligent device.

[0019] Other beneficial effects of the embodiments of the present application will be further described in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a structural schematic diagram of a gate drive circuit provided in some embodiments of the present application;

[0021] Figure 2 is a structural schematic diagram of a gate drive sub-circuit provided in some embodiments of the present application;

[0022] Figure 3 is a structural schematic diagram of another gate drive sub-circuit provided in some embodiments of the present application;

[0023] Figure 4 is a structural schematic diagram of another gate drive sub-circuit provided in some embodiments of the present application;

[0024] Figure 5 is a partitioning schematic diagram of a display panel provided in some embodiments of the present application;

[0025] Figure 6 is a timing schematic diagram of a control signal provided in some embodiments of the present application;

[0026] Figure 7 is a partitioned schematic diagram of still another display panel provided in some embodiments of the present application;

[0027] Figure 8 is a timing schematic diagram of still another control signal provided in some embodiments of the present application;

[0028] Figure 9 is a timing schematic diagram of still another control signal provided in some embodiments of the present application;

[0029] Figure 10 is a flowchart of a driving method of a display panel provided in some embodiments of the present application;

[0030] Figure 11 is a structural schematic diagram of a display panel provided in some embodiments of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and describe the ideas of the present application, and should not be regarded as a limitation on the protection scope of the present application.

[0032] In addition, the terms "first", "second" are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0033] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium; can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0034] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For purposes of explanation and ease of understanding, specific examples of components and arrangements are described in the following disclosure. Of course, they are merely examples and are not intended to limit the present application. Also, the present application can refer to a number of items by reference to a drawing figure, in which the articles are not necessarily drawn to scale. The same reference numerals in different figures identifying the same or similar elements do not necessarily indicate similar items on later drawings. In addition, various specific processes and materials are described in the following disclosure, but the present application can be practiced using other processes and / or materials as would be understood by one of ordinary skill in the art.

[0035] In describing some embodiments, the use of "coupled" and "connected", and variations thereof, is intended to mean that two or more components are in direct physical or electrical contact with one another, for example. In some embodiments, the use of "coupled" or "connected" can also mean that two or more components are not in direct physical or electrical contact with one another, but yet still cooperate or interact with one another. The embodiments disclosed herein are not necessarily limited in scope by the embodiments of the application described herein.

[0036] The various embodiments provided by the present application are similar, and features in different embodiments can be combined with each other.

[0037] The use of "configured to" in the embodiments of the present application means open and inclusive language that does not exclude devices that are adapted to perform additional tasks or steps.

[0038] The order of the following description of the embodiments is not intended to limit the preferred order of the embodiments.

[0039] To solve the problem of high power consumption and poor endurance of smart devices with high refresh rate display panels, one embodiment of the present application provides a gate drive circuit including a plurality of cascaded gate drive sub-circuits. For simplicity of description, the same mark is used to describe the following signal ports and the corresponding received or transmitted signals, for example, the clock signal port and the clock signal are represented by CK, the first node and the first node potential are represented by G(N), and the output port and the output driving signal are represented by G(N)-AA.

[0040] Figure 1 A structural schematic diagram of a gate drive circuit provided in some embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, the gate drive circuit includes a plurality of cascaded gate drive sub-circuits. The gate drive circuit is configured to receive a clock signal CK, a gate drive signal G(N)-AA, and a gate drive signal G(N)-BB, and output a gate drive signal G(N)-CC. Figure 1As shown, the embodiment of the present application provides a gate drive circuit GM, the gate drive circuit GM includes a plurality of cascaded gate drive sub-circuits GA and a frequency division control line CL transmitting control signals Ctr to the plurality of gate drive sub-circuits GA, the plurality of gate drive sub-circuits GA are electrically connected with a plurality of clock lines CKL1-CKL8, the plurality of gate drive sub-circuits GA are configured to output a scanning signal Nscan to a corresponding pixel row as a gate drive signal, and output to an input end STV of a corresponding gate drive sub-circuit as an input signal or to a pull-down signal control end PD of a corresponding gate drive sub-circuit as a pull-down control signal. For example Figure 1 As shown, the scanning signal Nscan 1 output by the first-stage gate drive sub-circuit is the input signal of the fifth-stage gate drive sub-circuit GA, and the scanning signal Nscan 5 output by the fifth-stage gate drive sub-circuit GA is the pull-down control signal of the first-stage gate drive sub-circuit. Figure 1 The input signal of the Nth-stage gate drive sub-circuit shown in the figure is the scanning signal output by the N-4th-stage gate drive sub-circuit, therefore, the input signals of the first four-stage gate drive sub-circuits are frame start signals stv.

[0041] It should be noted that, Figure 1 As shown in the figure, one frequency division control line CL is connected to the plurality of gate drive sub-circuits GA, which is an exemplary display. In actual application, since the potentials of the control signals Ctr accessed by different gate drive sub-circuits are different, therefore, each stage of gate drive sub-circuit can be connected with an independent frequency division control line CL to obtain an independent control signal Ctr, so as to control the refresh frequency of each pixel row. It can also be that according to different refresh frequencies, the partitions of the display screen are set, for example, 1 to 100 rows share the same frequency division control line CL1, 101 to 1100 rows share the same frequency division control line CL2, and 1101 to 1200 rows share the same frequency division control line CL3. Each stage of gate drive sub-circuit is connected with an independent frequency division control line CL, which can more flexibly control the refresh frequency of each pixel row, and the partitions share a frequency division control line CL, which can effectively save the area of the non-display area of the panel.

[0042] Figure 2 A structural schematic diagram of a gate drive sub-circuit provided in some embodiments of the present application is shown. Referring to Figure 2 As shown, the Nth-stage gate drive sub-circuit GA is taken as an example for exemplary description. The gate drive sub-circuit GA includes a pull-up module 1211, a pull-down module 1212 and an output control module 1213.

[0043] The pull-up module 1211 is connected to the first-stage transmission signal G(N-K) and the CK clock signal, and is connected to the first node G(N). The pull-up module 1211 is configured to control the potential of the first node according to the first-stage transmission signal G(N-K) and the preset high potential CK. The first-stage transmission signal G(N-K) is from an N-Kth gate driving sub-circuit, and N>K>0.

[0044] The pull-down module 1212 is connected to the preset low potential VSS and the second-stage transmission signal G(N+M), and is connected to the first node G(N). The pull-down module 1212 is configured to control the potential of the first node G(N) according to the preset low potential VSS and the second-stage transmission signal G(N+M). The second-stage transmission signal G(N+M) is from an N+Mth gate driving sub-circuit, and M>0.

[0045] The output control module 1213 is connected to the control signal Ctr and the preset low potential VSS, and is connected to the first node G(N) and the output port G(N)-AA. The output control module 1213 is configured to output a corresponding driving signal to a corresponding sub-pixel through the output port G(N)-AA according to the control signal Ctr, the preset low potential VSS, and the potential of the first node G(N).

[0046] Through the above setting, the output control module 1213 can selectively output an effective gate control signal or an ineffective gate control signal to a certain row or several rows of sub-pixels, so as to control different display areas of the same display panel to have different refresh rates, thereby at least solving the problem that the power consumption of the smart device with a high refresh rate display panel is high and the endurance is poor. Specifically, when the control signal Ctr is high, the output port G(N)-AA outputs the preset low potential VSS to the pixel row corresponding to the gate driving sub-circuit, and when the control signal Ctr is low, the output port G(N)-AA outputs the potential G(N) of the first node to the pixel row corresponding to the gate driving sub-circuit, so as to control different display areas of the same display panel to have different refresh rates. For display rows that do not need a high refresh rate, an ineffective gate control signal is outputted, so as to reduce the refresh rate of the corresponding display row, thereby effectively reducing the power consumption of the display panel and prolonging the endurance of the smart device.

[0047] It should be noted that the implementation of each unit and control switch in the gate driving circuit can be a single transistor, a combination of multiple transistors, a capacitor, or a combination of a transistor and a capacitor. The transistors used in all embodiments of the present application can be thin film transistors (TFT) or metal oxide semiconductors (MOS), or other devices with the same characteristics, which are not limited in the embodiments of the present application.

[0048] Exemplarily, the transistor can be a TFT. The TFT can be prepared by an a-Si process, an oxide semiconductor process, a low temperature poly-silicon (LTPS) process, or a high temperature poly-silicon (HTPS) process. Embodiments of the present application do not limit the type of the transistor.

[0049] Embodiments of the present application do not limit the type of the transistor. The transistor can be an N-type transistor or a P-type transistor, and can be an enhancement mode transistor or a depletion mode transistor. In embodiments of the present application, all the transistors are exemplarily taken as N-type transistors. The N-type transistor is turned on under the action of a high level voltage signal and is turned off under the action of a low level voltage signal, that is, the working voltage of the N-type transistor is a high level voltage and the turn-off voltage is a low level voltage.

[0050] In embodiments of the present application, the gate of the transistor is the control electrode, and in order to distinguish the two electrodes of the transistor other than the gate, one of the two electrodes is directly described as the first electrode and the other is directly described as the second electrode. At this time, the first electrode of the transistor can be one of the source and the drain of the transistor, and the second electrode can be the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure.

[0051] The capacitor in embodiments of the present application can be a capacitor device prepared separately by a process, for example, a capacitor device realized by preparing a special capacitor electrode. Each capacitor electrode (first electrode plate and second electrode plate) of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or realized by a transistor itself and other devices and lines, or realized by using a parasitic capacitor between lines of a circuit itself.

[0052] Each of the above transistors can further include at least one switch tube connected in parallel with each of the transistors. Embodiments of the present application are only exemplarily described for the pixel driving circuit and the gate driving circuit, and other structures having the same functions as the pixel driving circuit and the gate driving circuit will not be described one by one, but should all belong to the protection scope of the present application.

[0053] The "first node", "second node", etc. in embodiments of the present application do not represent actual components, but represent the convergence points of related electrical connections in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of related electrical connections in a circuit diagram.

[0054] Figure 3 FIG. 13 is a structural schematic diagram of another gate driving sub-circuit provided in some embodiments of the present application. Referring to FIG. 13, in some embodiments, the output control module 1213 is further configured to control the output port G(N)-AA to output a preset low potential to the pixel row corresponding to the gate driving sub-circuit GA when the control signal Ctr is a preset high potential, and control the output port G(N)-AA to output the potential G(N) of the first node to the pixel row corresponding to the gate driving sub-circuit GA when the control signal Ctr is a preset low potential. Figure 3

[0055] Continuing to refer to FIG. 12, in some embodiments, the output control module 1213 includes: a first transistor T1 including a control electrode connected to the first node G(N), a first electrode connected to the first node G(N), and a second electrode connected to the second node A; a second transistor T2 including a control electrode connected to the second node A, a first electrode connected to the first node G(N), and a second electrode connected to the output port G(N); a third transistor T3 including a control electrode connected to the control signal Ctr, a first electrode connected to the second node A, and a second electrode connected to a preset low potential VSS; and a fourth transistor T4 including a control electrode connected to the control signal Ctr, a first electrode connected to the output port G(N)-AA, and a second electrode connected to the preset low potential VSS. Figure 3

[0056] The gate driving sub-circuit provided in the embodiments of the present application is equivalent to determining whether to output the valid G(N) signal through the output control module 1213 before the gate control signal G(N) is output to the sub-pixel corresponding to the AA area. The control signal Ctr is connected to the gate driving sub-circuit GA through the frequency division signal line CL. The frequency division control line CL can be connected to the timing controller TCON or the system on chip SIC. By setting the control signal Ctr of a certain row or a few rows, whether the gate control signal input to the sub-pixel corresponding to the AA area is the valid G(N) signal can be controlled.

[0057] Continuing to refer to FIG. 12, in some embodiments, when the Ctr signal input in the gate driving sub-circuit of a certain row of sub-pixels is a low potential, the third transistor T3 and the fourth transistor T4 are closed, the low potential VSS cannot be transmitted to the output port G(N)-AA through the third transistor T3 or the fourth transistor T4, and the potential G(N) of the first node can be transmitted to the output port G(N)-AA, that is, the G(N)-AA signal received by the corresponding sub-pixel is consistent with the potential G(N) of the first node, and the sub-pixel performs refresh of the data signal. Figure 3

[0058] ​​​When the Ctr signal input in the gate driving sub-circuit of a row of sub-pixels is high, the third transistor T3 and the fourth transistor T4 are turned on, and the low potential VSS can be transmitted to the output port G(N)-AA through the third transistor T3 or the fourth transistor T4, and the potential of the first node G(N) cannot be normally transmitted to the output port G(N)-AA, that is, the G(N)-AA signal received by the corresponding sub-pixel is a sustained low level, and the sub-pixel does not perform refresh of the data signal.

[0059] It should be noted that the pull-up module and the pull-down module can be realized by a conventional GOA (Gate-driver on array) circuit, for example, 7T2C, 9T2C or 13T2C, etc., which can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0060] Figure 4 A structure diagram of another gate driving sub-circuit provided in some embodiments of the present application is shown in FIG. 12B. As shown in FIG. 12B, the gate driving sub-circuit GA of the Nth stage includes a pull-up module 1211, a pull-down module 1212, an output control module 1213, an inverting module 1214, a pull-down maintaining module 1215, and two reset transistors T6 and T15. Figure 4

[0061] The pull-up module 1211 includes a fifth transistor T5 and a sixteenth transistor T16. The control electrode of the fifth transistor T5 is connected to the first stage transmission signal G(N-4) and the first electrode, and the second electrode is connected to the third node Q(N). The control electrode of the sixteenth transistor T16 is connected to the third node Q(N), the first electrode is connected to the clock signal CKN, and the second electrode is connected to the first node G(N). The pull-up module 1211 is used to turn on the sixteenth transistor T16 when the potential of the second node Q(N) is high, and output the high potential to the first node G(N) when the clock signal CKN is high.

[0062] The pull-down module 1212 includes a thirteenth transistor T13 and a fourteenth transistor T14. The control electrode of the thirteenth transistor T13 is connected to the second stage transmission signal G(N+6), the first electrode is connected to the third node Q(N), and the second electrode is connected to the preset low potential VSS. The control electrode of the fourteenth transistor T14 is connected to the third stage transmission signal G(N+4), the first electrode is connected to the first node G(N), and the second electrode is connected to the preset low potential VSS. The thirteenth transistor T13 is used to pull down the potential of the third node Q(N), and the fourteenth transistor T14 is used to pull down the potential of the first node G(N).

[0063] ​The inverting module 1214 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10. The control electrode of the seventh transistor T7 is connected to its first electrode and a preset high potential VGH, and the second electrode is connected to the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is connected to the third node Q(N), the first electrode is connected to the second electrode of the seventh transistor T7, and the second electrode is connected to a preset low potential VSS; the control electrode of the ninth transistor T9 is connected to the first electrode of the eighth transistor T8, the first electrode is connected to the first electrode of the seventh transistor T7, and the second electrode is connected to the fourth node P(N); the control electrode of the tenth transistor T10 is connected to the third node Q(N), the first electrode is connected to the fourth node P(N), and the second electrode is connected to the preset low potential VSS. The inverting module 1214 is used to invert the potentials of the fourth node P(N) and the third node Q(N).

[0064] The pull-down maintaining module 1215 includes an eleventh transistor T11 and a twelfth transistor T12. The control electrode of the eleventh transistor T11 is connected to the fourth node P(N), the first electrode is connected to the third node Q(N), and the second electrode is connected to the preset low potential VSS; the control electrode of the twelfth transistor T12 is connected to the fourth node P(N), the first electrode is connected to one end of the bootstrap capacitor C, and the second electrode is connected to the preset low potential VSS. The pull-down maintaining module 1215 is used to maintain the third node Q(N) and the voltage stability. The two ends of the bootstrap capacitor C are respectively connected to the third node Q(N) and the first node G(N), which are used to couple the voltage between the third node Q(N) and the first node G(N).

[0065] The sixth transistor T6 and the fifteenth transistor T15 are reset transistors. By connecting the reset signal, the potential of the third node Q(N) and the first node G(N) can be reset by one key.

[0066] In some embodiments, in the first time t1, the gate drive sub-circuits of the kth to mth stages are connected to the control signal of the first type, and the gate drive sub-circuits of the m+1th to nth stages are connected to the control signal of the first type; in the second time t2, the gate drive sub-circuits of the kth to mth stages are connected to the control signal of the first type, and the gate drive sub-circuits of the m+1th to nth stages are connected to the control signal of the second type; wherein n>m>k, t1>0, t2>0, one of the control signal of the first type and the control signal of the second type is a preset high potential, and the other is a preset low potential.

[0067] Figure 5 is a partitioned schematic diagram of a display panel provided in some embodiments of the present application, Figure 6 is a timing diagram of a control signal provided in some embodiments of the present application. Referring to Figure 5 and Figure 6As shown, the display area (AA) of the display panel can be divided into two display partitions with different refresh frequencies, for example, the first to 100th row of sub-pixels are a dynamic display area with a refresh frequency of 120HZ, and the 101st to 1200th row of sub-pixels are a static display area with a refresh frequency of 60HZ. The first to 100th gate driving sub-circuits are connected to a first control signal Ctr 1, and the 101st to 1200th gate driving sub-circuits are connected to a second control signal Ctr 2. In a first time t1, the first control signal Ctr 1 is at a low level, the gate driving sub-circuits of the first to 100th row output an effective G(N)-AA, and the second control signal Ctr 2 is at a low level, the gate driving sub-circuits of the 101st to 1200th row output an effective G(N)-AA; in a second time t2, the first control signal Ctr 1 is at a low level, the gate driving sub-circuits of the first to 100th row output an effective G(N)-AA, and the second control signal Ctr 2 is at a high level, the gate driving sub-circuits of the 101st to 1200th row output a preset low potential and do not perform data refresh.

[0068] In some embodiments, the first to 100th row of sub-pixels can also be a static display area with a refresh frequency of 30HZ, and the 101st to 1200th row of sub-pixels are a dynamic display area with a refresh frequency of 100HZ. The specific partition and corresponding refresh frequency can be set according to the actual application scenario, and the embodiments of the present application do not limit this.

[0069] In some embodiments, in the first time t1, the n+1th to xth gate driving sub-circuits are all connected to the control signal of the first type; in the second time t2, the n+1th to xth gate driving sub-circuits are all connected to the control signal of the first type; wherein x>n.

[0070] Figure 7 is another display panel partitioning schematic diagram provided in some embodiments of the present application, Figure 8 is another control signal timing diagram provided in some embodiments of the present application. Refer to Figure 7 and Figure 8As shown, the display area (AA) of the display panel can be divided into three display zones with different refresh rates. For example, rows 1 to 100 are dynamic display zones with a refresh rate of 120Hz, rows 101 to 1100 are static display zones with a refresh rate of 60Hz, and rows 1101 to 1200 are dynamic display zones with a refresh rate of 120Hz. The gate driver sub-circuits of levels 1 to 100 are connected to the first control signal Ctr 1, levels 101 to 1100 are connected to the second control signal Ctr 2, and levels 1101 to 1200 are connected to the third control signal Ctr 3. Within the first time interval t1, the first control signal Ctr1 is low, and the gate driver sub-circuits of levels 1 to 100 output valid G(N)-AA; the second control signal Ctr2 is low, and the gate driver sub-circuits of levels 101 to 1100 output valid G(N)-AA; the third control signal Ctr3 is low, and the gate driver sub-circuits of levels 1101 to 1200 output valid G(N)-AA; within the second time interval t2, the first control signal Ctr1 is low, and the gate driver sub-circuits of levels 1 to 100 output valid G(N)-AA; the second control signal Ctr2 is high, and the gate driver sub-circuits of levels 101 to 1200 output a preset low potential and do not perform data refresh; the third control signal Ctr1 is low, and the gate driver sub-circuits of levels 1 to 100 output valid G(N)-AA.

[0071] Figure 8 In the timing diagram shown, the refresh rate of sub-pixels in rows 1 to 100 is the same as the refresh rate of rows 1101 to 1200. The specific timing control of the control signals can be... Figure 8 Conversely, for example, rows 1 to 100 are static display areas with a refresh rate of 60Hz, rows 101 to 1100 are dynamic display areas with a refresh rate of 120Hz, and rows 1101 to 1200 are static display areas with a refresh rate of 60Hz. The corresponding first control signal Ctr 1 is low in the first time t1 and high in the second time t2. The second control signal Ctr 2 is low in both the first time t1 and the second time t2. The third control signal Ctr 3 is low in the first time t1 and high in the second time t2.

[0072] In some embodiments, during a third time t3, the gate driving sub-circuits of stages k to m are all connected to a first type of control signal, the gate driving sub-circuits of stages m+1 to n are all connected to a second type of control signal, and the gate driving sub-circuits of stages n+1 to x are all connected to the second type of control signal; wherein, t3 > 0.

[0073] Figure 9is another timing diagram of a control signal provided in some embodiments of the present application. Refer to Figure 9 As shown, the display panel can be divided into 3 partitions, and the refresh frequencies of the 3 partitions are different. The 1st to 100th gate drive sub-circuits are connected to the first control signal Ctr 1, the 101st to 1100th gate drive sub-circuits are connected to the second control signal Ctr 2, and the 1101st to 1200th gate drive sub-circuits are connected to the third control signal Ctr 3. In the first time t1, the second time t2, and the third time t3, the first control signal Ctr 1 is always low, and the 1st to 100th gate drive sub-circuits always output valid G(N)-AA. The second control signal Ctr 2 is low in the first time t1, and the 101st to 1100th gate drive sub-circuits output valid G(N)-AA. In the second time t2 and the third time t3, the second control signal Ctr 2 is high, and the 101st to 1200th gate drive sub-circuits output a preset low potential and do not perform data refresh. The third control signal Ctr 3 is low in the first time t1, and the 1101st to 1200th gate drive sub-circuits output valid G(N)-AA. In the second time t2, the third control signal Ctr 3 is high, and the 1101st to 1200th gate drive sub-circuits output a preset low potential and do not perform data refresh. In the third time t3, the third control signal Ctr 3 is low, and the 1101st to 1200th gate drive sub-circuits output valid G(N)-AA.

[0074] Figure 10 is a flowchart of a driving method of a display panel provided in some embodiments of the present application. Refer to Figure 10 As shown, another embodiment of the present application also provides a driving method of a display panel, which is realized by the gate drive circuit in any of the above embodiments, and the content has been described and will not be repeated here.

[0075] The driving method includes:

[0076] In step S1001, the gate drive sub-circuit generates the potential of the first node according to the first level signal, the second level signal, the clock signal, and the preset low potential.

[0077] In step S1002, the driving signal is output to the pixel row corresponding to the gate drive sub-circuit according to the potential of the first node and the control signal.

[0078] In some embodiments, the above step S1002 can be realized by the following steps:

[0079] In step S11, when the control signal is a preset high potential, a preset low potential is output to the pixel row corresponding to the gate drive sub-circuit.

[0080] In some embodiments, the above step S1002 can be realized by the following steps:

[0081] S21, when the control signal is a preset low potential, outputting the potential of the first node to the pixel row corresponding to the gate drive sub-circuit.

[0082] In some embodiments, the above step S1002 can be realized by the following steps:

[0083] In the first time t1, the first type of control signal is input to the kth to mth gate drive sub-circuit, and the first type of control signal is input to the m+1th to nth gate drive sub-circuit, so as to output the first type of drive signal to the kth to nth pixel row;

[0084] In the second time t2, the first type of control signal is input to the kth to mth gate drive sub-circuit, so as to output the first type of drive signal to the kth to mth pixel row; the second type of control signal is input to the m+1th to nth gate drive sub-circuit, so as to output the second type of drive signal to the m+1th to nth pixel row;

[0085] Wherein, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

[0086] In some embodiments, in the first time t1, the first type of control signal is input to the n+1th to xth gate drive sub-circuit, so as to output the first type of drive signal to the n+1th to xth pixel row; in the second time t2, the first type of control signal is input to the n+1th to xth gate drive sub-circuit, so as to output the first type of drive signal to the n+1th to xth pixel row; wherein, x>n.

[0087] In some embodiments, in the third time t3, the first type of control signal is input to the kth to mth gate drive sub-circuit, so as to output the first type of drive signal to the kth to mth pixel row; the second type of control signal is input to the m+1th to nth gate drive sub-circuit, so as to output the second type of drive signal to the m+1th to nth pixel row; and the second type of control signal is input to the n+1th to xth gate drive sub-circuit, so as to output the second type of drive signal to the n+1th to xth pixel row; wherein, t3>0.

[0088] By the above method, according to the potential of the first node and the control signal, the driving signal is output to the pixel row corresponding to the gate driving sub-circuit, whether the signal output by each stage of the gate driving sub-circuit is an effective scanning signal can be effectively controlled, the display panel is realized partition control, the refresh rate of part of the display area is reduced, at least the problem that the power consumption of the intelligent device with high refresh rate display panel is high and the endurance is poor is solved, so that different display areas of the same display panel have different refresh rates, and for the display row which does not need high refresh rate, the refresh rate of the corresponding display row can be reduced by outputting invalid gate control signal, thereby effectively reducing the power consumption of the display panel and prolonging the endurance of the intelligent device.

[0089] Figure 11 is a structural schematic diagram of a display panel provided in some embodiments of the present application. Referring to Figure 11 It is shown that another embodiment of the present application further provides a display panel 100, which includes the gate driving circuit GM described in any of the above embodiments. The display panel 100 includes an active display area AA and a non-display area NA located at the periphery of the AA, and the gate driving circuit GM is arranged in the non-display area NA, and the gate driving circuit GM receives a clock signal and a control signal from a timing controller TCON.

[0090] Another embodiment of the present application further provides a non-transitory computer readable storage medium having a computer program stored thereon, which is executed by a processor to implement the steps of the above-mentioned display panel driving method. The non-transitory computer readable storage medium has all the beneficial effects of the above-mentioned display panel driving method, which will not be repeated here.

[0091] The computer readable storage medium may, for example, be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any combination of the above, which is not specifically limited herein. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0092] In some embodiments of the present application, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0093] Computer program code for carrying out operations of some embodiments of the application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0094] The principles and implementation manners of the present application are described in the embodiments of the present application by using specific examples. The above description of the embodiments is only for the purpose of understanding the method of the present application and its core idea; meanwhile, for those skilled in the field, the specific implementation manners and application scopes can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

[0095] The above describes only specific implementation manners of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, each of the gate drive sub-circuits corresponds to control a row of sub-pixels, the Nth gate drive sub-circuit comprises: a pull-up module connected to the first level transmission signal and the clock signal and connected to the first node, the pull-up module is configured to control the potential of the first node according to the first level transmission signal and the clock signal; wherein the first level transmission signal is the scanning signal output by the N-Kth gate drive sub-circuit, N>K>0; a pull-down module connected to a preset low potential and a second level transmission signal and connected to the first node, the pull-down module is configured to control the potential of the first node according to the preset low potential and the second level transmission signal; wherein the second level transmission signal is the scanning signal output by the N+Mth gate drive sub-circuit, M>0; and an output control module connected to a control signal and the preset low potential and connected to the first node and an output port, the output control module is configured to output a driving signal to the pixel row corresponding to the gate drive sub-circuit through the output port according to the control signal, the preset low potential and the potential of the first node; wherein, in the first time t1, the kth to mth gate drive sub-circuit is connected to the first type of control signal, and the m+1th to nth gate drive sub-circuit is connected to the first type of control signal; in the second time t2, the kth to mth gate drive sub-circuit is connected to the first type of control signal, and the m+1th to nth gate drive sub-circuit is connected to the second type of control signal; wherein n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

2. The gate drive circuit according to claim 1, characterized by The output control module is further configured to: when the control signal is a preset high potential, control the output port to output a preset low potential to the pixel row corresponding to the gate drive sub-circuit, and when the control signal is a preset low potential, control the output port to output the potential of the first node to the pixel row corresponding to the gate drive sub-circuit.

3. The gate drive circuit according to claim 2, characterized by The output control module comprises: a first transistor comprising a control electrode connected to the first node, a first electrode connected to the first node, and a second electrode connected to a second node; a second transistor comprising a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the output port; a third transistor comprising a control electrode connected to the control signal, a first electrode connected to the second node, and a second electrode connected to the preset low potential; and a fourth transistor comprising a control electrode connected to the control signal, a first electrode connected to the output port, and a second electrode connected to the preset low potential.

4. The gate drive circuit of claim 1, wherein in the first time t1, the n+1th to xth gate drive sub-circuit is connected to the first type of control signal; In a second time t2, the gate drive sub-circuits of the n+1th to xth stages are connected to the first type of control signal; Wherein, x>n.

5. The gate drive circuit according to claim 4, characterized in that, In a third time t3, the gate drive sub-circuits of the kth to mth stages are connected to the first type of control signal, the gate drive sub-circuits of the m+1th to nth stages are connected to the second type of control signal, and the gate drive sub-circuits of the n+1th to xth stages are connected to the second type of control signal; Wherein, t3>0.

6. A driving method of a display panel, characterized by, The display panel comprises a plurality of cascaded gate drive sub-circuits, each of which corresponds to control a row of sub-pixels, and the driving method of the display panel comprises: The gate drive sub-circuit generates the potential of the first node according to the first stage transmission signal, the second stage transmission signal, the clock signal and the preset low potential; According to the potential of the first node and the control signal, a driving signal is output to the pixel row corresponding to the gate drive sub-circuit; Wherein, according to the potential of the first node and the control signal, a driving signal is output to the pixel row corresponding to the gate drive sub-circuit, comprising: In a first time t1, the gate drive sub-circuits of the kth to mth stages are input with the first type of control signal, and the gate drive sub-circuits of the m+1th to nth stages are input with the first type of control signal, so as to output the first type of driving signal to the kth to nth pixel row; In a second time t2, the gate drive sub-circuits of the kth to mth stages are input with the first type of control signal, so as to output the first type of driving signal to the kth to mth pixel row; the gate drive sub-circuits of the m+1th to nth stages are input with the second type of control signal, so as to output the second type of driving signal to the m+1th to nth pixel row; Wherein, n>m>k, t1>0, t2>0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

7. The driving method of the display panel according to claim 6, wherein According to the potential of the first node and the control signal, a driving signal is output to the pixel row corresponding to the gate drive sub-circuit, comprising: When the control signal is a preset high potential, a preset low potential is output to the pixel row corresponding to the gate drive sub-circuit.

8. The driving method of the display panel according to claim 6, wherein According to the potential of the first node and the control signal, a driving signal is output to the pixel row corresponding to the gate drive sub-circuit, comprising: When the control signal is a preset low potential, the potential of the first node is output to the pixel row corresponding to the gate drive sub-circuit.

9. The driving method of the display panel according to claim 6, wherein The method further comprises: In a first time t1, the gate drive sub-circuits of the n+1th to xth stages are input with the first type of control signal, so as to output the first type of driving signal to the n+1th to xth pixel row; In a second time t2, the gate drive sub-circuits of the n+1th to xth stages are input with the first type of control signal, so as to output the first type of driving signal to the n+1th to xth pixel row; Wherein, x>n.

10. The driving method of the display panel according to claim 9, wherein The method further comprises: In a third time t3, the control signal of the first type is input to the gate driving sub-circuit of the kth to mth stage to output the driving signal of the first type to the kth to mth row of pixel rows; the control signal of the second type is input to the gate driving sub-circuit of the m+1th to nth stage to output the driving signal of the second type to the m+1th to nth row of pixel rows; and the control signal of the second type is input to the gate driving sub-circuit of the n+1th to xth stage to output the driving signal of the second type to the n+1th to xth row of pixel rows. Wherein, t3>0.

11. A display panel, characterized by, The gate driving circuit comprises any one of claims 1 to 5.

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