Array substrate, display panel comprising array substrate and display device comprising array substrate

Abstract

The invention provides an array substrate, a display panel and a display device, the array substrate comprises a scanning circuit, the scanning circuit comprises a shift register unit, the shift register unit comprises a positive and negative scanning module, and the positive and negative scanning module comprises a first input unit, a second input unit, a third input unit and a fourth input unit; wherein the first input unit comprises a first transistor, the second input unit comprises a second transistor, the third input unit comprises a third transistor, the fourth input unit comprises a fourth transistor, a first electrode of the first transistor and a first electrode of the fourth transistor are connected with a first power supply end, and the first power supply end continuously provides low-level signals. The first electrodes of the second transistor and the third transistor are connected with a second power supply end, the second power supply end continuously provides high-level signals, the second electrodes of the first transistor, the second transistor, the third transistor and the fourth transistor are connected with a pull-up node, and the first transistor and the fourth transistor pull down the potential of the pull-up node. The first transistor, the second transistor, the third transistor and the fourth transistor pull up the potential of the pull-up node, and in the positive and negative scanning switching process, the effects of the first transistor, the second transistor, the third transistor and the fourth transistor are not changed, so that normal positive and negative scanning switching of the shift register unit can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] In the related art, a gate scanning circuit (GOA, Gate Driver On Array) includes a plurality of cascaded shift register units, and the driving output end of each shift register unit corresponds to a gate line respectively, so as to realize line-by-line scanning of the display panel. With the development of the technology of gate scanning circuits, it has been generally required that the gate scanning circuit can realize forward and reverse scanning functions.

[0003] However, after a long period of forward scanning or reverse scanning, some transistors in the shift register unit currently suitable for forward and reverse scanning may experience threshold drift, thereby causing the gate scanning circuit to fail to work normally when switching the scanning direction. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes an array substrate, a display panel and a display device to solve the problem of threshold drift of transistors in a forward and reverse scan shift register unit.

[0005] In one aspect, the present invention provides an array substrate, comprising: a scanning circuit, the scanning circuit comprising a multi-stage shift register unit, the shift register unit comprising at least a first input unit, a second input unit, a third input unit and a fourth input unit;

[0006] The control end of the first input unit is electrically connected to the first trigger end, the input end of the first input unit is electrically connected to the first power end, and the output end of the first input unit is electrically connected to the pull-up node, and is used to respond to the control of the first trigger end and adjust the potential of the pull-up node according to the first power signal provided by the first power end;

[0007] The control end of the second input unit is electrically connected to the second trigger end, the input end of the second input unit is electrically connected to the second power supply end, and the output end of the second input unit is electrically connected to the pull-up node, for responding to the control of the second trigger end and adjusting the potential of the pull-up node according to the second power supply signal provided by the second signal end;

[0008] The control end of the third input unit is electrically connected to the third trigger end, the input end of the third input unit is electrically connected to the second power supply end, and the output end of the third input unit is electrically connected to the pull-up node, and is used to respond to the control of the third trigger end and adjust the potential of the pull-up node according to the second power supply signal provided by the second power supply end;

[0009] The control end of the fourth input unit is electrically connected to the fourth trigger end, the input end of the fourth input unit is electrically connected to the first power end, and the output end of the fourth input unit is electrically connected to the pull-up node, and is used to respond to the control of the fourth trigger end and adjust the potential of the pull-up node according to the first power signal provided by the first power end;

[0010] The first power signal and the second power signal are electrically different.

[0011] On the other hand, based on the same inventive concept, the present invention provides an array substrate, the array substrate includes X-stage shift register units, each stage of the shift register unit includes a forward and reverse scan module, and the forward and reverse scan module includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0012] Wherein, the gate of the first transistor of the nth stage shift register unit is connected to the shift output terminal or trigger line of the n-2ith stage shift register unit, n≤X, i≥1, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode is connected to the pull-up node;

[0013] The gate of the second transistor of the nth stage shift register unit is connected to the shift output terminal or trigger line of the nith stage shift register unit, the first electrode of the second transistor is connected to the second power supply terminal, and the second stage is connected to the pull-up node;

[0014] The gate of the third transistor of the nth stage shift register unit is connected to the shift output terminal or the trigger line of the n+ith stage shift register unit, the first electrode of the third transistor is connected to the second power supply terminal, and the second electrode is connected to the pull-up node;

[0015] The gate of the fourth transistor of the nth shift register unit is connected to the shift output terminal or trigger line of the (n+2i)th shift register unit, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode is connected to the pull-up node.

[0016] On the other hand, based on the same inventive concept, the present invention provides a display panel including: the array substrate as described above.

[0017] On the other hand, based on the same inventive concept, the present invention provides a display device including: the display panel as described above.

[0018] In the present invention, the input end of the first input unit of each level of shift register unit is electrically connected to the first power supply end, the input end of the second input unit is electrically connected to the second power supply end, the input end of the third input unit is electrically connected to the second power supply end, the input end of the fourth input unit is electrically connected to the first power supply end, and the output ends of the first input unit, the second input unit, the third input unit and the fourth input unit are electrically connected to the pull-up node, that is, each level of shift register unit includes a forward and reverse scan module, the forward and reverse scan module includes a first transistor, a second transistor, a third transistor and a fourth transistor, the first electrode of the first transistor is connected to the first power supply end, the first electrode of the second transistor is connected to the second power supply end, the first electrode of the third transistor is connected to the second power supply end, the first electrode of the fourth transistor is connected to the first power supply end, and the second electrode of the first transistor, the second electrode of the second transistor, the second electrode of the third transistor and the second electrode of the fourth transistor are all connected to the pull-up node. In the process of forward and reverse scan switching, the first power supply end always provides the first power supply signal, and the second power supply end always provides the second power supply signal, so that normal forward and reverse scan switching can be achieved, which is conducive to improving the stability and reliability of the shift register unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0020] Figure 1 Schematic diagram of the circuit structure of a shift register unit in the related art;

[0021] Figure 2 is a schematic diagram of a current-gate-source voltage (I-Vgs) characteristic curve of a shift register unit in the related art;

[0022] Figure 3 A schematic diagram of the timing sequence of signals received by the forward and reverse scan input transistors in a shift register unit in the related art;

[0023] Figure 4 is a schematic diagram of an array substrate provided by an embodiment of the present invention;

[0024] Figure 5 is a schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0026] Figure 7 yes Figure 6The timing diagram of the shift register unit when performing forward scanning is shown;

[0027] Figure 8 yes Figure 6 The timing diagram of the shift register unit when performing reverse scanning is shown;

[0028] Fig. 9 is a schematic diagram of a scanning circuit provided by an embodiment of the present invention;

[0029] Fig.10 yes Fig. 9 The schematic diagram of the clock signal and trigger signal of the scanning circuit in the forward scanning mode shown;

[0030] Fig.11 yes Fig. 9 The schematic diagram of the clock signal and trigger signal of the scanning circuit in reverse scanning mode shown;

[0031] Fig.12 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention;

[0032] Fig.13 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention;

[0033] Fig.14 yes Fig.12 A schematic diagram of a clock signal and a trigger signal in a forward scanning mode of the scanning circuit shown;

[0034] Fig.15 yes Fig.12 A schematic diagram of a clock signal and a trigger signal of a reverse scanning mode of the scanning circuit shown;

[0035] Fig.16 yes Fig.13 A schematic diagram of a clock signal and a trigger signal in a forward scanning mode of the scanning circuit shown;

[0036] Fig.17 yes Fig.13 A schematic diagram of a clock signal and a trigger signal of a reverse scanning mode of the scanning circuit shown;

[0037] Fig.18 A schematic diagram of another scanning circuit provided by an embodiment of the present invention;

[0038] Fig.19 yes Fig.18 The schematic diagram of the clock signal and trigger signal of the scanning circuit in the forward scanning mode is shown;

[0039] Fig. 20 yes Fig.18 The schematic diagram of the clock signal and trigger signal of the scanning circuit in the reverse scanning mode is shown;

[0040] Fig.21 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention;

[0041] Fig. 22 yes Fig.21 The scanning circuit shown is a schematic diagram of a clock signal and a trigger signal in a forward scanning mode;

[0042] Fig.23 yes Fig.21 The scanning circuit shown is a schematic diagram of a clock signal and a trigger signal in a reverse scanning mode;

[0043] Fig.24 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, there is no difference between the source and drain. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the first pole and the other pole is called the second pole. The first pole and the second pole are only different in name and have no difference in essence. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are all explained by taking N-type transistors as an example. It can be imagined that when using P-type transistors for implementation, it is something that a technician in the field can easily think of without making creative work, so it is also within the scope of protection of the embodiments of the present invention.

[0046] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a shift register unit suitable for forward and reverse scanning in the related art, such as Figure 1The shift register unit includes: a forward scan input transistor T1, a reverse scan input transistor T2 and a first node N1. Taking the case where both the forward scan input transistor T1 and the reverse scan input transistor T2 are N-type transistors as an example, when performing forward scanning, the input terminal FW of the forward scan input transistor T1 continuously provides a high-level signal, and the input terminal BW of the reverse scan input transistor T2 continuously provides a low-level signal. INPUT1 and INPUT2 are respectively connected to the gate of the forward scan input transistor T1 and the gate of the reverse scan input transistor T2, and intermittently and continuously control the opening of the forward scan input transistor T1 and the reverse scan input transistor T2. During a long period of forward scanning, the forward scan input transistor T1 pulls up the potential of the first node N1, and the reverse scan input transistor T2 pulls down the potential of the first node N1. Since the gate-source voltage Vgs of the reverse scan input transistor T2 is greater than the threshold voltage of the reverse scan input transistor T2 for a long time, the current-gate-source voltage (I-Vgs) characteristic curve of the reverse scan input transistor T2 is generated as follows: Figure 2 As shown in the forward drift, the threshold voltage of the reverse scan input transistor T2 increases and the driving capability decreases. When the scanning direction is switched from forward scanning to reverse scanning, as shown in the forward drift, the threshold voltage of the reverse scan input transistor T2 increases and the driving capability decreases. Figure 3 As shown, the input terminal FW of the forward scan input transistor T1 changes to provide a low potential, the input terminal BW of the reverse scan input transistor T2 changes to provide a high potential, and the level signals provided by the input terminal FW of the forward scan input transistor T1 and the input terminal BW of the reverse scan input transistor T2 are switched with each other. Since the threshold voltage of the reverse scan input transistor T2 increases, the driving capability decreases, resulting in a decrease in the potential written into the first node N1, so the shift register unit cannot work normally.

[0047] Figure 4 is a schematic diagram of an array substrate provided by an embodiment of the present invention, Figure 5 is a schematic diagram of a shift register unit provided by an embodiment of the present invention. Figure 4 and Figure 5As shown, the array substrate includes a scanning circuit 100, the scanning circuit includes an X-stage shift register unit 101, and the shift register unit includes at least a first input unit 111, a second input unit 112, a third input unit 113 and a fourth input unit 114; the control end of the first input unit 111 is electrically connected to the first trigger end IN1, the input end of the first input unit 111 is electrically connected to the first power supply end PW1, and the output end of the first input unit 111 is electrically connected to the pull-up node PU, which is used to respond to the control of the first trigger end IN1 and adjust the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1; the control end of the second input unit 112 is electrically connected to the second trigger end IN2, the input end of the second input unit 112 is electrically connected to the second power supply end PW2, and the output end of the second input unit 112 is electrically connected to the pull-up node PU, which is used to respond to the control of the second trigger end IN1 and adjust the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1. The control end of the third input unit 113 is electrically connected to the third trigger end IN3, the input end of the third input unit 113 is electrically connected to the second power supply end PW2, and the output end of the third input unit 113 is electrically connected to the pull-up node PU, which is used to respond to the control of the third trigger end IN3 and adjust the potential of the pull-up node PU according to the second power supply signal VGH provided by the second power supply end PW2; the control end of the fourth input unit 114 is electrically connected to the fourth trigger end IN4, the input end of the fourth input unit 114 is electrically connected to the first power supply end PW1, and the output end of the fourth input unit 114 is electrically connected to the pull-up node PU, which is used to respond to the control of the fourth trigger end IN4 and adjust the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1. The electrical properties of the first power supply signal VGL and the second power supply signal VGH are different. In this embodiment, the first power supply signal VGL can turn off the N-type transistor, and the second power supply signal VGH can turn on the N-type transistor.

[0048] In this embodiment, the array substrate includes a display 201 and a non-display area 202. The display area 201 includes a plurality of sub-pixels 203, and the plurality of sub-pixels 203 are arranged in an array. The plurality of sub-pixels 203 are arranged along a first direction F1 to form a row of sub-pixels 203, and the plurality of sub-pixels 203 are arranged along a second direction F2 to form a column of sub-pixels 203, and the first direction F1 and the second direction F2 intersect; wherein, the arrangement of pixels in the display area 201 may also be other arrangement modes, not limited to array arrangement. The non-display area 202 includes a driving structure for the sub-pixels 203 in the display area 201 to display, and specifically, the non-display area 202 includes at least a scanning circuit 100, and the scanning circuit 100 is used to drive the sub-pixels 203 in the display area to display. Optionally, the sub-pixels in the display area 201 can be liquid crystal display units, organic light-emitting display units, or micro light-emitting diode display units, without specific restrictions. The scanning circuit 100 in the non-display area 202 is a gate scanning circuit, which is used to control the sub-pixels 203 in the display area 201 to perform row-by-row scanning.

[0049] The scanning circuit 100 includes a multi-stage shift register unit 101. The shift register unit 101 includes a driving output terminal Gout, and a stage of the shift register unit 101 is electrically connected to one or more rows of sub-pixels 203 through the driving output terminal Gout. The shift register unit 101 provides a gate driving signal to the electrically connected sub-pixels 203 through the driving output terminal Gout, so as to drive the sub-pixels 203 to work. Figure 4 In the embodiment, the shift register unit 101 can be selected to be electrically connected to a row of sub-pixels 203, and the shift register unit 101 provides a gate drive signal to the corresponding row of sub-pixels 203; however, in other embodiments, a first-level shift register unit can be selected to be electrically connected to multiple rows of sub-pixels, and the first-level shift register unit provides gate drive signals to multiple rows of sub-pixels simultaneously or in a time-sharing manner.

[0050] In this embodiment, the shift register unit 101 includes a first input unit 111, a control end of the first input unit 111 is electrically connected to a first trigger end IN1, an input end of the first input unit 111 is connected to a first signal end PW1, and an output end of the first input unit is connected to a pull-up node PU. Specifically, the electrical signal provided by the first trigger end IN1 is a signal of high-low level jump, thereby controlling the on-off state of the first input unit 111. It can be understood that the present invention is described with the transistor in the shift register unit 101 as an N-type transistor, therefore, a high-level signal can turn on the first input unit 111, and a low-level signal can turn off the first input unit 111; if the first trigger end IN1 provides a high-level signal, then the first power supply signal VGL provided by the first signal end PW1 is written into the pull-up node PU, and if the first trigger end IN1 provides a low-level signal, then the first input unit 111 is switched to an off state, and the transmission path between the first signal end PW1 and the pull-up node PU is disconnected. Therefore, the first input unit 111 adjusts the potential of the pull-up node PU according to the first power signal VGL provided by the first power terminal PW1 in response to the control of the first trigger terminal N1.

[0051] The shift register unit 101 includes a second input unit 112, a control end of the second input unit 112 is electrically connected to the second trigger end IN2, an input end of the second input unit 112 is connected to the second signal end PW2, and an output end of the second input unit is connected to the pull-up node PU. Specifically, the electrical signal provided by the second trigger end IN2 is a signal of high-low level jump, thereby controlling the on-off state of the second input unit 112. It can be understood that the present invention is described as an N-type transistor in the shift register unit 101, so a high-level signal can turn on the second input unit 112, and a low-level signal can turn off the second input unit 112. If the second trigger end IN2 provides a high-level signal, the second power supply signal VGH provided by the second signal end PW2 is written into the pull-up node PU; if the second trigger end IN2 provides a low-level signal, the second input unit 112 is switched to the off state, and the transmission path between the second signal end PW2 and the pull-up node PU is disconnected. Therefore, the second input unit 112 adjusts the potential of the pull-up node PU according to the second power signal VGH provided by the second power terminal PW2 in response to the control of the second trigger terminal IN2.

[0052] The shift register unit 101 includes a third input unit 113, a control end of the third input unit 113 is electrically connected to a third trigger end IN3, an input end of the third input unit 113 is connected to a second signal end PW2, and an output end of the third input unit is connected to a pull-up node PU. Specifically, the electrical signal provided by the third trigger end IN3 is a signal of high-low level jump, thereby controlling the on-off state of the third input unit 113. It can be understood that the present invention is described with the transistor in the shift register unit 101 as an N-type transistor, therefore, a high-level signal can turn on the third input unit 113, and a low-level signal can turn off the third input unit 113. If the third trigger end IN3 provides a high-level signal, the second power supply signal VGH provided by the second signal end PW2 is written into the pull-up node PU; if the third trigger end IN3 provides a low-level signal, the third input unit 113 is switched to an off state, and the transmission path between the second signal end PW2 and the pull-up node PU is disconnected. Therefore, the third input unit 113 adjusts the potential of the pull-up node PU according to the second power signal VGH provided by the second power terminal PW2 in response to the control of the third trigger terminal IN3.

[0053] The shift register unit 101 includes a fourth input unit 114, a control end of the fourth input unit 114 is electrically connected to a fourth trigger end IN4, an input end of the fourth input unit 114 is connected to the first signal end PW1, and an output end of the fourth input unit 114 is connected to the pull-up node PU. Specifically, the electrical signal provided by the fourth trigger end IN4 is a signal of high-low level jump, thereby controlling the on-off state of the fourth input unit 114. It can be understood that the present invention is described as an N-type transistor in the shift register unit 101, so a high-level signal can turn on the fourth input unit 114, and a low-level signal can turn off the fourth input unit 114. If the fourth trigger end IN1 provides a high-level signal, the first power supply signal VGL provided by the first signal end PW1 is written into the pull-up node PU; if the fourth trigger end IN4 provides a low-level signal, the fourth input unit 114 is switched to an off state, and the transmission path between the first signal end PW1 and the pull-up node PU is disconnected. Therefore, the fourth input unit 114 adjusts the potential of the pull-up node PU according to the first power signal VGL provided by the first power terminal PW1 in response to the control of the fourth trigger terminal IN4 .

[0054] In this embodiment, the input end of the first input unit 111 of the shift register unit 101 is electrically connected to the first power supply end PW1, the input end of the second input unit 112 is electrically connected to the second power supply end PW2, the input end of the third input unit 113 is electrically connected to the second power supply end PW2, and the input end of the fourth input unit 114 is electrically connected to the first power supply end PW1, and the output ends of the first input unit 111, the second input unit 112, the third input unit 113 and the fourth unit 114 are electrically connected to the pull-up node PU; regardless of the forward scanning mode or the reverse scanning mode, the first input unit 111 and the fourth unit 114 pull down the potential of the pull-up node PU, and the second input unit 112 and the third input unit 113 pull up the potential of the pull-up node, and the potential of the input ends of the first input unit 111 to the fourth unit 114 do not need to jump high and low during the switching process of the forward and reverse scanning modes as in the prior art, therefore, the reverse scanning mode can be switched normally after a long period of the forward scanning mode or the forward scanning mode can be switched normally after a long period of the reverse scanning mode.

[0055] The optional shift register unit 101 further includes an output unit 115, a control end of the output unit 115 is electrically connected to the pull-up node PU, an input end of the output unit 115 is electrically connected to the first signal end SG1, and an output end of the output unit 115 is electrically connected to the driving output end Gout. Specifically, the potential of the pull-up node PU is controlled by the first input unit 111, the second input unit 112, the third input unit 113, and the fourth input unit 114 to cause a high-low level jump, thereby controlling the on-off state of the output unit 115. In the embodiment of the present invention, the first signal provided by the first signal end SG1 may be a clock signal, which is marked as the first clock signal CK1. It can be understood that if the potential of the pull-up node PU is a high-level potential, the first output unit 115 is controlled to switch to the on state, and the first clock CK1 signal provided by the first signal end SG1 is written to the driving output end Gout. If the potential of the pull-up node PU is a low-level potential, the first output unit 115 is controlled to switch to the off state, and the transmission path between the first signal end SG1 and the driving output end Gout is disconnected. Therefore, the output unit 115 is used to respond to the control of the pull-up node PU and adjust the signal of the driving output terminal Gout according to the first signal provided by the first signal terminal SG1.

[0056] The optional shift register unit further includes a first reset unit 116, a control end of the first reset unit 116 is electrically connected to the second signal end SG2, an input end of the first reset unit 116 is electrically connected to the first power supply end PW1, and an output end of the first reset unit 116 is electrically connected to the drive output end Gout, and is used to respond to the control of the second signal provided by the second signal end SG2, and adjust the signal of the drive output end Gout according to the first power supply signal VGL provided by the first power supply end PW1. Specifically, the second signal provided by the second signal end SG2 can be a clock signal, marked as the second clock signal CK2, and the second clock signal CK2 can control the on-off state of the first reset unit 116. It can be understood that if the potential of the second clock signal CK2 is a high-level potential, the first reset unit 116 is controlled to switch to the on state, and the first power supply signal VGL provided by the first power supply end PW1 is written to the drive output end Gout. If the potential of the second clock signal CK2 is a low-level potential, the first reset unit 116 is controlled to switch to the off state, and the transmission path between the first power supply end PW1 and the drive output end Gout is disconnected. Therefore, the first reset unit 116 is used for responding to the control of the second signal terminal SG2 and adjusting the signal of the driving output terminal Gout according to the first power signal VGL provided by the first power terminal PW1.

[0057] The optional shift register unit further includes: a second reset unit 117, a third reset unit 118 and a node control unit 119;

[0058] The control end of the second reset unit 117 is electrically connected to the third signal end Reset, the input end of the second reset unit 117 is electrically connected to the first power supply end PW1, and the output end of the second reset unit 117 is electrically connected to the pull-up node PU, and is used to respond to the control of the third signal end Reset, and adjust the potential of the pull-up node PU according to the first power supply signal VGL provided by the first power supply end PW1. Specifically, the electrical signal provided by the third signal end Reset is a signal of high-low level jump, thereby controlling the on-off state of the second reset unit 117. It can be understood that if the level signal potential provided by the third signal end Reset is a high level potential, the second reset unit 117 is controlled to switch to the on state, and the first power supply signal VGL provided by the first power supply end PW1 is written into the pull-up node PU. If the level signal potential provided by the third signal end Reset is a low level potential, the second reset unit 117 is controlled to switch to the off state, and the transmission path between the first power supply end PW1 and the pull-up node PU is disconnected. Therefore, the second reset unit 117 is used to respond to the control of the third signal terminal Reset and adjust the potential of the pull-up node PU according to the first power signal VGL provided by the first power terminal PW1;

[0059] The control end of the third reset unit 118 is electrically connected to the fourth signal end Goff, the input end of the third reset unit 118 is connected to the first power supply end PW1, and the output end of the third output unit 118 is electrically connected to the driving output end Gout, and is used to respond to the control of the fourth signal end Goff, and adjust the signal of the driving output end Gout according to the first power supply signal VGL provided by the first power supply end PW1. Specifically, the electrical signal provided by the fourth signal end Goff is a signal of high-low level jump, thereby controlling the on-off state of the third reset unit 118. It can be understood that if the level signal potential provided by the fourth signal end Reset is a high level potential, the third reset unit 118 is controlled to switch to the on state, and the first power supply signal VGL provided by the first power supply end PW1 is written to the driving output end Gout. If the level signal potential provided by the fourth signal end Goff is a low level potential, the third reset unit 118 is controlled to switch to the off state, and the transmission path between the first power supply end PW1 and the driving output end Gout is disconnected. Therefore, the third reset unit 118 is used to respond to the control of the fourth signal terminal Goff and adjust the signal of the driving output terminal Gout according to the first power signal VGL provided by the first power terminal PW1;

[0060] The control end of the node control unit 119 is electrically connected to the pull-up node PU and the pull-down node PD, the input end of the node control unit 119 is electrically connected to the first power supply terminal PW1, and the output end of the node control unit 119 is electrically connected to the pull-up node PU, the pull-down node PD and the driving output terminal Gout, and is used to respond to the control of the pull-up node PU or the pull-down node PD, and adjust the signals of the pull-up node PU, the pull-down node PD and the driving output terminal according to the first power supply signal VGL provided by the first power supply terminal PW1. Specifically, at least one control terminal of the node control unit 119 is electrically connected to the pull-up node PU, and at least one control terminal is electrically connected to the pull-down node PD. The signals of the pull-up node PU and the pull-down node PD will undergo high-low level jumps. If the potential of the pull-up node PU is a high level potential, the first power signal VGL provided by the first power terminal PW1 is written into the pull-down node PD. If the potential of the pull-up node PU is a low level potential, the transmission path between the first power terminal PW1 and the pull-down node PD is disconnected; if the potential of the pull-down node PD is a high level potential, the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU and the driving output terminal Gout. If the potential of the pull-down node PD is a low level potential, the transmission paths between the first power terminal PW1 and the pull-up node PU and between the first power terminal PW1 and the driving output terminal Gout are all disconnected. Therefore, the node control unit 119 is used to respond to the control of the pull-up node PU or the pull-down node PD, and adjust the signals of the pull-up node PU, the pull-down node PD and the driving output terminal Gout according to the first power signal VGL provided by the first power terminal PW1.

[0061] In this embodiment, the scanning circuit 100 can realize the forward and reverse scanning functions. In the forward scanning mode or the reverse scanning mode, the input end of the first input unit 111 provides the first power signal VGL, the input end of the second input unit 112 provides the second power signal VGH, the input end of the third input unit 113 provides the second power signal VGH, and the input end of the fourth input unit 114 provides the first power signal VGL. The first input unit 111 and the fourth input unit 114 pull down the potential of the pull-up node PU, and the second input unit 112 and the third input unit 113 pull up the potential of the pull-up node PU. Compared with the prior art, After the scanning direction is switched, the functions of the first input unit 111, the second input unit 112, the third input unit 113 and the fourth input unit 114 do not change, that is, the power supply signals provided by the input ends of the first input unit 111, the second input unit 112, the third input unit 113 and the fourth input unit 114 do not change, even if the threshold voltages of the transistors in the first input unit 111 and the fourth input unit 114 become larger, but because there is no need to switch the pull-up action, the driving capability will not be reduced, and the potential written to the pull-up node PU will not be reduced, thereby ensuring that the shift register unit 101 can operate normally.

[0062] Figure 6 6, the optional shift register unit 101 includes a forward and reverse scanning module S, and the forward and reverse scanning module S includes a first input unit 111, a second input unit 112, a third input unit 113 and a fourth input unit 114;

[0063] The first input unit 111 includes a first transistor M1, the gate of the first transistor M1 is connected to the first trigger terminal IN1, the first transistor M1 is connected between the first power supply terminal PW1 and the pull-up node PU, the first stage of the first transistor M1 is connected to the first power supply terminal PW1, and the second electrode of the first transistor M1 is connected to the pull-up node PU; the second input unit 112 includes a second transistor M2, the gate of the second transistor M2 is connected to the second trigger terminal IN2, the second transistor M2 is connected between the second power supply terminal PW2 and the pull-up node PU, the first stage of the second transistor M2 is connected to the second power supply terminal PW2, and the second electrode of the second transistor M2 is connected to the pull-up node PU; The third input unit 113 includes a third transistor M3, the gate of the third transistor M3 is connected to the third trigger terminal IN3, the third transistor M3 is connected between the second power supply terminal PW2 and the pull-up node PU, the first stage of the third transistor M3 is connected to the second power supply terminal PW2, and the second electrode of the third transistor M3 is connected to the pull-up node PU; the fourth input unit 114 includes a fourth transistor M4, the gate of the fourth input transistor M4 is connected to the fourth trigger terminal IN4, the fourth transistor M4 is connected between the first power supply terminal PW1 and the pull-up node PU, the first stage of the fourth transistor M4 is connected to the first power supply terminal PW1, and the second electrode of the fourth transistor M4 is connected to the pull-up node PU.

[0064] The optional output unit 115 includes a fifth transistor M5, a gate of the fifth transistor M5 is connected to the pull-up node PU, the fifth transistor M5 is connected between the first signal terminal SG1 and the driving output terminal Gout, the first electrode of the fifth transistor M5 is connected to the first signal terminal SG1, and the second electrode of the fifth transistor M5 is connected to the driving output terminal Gout; specifically, when the potential of the pull-up node PU is at a high level, the fifth transistor M5 is turned on, and the first clock signal CK1 provided by the first signal terminal SG1 is written to the driving output terminal Gout, otherwise, when the potential of the pull-up node PU is at a low level, the fifth transistor M5 is turned off.

[0065] The optional first reset unit 116 includes a sixth transistor M6, a gate of the sixth transistor M6 is connected to the second signal terminal SG2, the sixth transistor M6 is connected between the first power supply terminal PW1 and the drive output terminal Gout, the first electrode of the sixth transistor M6 is connected to the first power supply terminal PW1, and the second electrode of the sixth transistor M6 is connected to the drive output terminal Gout; when the second clock signal CK2 provided by the second signal terminal SG2 is a high level, the sixth transistor M6 is turned on, and the first power supply signal VGL provided by the first power supply terminal PW1 is written to the drive output terminal Gout, conversely, when the second clock signal CK2 provided by the second signal terminal SG2 is a low level, the sixth transistor is turned off.

[0066] Optionally, the second reset unit 117 includes a seventh transistor M7, a gate of the seventh transistor M7 is connected to the third signal terminal Reset, the seventh transistor M7 is connected between the first power supply terminal PW1 and the pull-up node PU, a first electrode of the seventh transistor M7 is connected to the first power supply terminal PW1, and a second electrode of the seventh transistor M7 is connected to the pull-up node PU;

[0067] Optionally, the third reset unit 118 includes an eighth transistor M8, the gate of the eighth transistor M8 is connected to the fourth signal terminal Goff, the eighth transistor M8 is connected between the first power supply terminal PW1 and the drive output terminal Gout, the first electrode of the eighth transistor M8 is connected to the first power supply terminal PW1, and the second electrode of the eighth transistor M8 is connected to the drive output terminal Gout. For any one of the seventh transistor M7 and the eighth transistor M8, when the potential of the gate of the transistor is at a high level, the transistor is turned on, and conversely, for any one of the first transistor M7 and the eighth transistor M8, when the potential of the gate of the transistor is at a low level, the transistor is turned off.

[0068] The optional node control unit 119 includes a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11, the gate of the ninth transistor M9 is connected to the pull-up node PU, the ninth transistor M9 is connected between the first power supply terminal PW1 and the first node PD, the first electrode of the ninth transistor M9 is connected to the first power supply terminal PW1, and the second electrode of the ninth transistor M9 is connected to the pull-down node PD; the gates of the tenth transistor M10 and the eleventh transistor M11 are both connected to the pull-down node PD, the tenth transistor M10 is connected between the first power supply terminal PW1 and the pull-up node PU, the first electrode of the tenth transistor M10 is connected to the first power supply terminal PW1, and the second electrode of the tenth transistor M10 is connected to the pull-up node PU; the eleventh transistor M11 is connected between the first power supply terminal PW1 and the drive output terminal Gout, the first electrode of the eleventh transistor M11 is connected to the first power supply terminal PW1, and the second electrode of the eleventh transistor M11 is connected to the drive output terminal Gout. For any one of the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11, when the potential of the gate of the transistor is at a high level, the transistor is turned on; conversely, for any one of the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11, when the potential of the gate of the transistor is at a low level, the transistor is turned off.

[0069] The optional shift register unit also includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is coupled between the driving output terminal Gout and the pull-up node PU, the first electrode of the first capacitor C1 is connected to the driving output terminal Gout, and the second electrode of the first capacitor C1 is connected to the pull-up node PU; the second capacitor C2 is coupled between the first signal terminal SG1 and the pull-down node PD, the first electrode of the second capacitor C2 is connected to the first signal terminal SG1, and the second electrode of the second capacitor C2 is connected to the pull-down node PD.

[0070] In this embodiment, the first capacitor C1 is coupled between the pull-up node PU and the driving output terminal Gout. When the pull-up node PU is in a floating state, the potential change of the driving output terminal Gout affects the potential change of the pull-up node PU. Specifically, when the potential of the driving output terminal Gout jumps from a high level to a low level, the potential of the pull-up node PU is pulled down; or when the potential of the driving output terminal Gout jumps from a low level to a high level, the potential of the pull-up node PU is bootstrapped.

[0071] The second capacitor C2 is coupled between the pull-down node PD and the first signal terminal SG1. When the pull-down node PD is in a floating state, the potential change of the first clock signal CK1 provided by the first signal terminal SG1 affects the potential change of the pull-down node PD. Specifically, when the first clock signal CK1 jumps from a high level to a low level, the potential of the pull-down node PD is pulled down; or, when the first clock signal CK1 jumps from a low level to a high level, the potential of the pull-down node PD is bootstrapped.

[0072] It is understood that the structure of the shift register unit of the present invention includes but is not limited to Figure 6 The structure of 11T2C shown in the figure, the relevant practitioners can reasonably design the structure of the shift register unit according to the product requirements and the application scenario of the shift register unit. The present invention does not repeat other shift register unit structures.

[0073] In this embodiment, Figure 6 Taking the shift register unit 101 shown as an example to describe its working process, the first power supply signal VGL provided by the first power supply terminal PW1 is a low-level signal, and the second power supply signal VGH provided by the second power supply terminal PW2 is a high-level signal. VGL can turn off the N-type transistor, and VGH can turn on the N-type transistor. The scanning circuit 100 can perform forward scanning and reverse scanning.

[0074] Figure 7 yes Figure 6 The timing diagram of the shift register unit performing forward scanning is shown in FIG. Figure 8 yes Figure 6 It should be noted that only the timing of one shift register unit in the scanning circuit is used for illustration. The forward scanning timing of the shift register unit is shown in FIG. Figure 7 shown.

[0075] Combination Figure 6 and Figure 7As shown, the forward scanning operation process of the shift register unit 101 includes at least the following stages: in the first stage t11, the electrical signal received by the first trigger terminal IN1 of the shift register unit 101 is a high-level signal, so that the first transistor M1 is turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU, the potential of the pull-up node PU is pulled down, the fifth transistor M5 is turned off, and the potential of the first clock CK1 provided by the first signal terminal SG1 jumps from a low level to a high level. After coupling through the second capacitor C2, the potential of the pull-down node PD is raised based on the bootstrap effect of the second capacitor C2, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU and the drive output terminal Gout.

[0076] In the second stage t12, the electric signal received by the first trigger terminal IN1 of the shift register unit 101 is a low-level signal, so that the first transistor M1 is turned off, and the first power signal VGL stops writing into the pull-up node PU. The electric signal received by the second trigger terminal IN2 is a high-level signal, so that the second transistor M2 is turned on, and the second power signal VGH provided by the second power terminal PW2 is written into the pull-up node PU, and the potential of the pull-up node PU jumps from a low level to a high level, so that the fifth transistor M5 is turned on, and the potential of the first clock signal CK1 provided by the first signal terminal SG1 jumps from a high level to a low level, driving the output terminal Gout to output a low-level signal. At the same time, the ninth transistor M9 is turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-down node PD, and the potential of the pull-down node PD is pulled down, and the tenth transistor M10 and the eleventh transistor M11 are turned off.

[0077] In the third stage t13, the electrical signal received by the second trigger terminal IN2 of the shift register unit 101 is a low-level signal, so that the second transistor M2 is turned off, and the pull-up node PU is in a floating state. The potential of the pull-up node PU maintains the high level of the second stage t12 period, and the fifth transistor M5 remains turned on. The potential of the first clock signal CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, driving the output terminal Gout to output a high-level signal to drive the corresponding row sub-pixel, and the low level of the driving output terminal Gout jumps to a high-level signal. After coupling through the first capacitor C1, the potential of the pull-up node PU is raised based on the bootstrap effect of the first capacitor C1.

[0078] In the fourth stage t14, the electrical signal received by the third trigger terminal IN3 of the shift register unit 101 is a high-level signal, which turns on the third transistor M3, and the second power supply signal VGH provided by the second power supply terminal PW2 is written into the pull-up node PU, maintaining the high level of the pull-up node PU, and the fifth transistor M5 remains on. The first clock signal CK1 provided by the first signal terminal SG1 jumps from a high level to a low level, and the low level of the first clock signal CK1 is written into the driving output terminal Gout.

[0079] In the fifth stage t15, the electric signal received by the fourth trigger terminal IN4 of the shift register unit 101 is a high-level signal, so that the fourth transistor M4 is turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU, and the potential of the pull-up node PU is pulled down and reduced, and the fifth transistor M5 is switched from on to off. The potential of the first clock CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, and after coupling through the second capacitor C2, the potential of the pull-down node PD is raised based on the bootstrap effect of the second capacitor C2, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU and the driving output terminal Gout.

[0080] As described above, the driving output terminal of the shift register unit 101 outputs a high level signal in the third stage t13, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register unit 101 maintains a low level signal output after the fifth stage t15 until the first trigger terminal IN1 receives a high level signal again.

[0081] Combination Figure 6 and Figure 8 As shown, the reverse scanning operation process of the shift register unit 101 includes at least the following stages: in the first stage t21, the electrical signal received by the fourth trigger terminal IN4 of the shift register unit 101 is a high-level signal, the fourth transistor M4 is turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU, the potential of the pull-up node PU is pulled down, the fifth transistor M5 is turned off, and the potential of the first clock signal CK1 provided by the first signal terminal SG1 jumps from a low level to a high level. After coupling through the second capacitor C2, the potential of the pull-down node PD is raised based on the bootstrap effect of the second capacitor C2, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU and the drive output terminal Gout.

[0082] In the second stage t22, the electric signal received by the fourth trigger terminal IN4 of the shift register unit 101 is a low-level signal, so that the fourth transistor M4 is turned off, and the first power signal VGL stops writing into the pull-up node PU. The electric signal received by the third trigger terminal IN3 is a high-level signal, so that the third transistor M3 is turned on, and the second power signal VGH provided by the second power terminal PW2 is written into the pull-up node PU, and the potential of the pull-up node PU jumps from a low level to a high level, so that the fifth transistor M5 is turned on, and the potential of the first clock signal CK1 provided by the first signal terminal SG1 jumps from a high level to a low level, driving the output terminal Gout to output a low-level signal. At the same time, the ninth transistor M9 is turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-down node PD, and the potential of the pull-down node PD is pulled down, and the tenth transistor M10 and the eleventh transistor M11 are turned off.

[0083] In the third stage t23, the electrical signal received by the third trigger terminal IN3 of the shift register unit 101 is a low-level signal, so that the third transistor M3 is turned off, and the pull-up node PU is in a floating state. The potential of the pull-up node PU maintains the high level of the second stage t22, and the fifth transistor M5 remains turned on. The potential of the first clock signal CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, driving the output terminal Gout to output a high-level signal to drive the corresponding row sub-pixel, and the low level of the driving output terminal Gout jumps to a high-level signal. After coupling through the first capacitor C1, the potential of the pull-up node PU is raised based on the bootstrap effect of the first capacitor C1.

[0084] In the fourth stage t24, the electrical signal received by the second trigger terminal IN2 of the shift register unit 101 is a high-level signal, the second transistor M2 is turned on, the second power supply signal VGH provided by the second power supply terminal PW2 is written into the pull-up node PU, and the high level of the pull-up node PU is maintained, the fifth transistor M5 remains on, and the first clock signal CK1 provided by the first signal terminal SG1 jumps from a high level to a low level, and the low level of the first clock signal CK1 is written into the driving output terminal Gout.

[0085] In the fifth stage t25, the electric signal received by the first trigger terminal IN1 of the shift register unit 101 is a high-level signal, so that the first transistor M1 is turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU, then the potential of the pull-up node PU is pulled down and reduced, so that the fifth transistor M5 is switched from on to off. The potential of the first clock CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, and after coupling through the second capacitor C2, the potential of the pull-down node PD is raised based on the bootstrap effect of the second capacitor C2, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first power signal VGL provided by the first power terminal PW1 is written into the pull-up node PU and the driving output terminal Gout.

[0086] As described above, the driving output terminal Gout of the shift register unit 101 outputs a high level signal in the third stage t23, and the high level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register unit 101 maintains a low level signal output after the fifth stage t25 until the fourth trigger terminal IN4 receives a high level signal again.

[0087] It should be noted that the first electrode of the fifth transistor M5 is connected to the first signal terminal SG1, the gate of the sixth transistor M6 is connected to the second signal terminal SG2, the first signal terminal SG1 receives the first clock signal CK1, and the second signal terminal SG2 receives the second clock signal CK2. The first clock signal CK1 is different from the second clock signal CK2, so the clock signal line connected to the first signal terminal SG1 is different from the clock signal line connected to the second signal terminal SG2.

[0088] In this embodiment, Figure 6As shown, the shift register unit 101 includes a forward and reverse scan module S, and the forward and reverse scan module S includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein the first transistor M1 and the fourth transistor M4 pull down the potential of the pull-up node PU, the second transistor M1 and the third transistor M3 pull up the potential of the pull-up node PU, the first electrode of the first transistor M1 is connected to the first power supply terminal PW1, the first electrode of the second transistor M2 is connected to the second power supply terminal PW2, the first electrode of the third transistor M3 is connected to the second power supply terminal PW2, and the fourth transistor M The first electrode of 4 is connected to the first power supply terminal PW1, and the second electrodes of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all connected to the pull-up node PU. In the forward scanning process, the first transistor M1 and the fourth transistor M4 pull down the potential of the pull-up node PU, and the second transistor M2 and the third transistor M3 pull up the potential of the pull-up node PU. In the reverse scanning process, the first transistor M1 and the fourth transistor M4 still pull down the potential of the pull-up node PU, and the second transistor M2 and the third transistor M3 pull up the potential of the pull-up node PU. Therefore, after the forward and reverse scanning modes are switched, the functions of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 do not change, and there is no need to switch the first power supply signal VGL and the second power supply signal VGH according to the scanning direction. The first transistor M1 and the second transistor M4 whose threshold voltage drifts forward do not need to pull up the pull-up node PU after the scanning mode is switched. Therefore, the shift register unit 101 can normally switch to the reverse scanning mode after a long period of forward scanning, or can normally switch to the forward scanning mode after a long period of reverse scanning. Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning, which solves the problems in the prior art.

[0089] The optional scanning circuit 100 includes X-stage cascaded shift register units 101, each stage of the shift register unit includes at least one shift output terminal Gx, and the shift register units of each stage are cascaded through the shift output terminal Gx. The shift output terminal Gx and the drive output terminal Gout output the same signal. In some embodiments, the shift output terminal Gx and Gou are separated. In this embodiment, the shift output terminal Gx multiplexes the drive output terminal Gout. Figure 6 As shown, on the one hand, the shift register unit 101 outputs a signal through the driving output terminal Gout to drive the corresponding sub-pixel, and on the other hand, the shift register unit 101 is also cascaded through the driving output terminal Gout.

[0090] The optional scanning circuit 100 further includes Y clock signal lines and k*Y trigger lines, k≥1, Y≥2. Among the Y clock signal lines, any two clock signal lines provide clock signals with the same frequency and different phases. Figure 6As shown, the first trigger terminal IN1 of the n-th shift register unit is connected to the shift output terminal Gx or the trigger line of the (n-2i)-th shift register unit, the second trigger terminal IN2 of the n-th shift register unit is connected to the shift output terminal Gx or the trigger line of the (ni)-th shift register unit, the third trigger terminal IN3 of the n-th shift register unit is connected to the shift output terminal Gx or the trigger line of the (n+i)-th shift register, and the fourth trigger terminal IN4 of the n-th shift register unit is connected to the shift output terminal Gx or the trigger line of the (n+2i)-th shift register unit, n≤X, i≥1.

[0091] In this embodiment, the scanning circuit can be driven on both sides or on one side. It is understandable that the clock signal provided by the same clock signal line during forward scanning may be different from the clock signal provided by the same clock signal line during reverse scanning, and the trigger signal provided by the same trigger line during forward scanning may be different from the trigger signal provided by the same trigger line during reverse scanning.

[0092] Fig. 9 is a schematic diagram of a scanning circuit 100 provided by an embodiment of the present invention, such as Fig. 9 As shown, the single-side structure of the scanning circuit is a 2-phase GOA structure. The optional scanning circuit 100 includes: two clock signal lines including a first clock signal line CKL1 and a second clock signal line CKL2; and four trigger lines including a first trigger line STV1, a second trigger line STV2, a third trigger line STV3 and a fourth trigger line STV4.

[0093] The X-stage shift registers 101 in the scanning circuit 100 are marked as GOA1, GOA2, GOA3, GOA4, ... GOA X , the nth stage shift register 101 is marked as GOA n 1≤n≤X. Two adjacent shift register units 101 constitute a shift register unit group 111. For example, shift register unit GOA1 and shift register unit GOA2 constitute a first-stage shift register unit group 111 / 1, shift register unit GOA3 and shift register unit GOA4 constitute a second-stage shift register unit group 111 / 2, and so on. Therefore, the scanning circuit 100 includes X / 2 cascaded shift register unit groups 111. Fig. 9 Only the first-stage shift register group 111 / 1, part of the second-stage shift register group 111 / 2, part of the X / 2-1st-stage shift register group 111 / (X / 2-1), and the X / 2nd-stage shift register group 111 / (X / 2) of the scanning circuit 100 are illustrated.

[0094] For any level of shift register unit group 111, the two adjacent shift register units 101 included therein are respectively marked as the first-level shift register unit GOA-1 and the second-level shift register unit GOA-2 of the shift register unit group 111, for example, shift register unit GOA1 is the first-level shift register unit GOA-1 of the first-level shift register unit group 111 / 1, and shift register unit GOA2 is the second-level shift register unit GOA-2 of the first-level shift register unit group 111 / 1; shift register unit GOA3 is the first-level shift register unit GOA-1 of the second-level shift register unit group 111 / 2, and shift register unit GOA4 is the second-level shift register unit GOA-2 of the second-level shift register unit group 111 / 2, and so on.

[0095] like Fig. 9 As shown, the shift register unit group satisfies the following conditions: the first clock signal CKL1 connects the first signal terminal SG1 of the first-stage shift register unit GOA-1 of each stage shift register unit group 111 and the second signal terminal SG2 of the second-stage shift register unit GOA-2 of each stage shift register unit group 111; the second clock signal CKL2 connects the second signal terminal SG2 of the first-stage shift register unit GOA-1 of each stage shift register unit group 111 and the first signal terminal SG1 of the second-stage shift register unit GOA-2 of each stage shift register unit group 111; the scanning circuit 100 includes a forward scanning mode and a reverse scanning mode. Specifically, the forward scanning mode can be a scanning direction from GOA1 to GOA-2. X The reverse scanning mode is along the GOA X Scan in the direction opposite to GOA1.

[0096] When the scanning circuit is performing forward scanning or reverse scanning, the working timing of the first-stage shift register unit GOA-1 of any stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the first clock signal line CKL1, and the second clock signal CK2 received by the second signal terminal SG2 is derived from the second clock signal line CKL2. The working timing of the second-stage shift register unit GOA-2 of any stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the second clock signal line CKL2, and the second clock signal CK2 received by the second signal terminal SG2 is derived from the second clock signal line CKL1. It can be understood that, in this embodiment, the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 have the same frequency and opposite phases. When switching the forward and reverse scanning modes, the timing of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 can be switched with each other.

[0097] Alternatively, if Fig. 9As shown, the first trigger terminal IN1 of the n-th stage shift register unit 101 is connected to the shift output terminal Gx of the (n-2)-th stage shift register unit 101, the second trigger terminal IN2 of the n-th stage shift register unit 101 is connected to the shift output terminal Gx of the (n-1)-th stage shift register unit 101, the third trigger terminal IN3 of the n-th stage shift register unit 101 is connected to the shift output terminal Gx of the (n+1)-th stage shift register unit 101, and the fourth trigger terminal IN4 of the n-th stage shift register unit 101 is connected to the shift output terminal Gx of the (n+2)-th stage shift register unit 101. For the case where n is less than or equal to 2, that is, including the first-stage shift register unit GOA1 and the second-stage shift register GOA2, the signals received by the first trigger terminal INI1 and the second trigger terminal IN2 of the first-stage shift register unit GOA1 and the first trigger terminal IN1 of the second-stage shift register unit GOA2 can be directly from the STV trigger line. For example, the first trigger line STV1 can directly provide an electrical signal to the first trigger terminal IN1 of the first-stage shift register unit GOA1, and the second trigger line STV2 can directly provide an electrical signal to the second trigger terminal IN2 of the first-stage shift register unit GOA1 and the first trigger terminal IN1 of the second-stage shift register unit GOA2; for the last two stages of GOA units 101, that is, the (X-1)th stage shift register unit GOA X-1 and the Xth-stage shift register unit GOA X , optional (X-1)th level shift register unit GOA X-1 The fourth trigger terminal IN4, the X-th stage shift register unit GOA X The signal received by the third trigger terminal IN3 and the fourth trigger terminal IN4 can directly come from the STV trigger line. For example, the third trigger line STV3 can directly give the X-1 stage shift register unit GOA X-1 The fourth trigger terminal IN4 and the X-th shift register unit GOA X The third trigger terminal IN3 provides an electrical signal, and the fourth trigger line STV4 directly supplies the X-th stage shift register unit GOA X The fourth trigger terminal IN4 of the first-stage shift register unit GOA1 provides an electrical signal. However, it is not limited to this. In other embodiments, two stages of dummy shift register units may be optionally provided on the first-stage shift register unit GOA1, respectively marked as dummy-GOA1 and dummy-GOA2. Dummy-GOA1 may directly provide an electrical signal to the first trigger terminal IN1 of the first-stage shift register unit GOA1, and dummy-GOA2 may provide an electrical signal to the second trigger terminal IN2 of the first-stage shift register unit GOA1 and the first trigger terminal IN1 of the second-stage shift register unit GOA2. Similarly, the second-stage shift register unit GOA1 may optionally provide an electrical signal to the first trigger terminal IN2 of the first-stage shift register unit GOA1 and the first trigger terminal IN1 of the second-stage shift register unit GOA2. X Two levels of dummy shift register units are set below, marked as dummy-GOAX-1 and dummy-GOA X , dummy-GOA X-1 You can directly give the X-1th level shift register unit GOA X-1 The fourth trigger terminal IN4 and the X-th shift register unit GOA X The third trigger terminal IN3 provides an electrical signal, dummy-GOA X Directly give the X-th shift register unit GOA X The fourth trigger terminal IN4 provides an electrical signal.

[0098] The optional scanning circuit 100 includes forward and reverse scanning modes, Fig.10 yes Fig. 9 The schematic diagram of the clock signal and trigger signal of the scanning circuit 100 in the forward scanning mode is shown in FIG. Fig.10 As shown, in the positive scanning mode, the clock signal provided by the first clock signal line CKL1 and the clock signal provided by the second clock signal line CKL2 have the same frequency and opposite phases; at the starting stage of the frame scan, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H; at the ending stage of the frame scan, the phase of the trigger signal provided by the third trigger signal line STV3 is earlier than the phase of the trigger signal provided by the fourth trigger signal line STV4, and the phase difference between the two is 2*H.

[0099] Fig.11 yes Fig. 9 The schematic diagram of the clock signal and trigger signal of the scanning circuit 100 in the reverse scanning mode is shown in FIG. Fig.11 As shown, in the reverse scanning mode, the clock signal provided by the first clock signal line CKL1 and the clock signal provided by the second clock signal line CKL2 have the same frequency and opposite phases; at the starting stage of the frame scan, the phase of the trigger signal provided by the fourth trigger signal line STV4 is earlier than the phase of the trigger signal provided by the third trigger signal line STV3, and the phase difference between the two is 2*H; at the end stage of the frame scan, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H.

[0100] In other embodiments, Fig.12 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention, such as Fig.12 As shown, the scanning circuit 100 may include: two clock signal lines including a first clock signal line CKL1 and a second clock signal line CKL2; two trigger lines including a first trigger line STV1 and a second trigger line STV2. Fig. 9In the scanning circuit shown in FIG. 1 , the third trigger line STV3 multiplexes the first trigger line STV1, and the fourth trigger line STV4 multiplexes the second trigger line STV2. Fig.12 As shown, the first trigger terminal IN1 of the first-stage shift register unit GOA1 of the scanning circuit 100 is connected to the first trigger line STV1, and the second trigger terminal IN2 of the first-stage shift register unit GOA1 is connected to the second trigger line; the first trigger terminal IN1 of the second-stage shift register unit GOA2 is connected to the second trigger line STV2, and the second trigger terminal IN2 of the second-stage shift register unit GOA2 is connected to the shift output terminal Gx of the first-stage shift register unit GOA1. X-1 The third trigger terminal IN3 is connected to the X-th stage shift register unit GOA X The shift output terminal Gx, the X-1th stage shift register unit GOA X-1 The fourth trigger terminal IN4 is connected to the first trigger line STV1, and the X-th stage shift register unit GOA X The third trigger terminal IN3 is connected to the first trigger line STV1, and the X-th stage shift register unit GOA X The fourth trigger terminal IN4 is connected to the second trigger line STV2; or Fig.13 As shown, Fig.13 is a schematic diagram of another scanning circuit 100 provided by an embodiment of the present invention, wherein the X-1-th stage shift register unit GOA X-1 The third trigger terminal IN3 is connected to the X-th stage shift register unit GOA X The shift output terminal Gx, the X-1th stage shift register unit GOA X-1 The fourth trigger terminal IN4 is connected to the second trigger line STV2, and the X-th stage shift register unit GOA X The third trigger terminal IN2 is connected to the second trigger line ST21, and the X-th stage shift register unit GOA X The fourth trigger terminal IN4 is connected to the first trigger line STV1. Fig. 9 In the scan circuit shown, the third trigger line STV3 multiplexes the first trigger line STV1, and the fourth trigger line STV4 multiplexes the second trigger line STV2. This arrangement can reduce two trigger lines and reduce the border of the array substrate.

[0101] Fig.14 yes Fig.12 A schematic diagram of a clock signal and a trigger signal in a forward scanning mode of the scanning circuit shown in FIG. Fig.14As shown, in the positive scanning mode, the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 have the same frequency and opposite phases; at the beginning stage of the frame scanning, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H; at the end stage of the frame scanning, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H.

[0102] Fig.15 yes Fig.12 A schematic diagram of a reverse scanning mode clock signal and trigger signal of the scanning circuit shown in FIG. Fig.14 As shown, in the reverse scan mode, the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 have the same frequency and opposite phases; Fig.14 The difference is that the phases of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 are switched with each other, that is, the clock signal provided by the first clock signal line CKL1 and the clock signal provided by the second clock signal line CKL2 are switched with each other. Fig.14 The phases of the second clock signal line CKL2 shown in the figure are the same, and the clock signal provided by the second clock signal line CKL2 is Fig.14 The clock signals provided by the first clock signal line CKL1 shown in the figure have the same phase; at the beginning stage of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H; at the end stage of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H.

[0103] Fig.16 yes Fig.13 A schematic diagram of a clock signal and a trigger signal in a forward scanning mode of the scanning circuit shown in FIG. Fig.16 As shown, in the positive scan mode, the clock signals provided by the first clock signal CKL1 and the second clock signal line CKL2 have the same frequency and opposite timing; at the beginning stage of the frame scan, the phase of the trigger signal provided by the first trigger signal line STV1 is earlier than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H; at the end stage of the frame scan, the phase of the trigger signal provided by the first trigger signal line STV1 is later than the phase of the trigger signal provided by the second trigger signal line STV2, and the phase difference between the two is 2*H.

[0104] Fig.17 yes Fig.13 A schematic diagram of a reverse scanning mode clock signal and trigger signal of the scanning circuit shown in FIG. Fig.17 As shown, in the reverse scan mode, the clock signals provided by the first clock signal CKL1 and the second clock signal line CKL2 have the same frequency and opposite phases; Fig.16 The difference is that the phases of the clock signals provided by the first clock signal line CKL1 and the second clock signal line CKL2 are switched with each other, that is, the clock signal provided by the first clock signal line CKL1 and the clock signal provided by the second clock signal line CKL2 are switched with each other. Fig.16 The phases of the second clock signal line CKL2 shown in the figure are the same, and the clock signal provided by the second clock signal line CKL2 is Fig.16 The clock phases provided by the first clock signal line CKL1 shown are the same; at the beginning stage of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is earlier than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H; at the end stage of frame scanning, the phase of the trigger signal provided by the second trigger signal line STV2 is later than the phase of the trigger signal provided by the first trigger signal line STV1, and the phase difference between the two is 2*H.

[0105] Fig.18 A schematic diagram of another scanning circuit provided by an embodiment of the present invention is shown as follows: Fig.18 As shown, the single-side structure of the scanning circuit 300 is a 4-phase GOA structure, the optional Y clock signal lines include a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3 and a fourth clock signal line CKL4, and the optional k*Y trigger lines include a first trigger line STV1 to an eighth trigger line STV8, k≥1, Y≥2. The scanning circuit 100 includes an X-stage shift register unit 101, and the X-stage shift register 101 in the scanning circuit 100 is marked as GOA1, GOA2, GOA3, GOA4...GOA in sequence. X , the nth stage shift register 101 is marked as GOA n Four adjacent shift register units 101 constitute a shift register unit group 111. For example, shift register unit GOA1, shift register unit GOA2, shift register unit GOA3 and shift register unit GOA4 constitute a first-stage shift register unit group 111 / 1, shift register unit GOA5, shift register unit GOA6, shift register unit GOA7 and shift register unit GOA8 constitute a second-stage shift register unit group 111 / 2, and so on. Therefore, the scanning circuit 100 includes an X / 4 cascaded shift register unit group 111, Fig.18 Only the 1st stage shift register unit group 111 / 1 and the X / 4th stage shift register unit group 111 / (X / 4) of the scan circuit 100 are illustrated.

[0106] For any level of shift register unit group 111, the four adjacent shift register units 101 included therein are respectively marked as the first-level shift register unit GOA-1, the second-level shift register unit GOA-2, the third-level shift register unit GOA-3 and the fourth-level shift register unit GOA-4 of the shift register unit group 111, for example, the shift register unit GOA1 is the first-level shift register unit GOA-1 of the first-level shift register unit group 111 / 1, the shift register unit GOA2 is the second-level shift register unit GOA-2 of the first-level shift register unit group 111 / 1, and the shift register unit GOA3 is the third-level shift register unit GOA-4 of the first-level shift register unit group 111 / 1. Shift register unit GOA-3, shift register unit GOA4 is the 4th-level shift register unit GOA-4 of the 1st-level shift register unit group 111 / 1; shift register unit GOA5 is the 1st-level shift register unit GOA-1 of the 2nd-level shift register unit group 111 / 2, shift register unit GOA6 is the 2nd-level shift register unit GOA-2 of the 2nd-level shift register unit group 111 / 2, shift register unit GOA7 is the 3rd-level shift register unit GOA-3 of the 2nd-level shift register unit group 111 / 2, shift register unit GOA8 is the 4th-level shift register unit GOA-4 of the 2nd-level shift register unit group 111 / 2; and so on.

[0107] like Fig.18 As shown, the shift register unit group satisfies the following conditions: the first clock signal CKL1 is connected to the first signal terminal SG1 of the first-stage shift register unit GOA-1 of each stage of the shift register unit group 111 and the second signal terminal SG2 of the third-stage shift register unit GOA-3 of each stage of the shift register unit group 111;

[0108] The second clock signal CKL2 is connected to the first signal terminal SG1 of the second-stage shift register unit GOA-2 of each stage shift register unit group 111 and the second signal terminal SG2 of the fourth-stage shift register unit GOA-4 of each stage shift register unit group 111;

[0109] The third clock signal CKL3 is connected to the first signal terminal SG1 of the third-stage shift register unit GOA-3 of each stage of the shift register unit group 111 and the second signal terminal SG2 of the first-stage shift register unit GOA-1 of each stage of the shift register unit group 111;

[0110] The fourth clock signal CKL4 is connected to the first signal terminal SG1 of the fourth-stage shift register unit GOA- 4 of each stage of the shift register unit group 111 and the second signal terminal SG2 of the second-stage shift register unit GOA- 2 of each stage of the shift register unit group 111 .

[0111] The scanning circuit 100 includes a forward scanning mode and a reverse scanning mode. Specifically, the forward scanning mode can be directed along GOA1 to GOA X The reverse scanning mode is along the GOA X Scan in the direction opposite to GOA1.

[0112] When the scanning circuit 100 performs forward scanning or reverse scanning, the working timing of the first-stage shift register GOA-1 of any stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the first clock signal line CKL1, and the second clock signal CK2 received by the second signal terminal SG2 is derived from the third clock signal line CKL3;

[0113] The working sequence of the second-stage shift register GOA-2 of any stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the second clock signal line CKL2, and the second clock signal CK2 received by the second signal terminal SG2 is derived from the fourth clock signal line CKL4;

[0114] The working timing of the third-stage shift register GOA-3 of any stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is derived from the third clock signal line CKL3, and the second clock signal CK2 received by the second signal terminal SG2 is derived from the first clock signal line CKL1;

[0115] The working timing of the 4th stage shift register GOA-4 of any stage shift register unit group 111 is as follows: the first clock signal CK1 received by the first signal terminal SG1 comes from the fourth clock signal line CKL4, and the second clock signal CK2 received by the second signal terminal SG2 comes from the second clock signal line CKL2.

[0116] like Fig.18As shown, the first trigger terminal IN1 of the nth-stage shift register unit can be connected to the shift output terminal Gx of the (n-4)th-stage shift register unit 101, the second trigger terminal IN2 of the nth-stage shift register unit 101 is connected to the shift output terminal Gx of the (n-2)th-stage shift register unit 101, the third trigger terminal IN3 of the nth-stage shift register unit 101 is connected to the shift output terminal Gx of the (n+2)th-stage shift register unit 101, and the fourth trigger terminal IN4 of the nth-stage shift register unit 101 is connected to the shift output terminal Gx of the (n+4)th-stage shift register unit 101. For the case where n is less than or equal to 4, i.e., including the shift register units GOA1 to GOA4, the signals received by the first trigger terminals IN1 of the shift register units GOA1 to GOA4 can directly come from the trigger line STV, and the signals received by the second trigger terminals IN2 of the shift register units GOA1 and GOA2 can also directly come from the trigger line STV. For example, the first trigger line STV1 can directly provide an electrical signal to the first trigger terminal IN1 of the first-stage shift register unit GOA1, the second trigger signal line STV2 can provide an electrical signal to the second trigger terminal IN2 of the first-stage shift register unit GOA1 and the first trigger terminal IN4 of the third-stage shift register unit GOA3, the third trigger signal line STV3 can directly provide an electrical signal to the first trigger terminal IN1 of the second-stage shift register unit GOA2, and the fourth trigger signal line STV4 can directly provide an electrical signal to the second trigger terminal IN2 of the second-stage shift register unit GOA2 and the first trigger terminal IN1 of the fourth-stage shift register unit GOA4. However, it is not limited thereto. In other embodiments, four levels of dummy shift register units may be optionally provided on the shift register unit GOA1, which are marked as dummy-GOA1, dummy-GOA2, dummy-GOA3 and dummy-GOA4 respectively. Dummy-GOA1 provides an electrical signal to the first trigger terminal IN1 of the first-level shift register unit GOA1, dummy-GOA2 can provide an electrical signal to the second trigger terminal IN2 of the first-level shift register unit GOA1 and the first trigger terminal IN1 of the third-level shift register unit GOA3, dummy-GOA3 can directly provide an electrical signal to the first trigger terminal IN1 of the second-level shift register unit GOA2, and dummy-GOA4 can directly provide an electrical signal to the second trigger terminal IN2 of the second-level shift register unit GOA2 and the first trigger terminal IN1 of the fourth-level shift register unit GOA4. Similarly, for the last four levels of shift register units GOA X-3 To shift register unit GOA X , optional shift register unit GOA X-3 To storage unit GOA X The signal received by the fourth trigger terminal IN4 can directly come from the trigger line STV, the shift register unit GOAX-3 and shift register unit GOA X-2 The signal received by the third trigger terminal IN3 can also come directly from the trigger line STV. For example, the fifth trigger line STV5 can directly provide the X-3 stage shift register unit GOA. X-3 The fourth trigger terminal IN4 and the X-1 stage shift register unit GOA X-1 The third trigger terminal IN3 provides an electrical signal, and the sixth trigger line STV6 can provide an electrical signal to the X-2 stage shift register unit GOA. X-2 The fourth trigger terminal IN4 and the X-th shift register unit GOA X The third trigger terminal IN3 provides an electrical signal, and the seventh trigger line STV7 can directly provide the X-1 stage shift register unit GOA X-1 The fourth trigger terminal IN4 provides an electrical signal, and the eighth trigger line STV8 can directly provide the X-th stage shift register unit GOA X The fourth trigger terminal IN4 provides an electrical signal. However, it is not limited thereto. In other embodiments, the shift register unit GOA may also be selected. X There are four levels of dummy shift register units, marked as dummy-GOA5, dummy-GOA6, dummy-GOA7 and dummy-GOA8 respectively. Dummy-GOA5 can directly give the X-3 level shift register unit GOA X-3 The fourth trigger terminal IN4 and the X-1 stage shift register unit GOA X-1 The third trigger terminal IN3 provides an electrical signal, and dummy-GOA6 can provide an electrical signal to the X-2 stage shift register unit GOA X-2 The fourth trigger terminal IN4 and the X-th shift register unit GOA X The third trigger terminal IN3 provides an electrical signal, and dummy-GOA7 can directly provide the X-1th stage shift register unit GOA X-1 The fourth trigger terminal IN4 provides an electrical signal, and dummy-GOA8 can directly provide the X-th shift register unit GOA X The fourth trigger terminal IN4 provides an electrical signal.

[0117] Fig.19 yes Fig.18 The schematic diagram of the clock signal and trigger signal of the scanning circuit in the forward scanning mode is shown in FIG. Fig.19As shown, in the forward scanning mode, the phase of the clock signal provided by the first clock signal CKL1 is earlier than the phase of the clock signal provided by the second clock signal CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H. At the start stage of frame scanning, the phase of the trigger signal provided by the first trigger line STV1 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the fourth trigger line STV4, and the phase difference between the two is 1*H; at the end stage of frame scanning, the phase of the trigger signal provided by the fifth trigger line STV5 is earlier than the phase of the trigger signal provided by the seventh trigger line STV7, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the seventh trigger line STV7 is earlier than the phase of the trigger signal provided by the sixth trigger line STV6, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the sixth trigger line STV6 is earlier than the phase of the trigger signal provided by the eighth trigger line STV8, and the phase difference between the two is 1*H.

[0118] Fig. 20 Fig.18 The schematic diagram of the clock signal and trigger signal of the scanning circuit in the reverse scanning mode is shown in FIG. Fig. 20It is shown that, in the reverse scanning mode, the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL1 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H. At the start stage of frame scanning, the phase of the trigger signal provided by the eighth trigger line STV8 is earlier than the phase of the trigger signal provided by the sixth trigger line STV6, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the sixth trigger line STV6 is earlier than the phase of the trigger signal provided by the seventh trigger line STV7, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the seventh trigger line STV7 is earlier than the phase of the trigger signal provided by the fifth trigger line STV5, and the phase difference between the two is 1*H; at the end stage of frame scanning, the phase of the trigger signal provided by the fourth trigger line STV4 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the first trigger line STV1, and the phase difference between the two is 1*H.

[0119] In some further embodiments, Fig.21 is a schematic diagram of another scanning circuit provided by an embodiment of the present invention, such as Fig.21 As shown, the scanning circuit 100 may include: four clock signal lines including a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3 and a fourth clock signal line CKL4; four trigger lines including a first trigger line STV1, a second trigger line STV2, a third trigger line STV3 and a second trigger line STV4. Fig.18 In the embodiment shown, the fifth trigger line STV5 in the scanning circuit 100 multiplexes the first trigger line STV1, the seventh trigger line STV7 multiplexes the third trigger line STV3, the sixth trigger line STV6 multiplexes the second trigger line STV2, and the eighth trigger line STV8 multiplexes the third trigger line STV1.

[0120] In this embodiment, the first trigger terminal IN1 of the first stage shift register unit GOA1 is connected to the first trigger line STV1, and the second trigger terminal IN2 of the first stage shift register unit GOA1 is connected to the second trigger line STV2;

[0121] The first trigger terminal IN1 of the second-stage shift register unit GOA2 is connected to the third trigger line STV3, and the second trigger terminal IN4 of the second-stage shift register unit GOA2 is connected to the fourth trigger line STV4;

[0122] The first trigger terminal IN1 of the third-stage shift register unit GOA3 is connected to the second trigger line STV2, and the second trigger terminal IN2 of the third-stage shift register unit GOA3 is connected to the shift output terminal Gx of the first-stage shift register unit GOA1;

[0123] The first trigger terminal IN1 of the 4th stage shift register unit GOA4 is connected to the fourth trigger line STV4, and the second trigger terminal IN2 of the 4th stage shift register unit GOA4 is connected to the shift output terminal Gx of the 2nd stage shift register unit GOA2;

[0124] X-3rd level shift register unit GOA X-3 The third trigger terminal IN3 is connected to the X-1th level bit register unit GOA X-1 The shift output terminal Gx, the X-3 stage shift register unit GOA X-3 The fourth trigger terminal IN4 is connected to the first trigger line STV1;

[0125] X-2nd stage shift register unit GOA X-2 The third trigger terminal IN3 is connected to the X-th stage shift register unit GOA X The shift output terminal Gx, the X-2 stage shift register unit GOA X-2 The fourth trigger terminal IN4 is connected to the third trigger line STV3;

[0126] X-1th level shift register unit GOA X-1 The third trigger terminal IN3 is connected to the first trigger line STV1, and the X-1th stage shift register unit GOA X-1 The fourth trigger terminal IN4 is connected to the second trigger line STV2;

[0127] Xth stage shift register unit GOA X The third trigger terminal IN3 is connected to the third trigger line STV3, and the X-th stage shift register unit GOA X The fourth trigger terminal IN4 is connected to the fourth trigger line STV4.

[0128] Fig. 22 yes Fig.21 The schematic diagram of the clock signal and trigger signal of a forward scanning mode of the scanning circuit shown in FIG. Fig. 22As shown, in the positive scan mode, the phase of the clock signal provided by the first clock signal CKL1 is earlier than the phase of the clock signal provided by the second clock signal CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H. At the start stage of frame scanning, the phase of the trigger signal provided by the first trigger line STV1 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the fourth trigger line STV4, and the phase difference between the two is 1*H; at the end stage of frame scanning, the phase of the trigger signal provided by the first trigger line STV1 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the fourth trigger line STV4, and the phase difference between the two is 1*H.

[0129] Fig.23 yes Fig.21 The schematic diagram of the clock signal and trigger signal of a reverse scanning mode of the scanning circuit shown in FIG. Fig.23As shown, the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1*H; the phase of the clock signal provided by the second clock signal line CKL1 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1*H. At the start stage of frame scanning, the phase of the trigger signal provided by the fourth trigger line STV4 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the first trigger line STV1, and the phase difference between the two is 1*H; at the end stage of frame scanning, the phase of the trigger signal provided by the fourth trigger line STV4 is earlier than the phase of the trigger signal provided by the second trigger line STV2, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the second trigger line STV2 is earlier than the phase of the trigger signal provided by the third trigger line STV3, and the phase difference between the two is 1*H; the phase of the trigger signal provided by the third trigger line STV3 is earlier than the phase of the trigger signal provided by the first trigger line STV1, and the phase difference between the two is 1*H. In addition, in the embodiment of the present invention, the fifth to eighth trigger lines can reuse the first to fourth trigger lines in other forms, which will not be described in detail here.

[0130] In the present invention, the first electrode of the first transistor M1 is connected to the first power supply terminal PW1, the first electrode of the second transistor M2 is connected to the second power supply terminal PW2, the first electrode of the third transistor M3 is connected to the second power supply terminal PW2, the first electrode of the fourth transistor M4 is connected to the first power supply terminal PW1, the second electrode of the first transistor M1, the second electrode of the second transistor M2, the second electrode of the third transistor M3 and the second electrode of the fourth transistor M4 are all connected to the pull-up node PU, in the process of switching from forward scanning to reverse scanning or in the process of switching from reverse scanning to forward scanning, the power supply signal provided by the first power supply terminal PW1 and the second power supply terminal PW2 does not change, the first power supply terminal PW1 always provides the first power supply signal VGL, and the second power supply terminal PW2 always provides the second power supply signal VGH, even if the threshold voltage of the first transistor M1 and the fourth transistor M4 will increase and the driving capability will decrease, but they no longer need to bear the role of pulling up the pull-up node PU, after a long period of forward scanning, the scanning circuit 100 can normally switch to the reverse scanning mode, or after a long period of reverse scanning, the scanning circuit 100 can normally switch to the forward scanning mode, so that the output stability, reliability and trustworthiness of the shift register unit 101 can be improved.

[0131] Based on the same inventive concept, an embodiment of the present invention further provides a display panel and a display device, including the array substrate described in any of the above embodiments. The display panel may be an organic light-emitting display panel, a micro LED display panel, or a liquid crystal display panel, but is not limited thereto. Fig.24 4 is a schematic diagram of a display device provided by an embodiment of the present invention, and the display device can be optionally applied to an electronic device 400 such as a smart phone, a tablet computer, and a car display screen. It can be understood that any of the above embodiments only provide partial examples or partial structures of the array substrate, and the array substrate also includes other structures in actual applications, which will not be described one by one here. The display device provided by the embodiment of the present invention has all the functions and beneficial effects of the display panel and array substrate described above, and will not be described in detail.

[0132] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An array substrate, characterized in that: include: A scanning circuit, the scanning circuit comprising a multi-stage shift register unit, the shift register unit comprising at least a first input unit, a second input unit, a third input unit and a fourth input unit; The control end of the first input unit is electrically connected to the first trigger end, the input end of the first input unit is electrically connected to the first power end, and the output end of the first input unit is electrically connected to the pull-up node, for responding to the control of the first trigger end and adjusting the potential of the pull-up node according to the first power signal provided by the first power end; The control end of the second input unit is electrically connected to the second trigger end, the input end of the second input unit is electrically connected to the second power supply end, and the output end of the second input unit is electrically connected to the pull-up node, so as to respond to the control of the second trigger end and adjust the potential of the pull-up node according to the second power supply signal provided by the second signal end; The control end of the third input unit is electrically connected to the third trigger end, the input end of the third input unit is electrically connected to the second power supply end, and the output end of the third input unit is electrically connected to the pull-up node, so as to respond to the control of the third trigger end and adjust the potential of the pull-up node according to the second power supply signal provided by the second power supply end; The control end of the fourth input unit is electrically connected to the fourth trigger end, the input end of the fourth input unit is electrically connected to the first power end, and the output end of the fourth input unit is electrically connected to the pull-up node, so as to respond to the control of the fourth trigger end and adjust the potential of the pull-up node according to the first power signal provided by the first power end; The first power signal and the second power signal are electrically different.

2. The array substrate according to claim 1, characterized in that: The shift register unit also includes an output unit, a control end of the output unit is electrically connected to the pull-up node, an input end of the output unit is electrically connected to the first signal end, and an output end of the output unit is electrically connected to the drive output end, for responding to the control of the pull-up node and adjusting the signal of the drive output end according to the first signal provided by the first signal end.

3. The array substrate according to claim 2, characterized in that: The shift register unit also includes a first reset unit, a control end of the first reset unit is electrically connected to the second signal end, an input end of the first reset unit is electrically connected to the first power supply end, and an output end of the first reset unit is electrically connected to the drive output end, for responding to the control of the second signal provided by the second signal end, and adjusting the signal of the drive output end according to the first power supply signal provided by the first power supply end.

4. The array substrate according to claim 1, characterized in that: The input unit comprises a first transistor, a gate of the first transistor is connected to the first trigger terminal, and the first transistor is connected between the first power supply terminal and the pull-up node; The second input unit comprises a second transistor, a gate of the second transistor is connected to the second trigger terminal, and the second transistor is connected between the second power supply terminal and the pull-up node; The third input unit comprises a third transistor, a gate of the third transistor is connected to the third trigger terminal, and the third transistor is connected between the second power supply terminal and the pull-up node; The fourth input unit includes a fourth transistor, a gate of the fourth transistor is connected to the fourth trigger terminal, and the fourth transistor is connected between the first power supply terminal and the pull-up node.

5. The array substrate according to claim 2, characterized in that: The output unit includes a fifth transistor, a gate of the fifth transistor is connected to the pull-up node, and the fifth transistor is connected between the first signal terminal and the driving output terminal.

6. The array substrate according to claim 3, characterized in that: The first reset unit includes a sixth transistor, a gate of the sixth transistor is connected to the second signal terminal, and the sixth transistor is connected between the first power supply terminal and the driving output terminal.

7. The array substrate according to claim 2, characterized in that: The shift register unit also includes a second reset unit, a third reset unit and a node control unit; The control end of the second reset unit is electrically connected to the third signal end, the input end of the second reset unit is electrically connected to the first power end, and the output end of the second reset unit is electrically connected to the pull-up node, so as to respond to the control of the third signal end and adjust the potential of the pull-up node according to the first power signal provided by the first power end; The control end of the third reset unit is electrically connected to the fourth signal end, the input end of the third reset unit is electrically connected to the first power end, and the output end of the third reset unit is electrically connected to the driving output end, so as to respond to the control of the fourth signal end and adjust the signal of the driving output end according to the first power signal provided by the first power end; The control end of the node control unit is electrically connected to the pull-up node and the pull-down node, the input end of the node control unit is electrically connected to the first power supply end, and the output end of the node control unit is electrically connected to the pull-up node, the pull-down node and the driving output end, so as to respond to the control of the first node or the pull-down node and adjust the signals of the pull-up node, the pull-down node and the driving output end according to the first power supply signal provided by the first power supply end.

8. The array substrate according to claim 7, characterized in that: The second reset unit comprises a seventh transistor, a gate of the seventh transistor is connected to the third signal terminal, and the seventh transistor is connected between the first power supply terminal and the pull-up node; The third reset unit comprises an eighth transistor, a gate of the eighth transistor is connected to the fourth signal terminal, and the eighth transistor is connected between the first power supply terminal and the driving output terminal; The node control unit includes a ninth transistor, a tenth transistor and an eleventh transistor, the gate of the ninth transistor is connected to the pull-up node, the ninth transistor is connected between the first power supply terminal and the pull-down node, the gates of the tenth transistor and the eleventh transistor are both connected to the pull-down node, the tenth transistor is connected between the first power supply terminal and the pull-up node, and the eleventh transistor is connected between the first power supply terminal and the drive output terminal.

9. The array substrate according to claim 8, characterized in that: The shift register unit further includes a first capacitor and a second capacitor, wherein the first capacitor is coupled between the pull-up node and the driving output terminal, and the second capacitor is coupled between the pull-down node and the first signal terminal.

10. The array substrate according to claim 2, characterized in that: The scanning circuit includes Y clock signal lines and k*Y trigger lines, wherein k≥1, Y≥2 and are positive integers.

11. The array substrate according to claim 10, characterized in that: The scanning circuit includes a forward scanning mode and a reverse scanning mode.

12. The array substrate according to claim 11, characterized in that: The scanning circuit comprises X-stage shift register units, and each stage of the shift register unit comprises at least one shift output terminal.

13. The array substrate according to claim 12, characterized in that: The shift output terminal multiplexes the drive output terminal.

14. The array substrate according to claim 12, characterized in that: The scanning circuit includes two clock signal lines and two trigger lines, the clock signal lines include a first clock signal line and a second clock signal line, and the trigger lines include a first trigger line and a second trigger line; Wherein, the first trigger end of the first-stage shift register unit of the scanning circuit is connected to the first trigger line, and the second trigger end of the first-stage shift register unit is connected to the second trigger line; The first trigger terminal of the second-stage shift register unit is connected to the second trigger line, and the second trigger terminal of the second-stage shift register unit is connected to the shift output terminal of the first-stage shift register unit.

15. The array substrate according to claim 14, characterized in that: The third trigger end of the X-1th shift register unit of the scanning circuit is connected to the shift output end of the Xth shift register unit, and the fourth trigger end of the X-1th shift register unit is connected to the second trigger line; the third trigger end of the Xth shift register unit is connected to the second trigger line, and the fourth trigger end of the Xth shift register unit is connected to the first trigger line; or, The third trigger end of the X-1th shift register unit is connected to the shift output end of the Xth shift register unit, the fourth trigger end of the X-1th shift register unit is connected to the first trigger line, the third trigger end of the Xth shift register unit is connected to the first trigger line, and the fourth trigger end of the Xth shift register unit is connected to the second trigger line.

16. The array substrate according to claim 12, characterized in that: The scanning circuit includes two clock signal lines and four trigger lines, the clock signal lines include a first clock signal line and a second clock signal line, and the trigger lines include a first trigger line, a second trigger line, a third trigger line and a fourth trigger line; Wherein, the first trigger end of the first-stage shift register unit of the scanning circuit is connected to the first trigger line, and the second trigger end of the first-stage shift register unit is connected to the second trigger line; A first trigger terminal of the second-stage shift register unit is connected to the second trigger line, and a second trigger terminal of the second-stage shift register unit is connected to the shift output terminal of the first-stage shift register unit; The third trigger terminal of the X-1th shift register unit is connected to the shift output terminal of the Xth shift register unit, and the fourth trigger terminal of the X-1th shift register unit is connected to the third trigger line; The third trigger terminal of the X-th stage shift register unit is connected to the third trigger line, and the fourth trigger terminal of the X-th stage shift register unit is connected to the fourth trigger line.

17. The array substrate according to claim 12, characterized in that: The scanning circuit includes four clock signal lines and four trigger lines, the clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the trigger lines include a first trigger line, a second trigger line, a third trigger line and a fourth trigger line; Wherein, the first trigger end of the first-stage shift register unit is connected to the first trigger line, and the second trigger end of the first-stage shift register unit is connected to the second trigger line; The first trigger end of the second-stage shift register unit is connected to the third trigger line, and the second trigger end of the second-stage shift register unit is connected to the fourth trigger line; A first trigger terminal of the third-stage shift register unit is connected to the second trigger line, and a second trigger terminal of the third-stage shift register unit is connected to the shift output terminal of the first-stage shift register unit; The first trigger terminal of the 4th stage shift register unit is connected to the fourth trigger line, and the second trigger terminal of the 4th stage shift register unit is connected to the shift output terminal of the 2nd stage shift register unit.

18. The array substrate according to claim 17, characterized in that: The third trigger terminal of the X-3th shift register unit of the scanning circuit is connected to the shift output terminal of the X-1th bit register unit, and the fourth trigger terminal of the X-3th shift register unit is connected to the first trigger line; The third trigger terminal of the X-2-th shift register unit is connected to the shift output terminal of the X-th shift register unit, and the fourth trigger terminal of the X-2-th shift register unit is connected to the third trigger line; The third trigger terminal of the X-1th stage shift register unit is connected to the first trigger line, and the fourth trigger terminal of the X-1th stage shift register unit is connected to the second trigger line; The third trigger terminal of the X-th stage shift register unit is connected to the third trigger line, and the fourth trigger terminal of the X-th stage shift register unit is connected to the fourth trigger line.

19. The array substrate according to claim 12, characterized in that: The scanning circuit includes four clock signal lines and eight trigger lines, the clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the trigger lines include a first trigger line, a second trigger line, a third trigger line, a fourth trigger line, a fifth trigger line, a sixth trigger line, a seventh trigger line and an eighth trigger line; Wherein, the first trigger end of the first-stage shift register unit is connected to the first trigger line, and the second trigger end of the first-stage shift register unit is connected to the second trigger line; The first trigger end of the second-stage shift register unit is connected to the third trigger line, and the second trigger end of the second-stage shift register unit is connected to the fourth trigger line; The first trigger end of the third-stage shift register unit is connected to the second trigger line, and the second trigger end of the third-stage shift register unit is connected to the shift output end of the first-stage shift register unit; The first trigger end of the 4th stage shift register unit is connected to the fourth trigger line, and the second trigger end of the 4th stage shift register unit is connected to the shift output end of the 2nd stage shift register unit; The third trigger terminal of the X-3th shift register unit is connected to the shift output terminal of the X-1th shift register unit, and the fourth trigger terminal of the X-3th shift register unit is connected to the fifth trigger line; The third trigger terminal of the X-2-th shift register unit is connected to the shift output terminal of the X-th shift register unit, and the fourth trigger terminal of the X-2-th shift register unit is connected to the seventh trigger line; The third trigger terminal of the X-1th stage shift register unit is connected to the fifth trigger line, and the fourth trigger terminal of the X-1th stage shift register unit is connected to the sixth trigger line; The third trigger terminal of the X-th stage shift register unit is connected to the seventh trigger line, and the fourth trigger terminal of the X-th stage shift register unit is connected to the eighth trigger line.

20. An array substrate, characterized in that: The array substrate comprises X-stage shift register units, each stage of the shift register units comprises a forward and reverse scan module, and the forward and reverse scan module comprises a first transistor, a second transistor, a third transistor and a fourth transistor; Wherein, the gate of the first transistor of the nth stage shift register unit is connected to the shift output terminal or trigger line of the n-2ith stage shift register unit, n≤X, i≥1, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode is connected to the pull-up node; The gate of the second transistor of the n-th shift register unit is connected to the shift output terminal of the ni-th shift register unit or the trigger line, the first electrode of the second transistor is connected to the second power supply terminal, and the second electrode is connected to the pull-up node; The gate of the third transistor of the n-th shift register unit is connected to the shift output terminal of the n+i-th shift register unit or the trigger line, the first electrode of the third transistor is connected to the second power supply terminal, and the second electrode is connected to the pull-up node; The gate of the fourth transistor of the nth shift register unit is connected to the shift output terminal of the (n+2i)th shift register unit or the trigger line, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode is connected to the pull-up node.

21. The array substrate according to claim 20, characterized in that: The shift register unit further includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor; Wherein, the gate of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first signal terminal, and the second electrode of the fifth transistor is connected to the driving output terminal; The gate of the sixth transistor is connected to the second signal terminal, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is connected to the driving output terminal; The gate of the seventh transistor is connected to the third signal terminal, the first electrode of the seventh transistor is connected to the first power supply terminal, and the second electrode of the seventh transistor is connected to the pull-up node; The gate of the eighth transistor is connected to the fourth signal terminal, the first electrode of the eighth transistor is connected to the first power supply terminal, and the second electrode of the eighth transistor is connected to the driving output terminal; The gate of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the first power supply terminal, and the second electrode of the ninth transistor is connected to the pull-down node; The gates of the tenth transistor and the eleventh transistor are both connected to the pull-down node, the first electrodes of the tenth transistor and the eleventh transistor are both connected to the first power supply terminal, the second electrode of the tenth transistor is connected to the pull-up node, and the second electrode of the eleventh transistor is connected to the driving output terminal; A first electrode of the first capacitor is connected to the driving output terminal, and a second electrode of the first capacitor is connected to the pull-up node.

22. The array substrate according to claim 21, characterized in that: The shift register unit further includes a second capacitor, a first electrode of the second capacitor is connected to the first signal terminal, and a second electrode of the second capacitor is connected to the pull-down node.

23. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 22.

24. A display device, characterized in that: include: The display panel as claimed in claim 23.

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