Electronic device, storage device, and operation method of storage device

Abstract

The invention relates to an electronic device, a storage device and a storage device operating method. An example storage device includes a first bank, a second bank, a cache controller, and a path selector. The first bank includes a first path group configured to receive power and store a first cache line corresponding to a first address. The second bank includes a second path group configured to receive power and store a second cache line corresponding to a second address. The cache controller is configured to output a second target indicating the second bank based on a power control signal indicating that supply of power to the first bank is stopped and the first address. The path selector is configured to transmit the first address to the second memory bank based on the first address, the power control signal, and the second target.

Description

Technical Field

[0001] The present disclosure relates to a storage device, an electronic device including the storage device, and an operating method of the storage device. Background Art

[0002] Semiconductor memories are widely used to store data in various electronic devices such as computers and wireless communication devices. In static random access memory (SRAM) as a type of semiconductor memory, single-port SRAM and dual-port SRAM that can perform read and write operations at a higher speed than single-port SRAM have been developed. In a typical single-port SRAM, a unit memory cell may include six transistors and perform read and write operations sequentially, while a dual-port SRAM may be configured such that two active transistors are added to a typical single-port SRAM to perform read and write operations in a dual mode, and is used for integrated circuits (ICs) that require ultra-high speed. Summary of the invention

[0003] The present disclosure relates to a memory device for improving refresh operation time, response time, processing speed, and power consumption, an electronic device including the memory device, and an operating method of the memory device.

[0004] In some implementations, a storage device includes: a first storage body, the first storage body including a first path group, the first path group is configured to receive power and store a first cache line corresponding to a first address; a second storage body, the second storage body including a second path group, the second path group is configured to receive power and store a second cache line corresponding to a second address; a cache controller, the cache controller is configured to output a second target indicating the second storage body based on a power control signal indicating to stop supplying power to the first storage body and the first address; and a path selector, the path selector is configured to send the first address to the second storage body based on the first address, the power control signal and the second target.

[0005] In some implementations, a storage device includes: a first storage body, the first storage body including a first path group; a second storage body, the second storage body including a second path group, the second path group is configured to receive power and store a first cache line corresponding to a first address and a second cache line corresponding to a second address; a cache controller, the cache controller is configured to output a first target indicating the first storage body based on a power control signal indicating that power is supplied to the first storage body and the first address; and a path selector, the path selector is configured to send the first address to the first storage body based on the first address, the power control signal and the first target.

[0006] In some implementations, a method for operating a storage device includes: receiving a power control signal, the power control signal indicating whether to supply power to a first storage body group, the first storage body group including at least one of a plurality of storage bodies capable of operating independently; selecting the first storage body group or a second storage body group based on a transaction including an address and the power control signal, the second storage body group including at least one storage body configured to receive power and located among the plurality of storage bodies other than the first storage body group; and sending the transaction to the selected storage body group based on the transaction and the power control signal.

[0007] In some implementations, an electronic device includes: a processor configured to output an operation request and a transaction, the transaction including an address; a power manager configured to generate power and output a power control signal indicating whether power is supplied to a first storage body including at least one storage body; and a memory including multiple storage bodies, a cache controller, and a path selector, the multiple storage bodies being capable of operating independently by receiving power, the cache controller being configured to select a first storage body group or a second storage body group based on the transaction and the power control signal, the second storage body group including at least one storage body configured to receive power and located among the multiple storage bodies except the first storage body group, and the path selector being configured to send the transaction to the selected storage body group based on the transaction and the power control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The implementation will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram of an example of an electronic device.

[0010] Figure 2A , Figure 2B and Figure 2CAn example of selecting a hash function in response to a power control signal is shown.

[0011] Figure 3 , Figure 4 and Figure 5 is a diagram illustrating the operation of an example of a memory.

[0012] Figure 6 is a flow chart of an example of the operation of an electronic device.

[0013] Figure 7 Shows when executing Figure 6 The operation shown in is an example of sending a first transaction to a bank.

[0014] Figure 8 Shows when executing Figure 6 The operation shown in is an example of sending a second transaction to the memory bank.

[0015] Fig. 9 is a flow chart of an example of the operation of an electronic device.

[0016] Fig.10 Shows when executing Fig. 9 The operations shown in FIG. 1 are example implementations of sending transactions to a memory bank.

[0017] Fig.11 is a flow chart of an example of the operation of an electronic device.

[0018] Fig.12 Shows when executing Fig.11 The operations shown in FIG. 1 are example implementations of sending transactions to a memory bank.

[0019] Fig.13 is a block diagram of an example of a way selector.

[0020] Fig.14 , Fig.15 and Fig.16 is a diagram illustrating the operation of an example of an electronic device.

[0021] Fig.17 is a flow chart illustrating examples of cache hit operations and cache miss operations.

[0022] Fig.18 is a block diagram of an example of a memory bank.

[0023] Fig.19 is a circuit diagram of an example of a memory cell.

[0024] Fig. 20 is a flowchart of an example of an operating method of an electronic device. DETAILED DESCRIPTION

[0025] Hereinafter, the implementation will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of an example of the electronic device 10 .

[0027] Reference Figure 1 , the electronic device 10 may include a mobile device such as a smart phone and a wearable device. In this case, the electronic device 10 may be implemented as an application processor (AP) or a system on a chip (SoC). However, the present disclosure is not limited thereto, and the electronic device 10 may be included in a computing device such as a personal computer (PC), a tablet PC, and a server.

[0028] The electronic device 10 may include a processor 110 , a storage device 120 , and a power manager 130 .

[0029] The processor 110 may be a data processing device such as a central processing unit (CPU), a neural processing unit (NPU), a graphics processing unit (GPU), and an AP. The processor 110 may execute an operating system (OS) and / or various application programs. The processor 110 may send a transaction requesting the storage device 120 to perform a specific operation to the storage device 120. In addition, the processor 110 may receive a response to the transaction from the storage device 120. For example, the processor 110 may send a transaction including a read request and an address to the storage device 120, and the storage device 120 may read the data stored in the storage area corresponding to the address. However, the present disclosure is not limited thereto.

[0030] The storage device 120 may perform operations by receiving power from the power manager 130. The storage device 120 may be referred to as a memory. The storage device 120 may include a cache controller 121, a path selector 122, and a plurality of memory banks 123_1, 123_2, ..., and 123_n. The cache controller 121 may receive a transaction provided from the processor 110. The cache controller 121 may send the transaction to a memory bank corresponding to an address included in the transaction to access the memory bank. In some implementations, the cache controller 121 may select a first memory bank group or a second memory bank group from among a plurality of memory banks 123_1, 123_2, ..., and 123_n based on the transaction and the power control signal. The first memory bank group may include at least one memory bank among the plurality of memory banks 123_1, 123_2, ..., and 123_n. The second memory bank group may include the remaining memory banks among the plurality of memory banks 123_1, 123_2, ..., and 123_n except the first memory bank group. In some implementations, the first memory bank group may include at least one memory bank to which power supply may be interrupted when the electronic device 10 is turned on, and the second memory bank group may include at least one memory bank designed to always receive power when the electronic device 10 is turned on. The power control signal may be generated by the power manager 130. The path selector 122 may send a transaction to the selected memory bank group. In some implementations, the path selector 122 may send a transaction to at least one of a plurality of paths included in the selected at least one memory bank based on the transaction and the power control signal sent by the cache controller 121. The number of memory banks 123_1, 123_2, ..., and 123_n may be n. n may be an integer of 2 or greater. Each of the plurality of memory banks 123_1, 123_2, ..., and 123_n may operate independently by receiving power generated by the power manager 130. A memory bank may also be referred to as a slice.

[0031] In some implementations, the storage device 120 may be implemented as a static random access memory (SRAM). The SRAM may be used as a cache in a computing device. To improve the throughput of the data processing amount per unit time of the cache, an independently operable storage body structure may be applied to the SRAM. The storage body structure may be a structure including a cache divided into a plurality of partitions that may be accessed simultaneously. When the SRAM of the storage body structure requires relatively low performance, some storage bodies may be powered off to save power. On the contrary, when the SRAM of the storage body structure requires high performance, power may be supplied to the powered-off storage body. When the power mode is changed, the cache lines mapped to the powered-off storage body may need to be redirected to the powered-on storage body, and may be accompanied by a cache refresh to ensure normal operation. When the number of storage bodies to be operated is reduced, all cache lines of the storage bodies to be powered-off may need to be refreshed. When the number of storage bodies to be operated increases, among the cache lines of the powered-on storage body, the cache lines to be mapped to the newly powered-on storage body may need to be refreshed.

[0032] The power manager 130 may generate power. The power generated by the power manager 130 may be supplied to the processor 110 and / or the storage device 120. In some implementations, the power generated by the power manager 130 may be supplied to at least one of the plurality of storage banks 123_1, 123_2, ..., and 123_n. The power manager 130 may output a power control signal indicating whether power is supplied to a first storage bank group among the plurality of storage banks 123_1, 123_2, ..., and 123_n. In some implementations, the power manager 130 may output a power control signal indicating whether power is supplied to at least one storage bank (e.g., power off or power on). In some implementations, the power manager 130 may output a power control signal indicating a first mode of supplying power only to a specific memory bank (e.g., a first memory bank 123_10 among the plurality of memory banks 123_1, 123_2, ..., and 123_n), a second mode of supplying power to a predetermined number (e.g., n / 2) of memory banks among the plurality of memory banks 123_1, 123_2, ..., and 123_n, or a third mode of supplying power to the plurality of memory banks 123_1, 123_2, ..., and 123_n. According to some implementations, the power manager 130 may be implemented as a power management unit (PMU).

[0033] The storage device 120 of the present disclosure can reduce power consumption and performance degradation in a system that controls power-performance balance by dynamically adapting the cache size. The storage device 120 of the present disclosure can be implemented as an L1 cache or L2 cache of a CPU or an L3 cache of a CPU cluster. Alternatively, the storage device 120 of the present disclosure can be used for a last level cache (LLC) included in a cache and bus interconnect embedded in a GPU or NPU.

[0034] The above implementation can have the effect of increasing the speed of changing the mode to power on or off the memory bank, the effect of improving power consumption, and the effect of improving response time.

[0035] Figure 2A , Figure 2B and Figure 2C An example of selecting a hash function in response to a power control signal is shown.

[0036] Reference Figure 2A , Figure 2B and Figure 2C , the memory 200 may correspond to Figure 1 The memory device 120 includes a cache controller 210 included in the memory 200. The cache controller 210 included in the memory 200 may select any one hash function from among the plurality of hash functions in response to the power control signal. The cache controller 210 may input an address to the selected hash function, and generate and output a target as an output of the selected hash function. In some implementations, the address included in each address group may include information required to check whether the processor 110 requests a block in the cache, and include a tag field and an index field, the tag field including the high bit of the address, and the index field including an index value indicating a specific path among the plurality of paths. The address may also include an offset field, the offset field including the offset value. In this case, the tag field and the index field may be input into the hash function. The memory 200 may include a plurality of memory banks. For example, the memory 200 may include a first memory bank 230_1, a second memory bank 230_2, and a third memory bank 230_3, and the cache controller 210 may include a first hash function 211, a second hash function 212, and a third hash function 213. However, the present disclosure is not limited thereto.

[0037] In some implementations, the power control signal may indicate that power is supplied to at least one of the plurality of memory banks. Figure 2A , Figure 2B and Figure 2C, in an example, the power control signal may indicate that power is supplied to only one of the first storage body 230_1, the second storage body 230_2, and the third storage body 230_3. In another example, the power control signal may indicate that power is supplied to only two of the first storage body 230_1, the second storage body 230_2, and the third storage body 230_3. In yet another example, the power control signal may indicate that power is supplied to all of the first storage body 230_1, the second storage body 230_2, and the third storage body 230_3. However, the present disclosure is not limited thereto. In some implementations, the power control signal may indicate that power is stopped from being supplied to one or both of the three storage bodies. Hereinafter, it is assumed that the power control signal indicates that power is supplied to at least one storage body. In some implementations, the first storage body group according to the present disclosure may include the first storage body 230_1 and the second storage body 230_2, and the second storage body group according to the present disclosure may include the third storage body 230_3.

[0038] Reference Figure 2A, a first power control signal PCS1 may be input into the memory 200. The first power control signal PCS1 may indicate that power is supplied to all of the first memory bank 230_1, the second memory bank 230_2, and the third memory bank 230_3. The cache controller 210 may select the first hash function 211 in response to the first power control signal PCS1. The cache controller 210 may input the first address group ADDa into the first hash function 211, and output a first target TGT1 indicating the first memory bank 230_1 (or representing the first memory bank 230_1). The first address group ADDa may include a plurality of first addresses (e.g., ADDa1, ADDa2, ADDa3, and ADDa4). Each of the first addresses ADDa1, ADDa2, ADDa3, and ADDa4 may correspond to at least one path included in the first memory bank 230_1. As an example only, the number of the first addresses ADDa1, ADDa2, ADDa3, and ADDa4 is shown as 4. The cache controller 210 may input the second address group ADDb to the first hash function 211, and output a second target TGT2 indicating the second memory bank 230_2. The second address group ADDb may include a plurality of second addresses (e.g., ADDb1, ADDb2, ADDb3, and ADDb4). Each of the second addresses ADDb1, ADDb2, ADDb3, and ADDb4 may correspond to at least one path included in the second memory bank 230_2. The cache controller 210 may input the third address group ADDc to the first hash function 211, and output a third target TGT3 indicating the third memory bank 230_3. The third address group ADDc may include a plurality of third addresses (e.g., ADDc1, ADDc2, ADDc3, and ADDc4). Each of the third addresses ADDc1, ADDc2, ADDc3, and ADDc4 may correspond to at least one path included in the third memory bank 230_3. When power is supplied to all the memory banks (eg, the first memory bank 230_1 , the second memory bank 230_2 , and the third memory bank 230_3 ) as described above, a specific address group may be mapped only to a specific memory bank.

[0039] Reference Figure 2B, the second power control signal PCS2 may be input into the memory 200. The second power control signal PCS2 may indicate that power is supplied to two of the first memory bank 230_1, the second memory bank 230_2, and the third memory bank 230_3 (e.g., only the second memory bank 230_2 and the third memory bank 230_3). Because the power supply to the first memory bank 230_1 is interrupted, the first address group ADDa may need to be remapped to another memory bank other than the first memory bank 230_1 (i.e., the second memory bank 230_2 or the third memory bank 230_3). For example, among a plurality of first addresses (e.g., ADDa1, ADDa2, ADDa3, and ADDa4), some first addresses (e.g., ADDa1 and ADDa2) may be mapped to the second memory bank 230_2, and some other first addresses (e.g., ADDa3 and ADDa4) may be mapped to the third memory bank 230_3. The implementation method of mapping some addresses is not limited to Figure 2B The implementation shown in the figure and can be designed in various ways. The cache controller 210 can select the second hash function 212 in response to the second power control signal PCS2. When the first addresses ADDa1 and ADDa2 are input into the cache controller 210, the cache controller 210 can output the second target TGT2 by using the second hash function 212. When some other first addresses (for example, ADDa3 and ADDa4) are input into the cache controller 210, the cache controller 210 can output the third target TGT3 by using the second hash function 212. The case where the second address group ADDb and / or the third address group ADDc are input into the cache controller 210 is the same as described in the above reference. Figure 2A Same as described.

[0040] Reference Figure 2C, the third power control signal PCS3 may be input into the memory 200. The third power control signal PCS3 may indicate that power is supplied to any one of the first memory bank 230_1, the second memory bank 230_2, and the third memory bank 230_3 (e.g., only the third memory bank 230_3). Because the power supply to the first memory bank 230_1 and the second memory bank 230_2 is interrupted, it may be necessary to remap the first address group ADDa and the second address group ADDb to the third memory bank 230_3. For this purpose, the cache controller 210 may select the third hash function 213 in response to the third power control signal PCS3. When the first address group ADDa, the second address group ADDb, or the third address group ADDc is input into the cache controller 210, the cache controller 210 may output the third target TGT3 by using the third hash function 213. When the power supply to at least one memory bank is interrupted as described above, a specific address group may be remapped to a memory bank different from a previously mapped memory bank.

[0041] Although not shown, the cache controller 210 may further include an arbitrator configured to transmit an address or a transaction including an address to a memory bank according to a target.

[0042] Figure 3 , Figure 4 and Figure 5 is a diagram illustrating the operation of an example of a memory. Specifically, Figure 3 shows an implementation in which a first transaction TXNa including an arbitrary first address ADDai is sent to the first memory bank 230_1, and Figure 4 and Figure 5 An implementation manner in which a second transaction TXNb including an arbitrary second address ADDbi is sent to the second memory bank 230_2 is shown.

[0043] Reference Figure 3 , Figure 4 and Figure 5 , the memory 200 may include a cache controller 210, a path selector 220, a first memory bank 230_1 and a second memory bank 230_2. Figure 3 , Figure 4 and Figure 5The memory 200 is shown to include two memory banks, but this illustration is provided only for exemplary description of implementations. In some implementations, the first memory bank 230_1 can be included in the first memory bank group as a memory bank to which power supply can be interrupted, and the second memory bank 230_2 can be included in the second memory bank group as at least one memory bank designed to always receive power when the memory 200 is turned on. Each of the first memory bank 230_1 and the second memory bank 230_2 can operate independently by receiving power PWR. Each memory bank may include multiple paths. For example, the first memory bank 230_1 and the second memory bank 230_2 may each include a first path WAY1, a second path WAY2, a third path WAY3, and a fourth path WAY4. Each of the first memory bank 230_1 and the second memory bank 230_2 has a first path WAY1, a second path WAY2, a third path WAY3, and a fourth path WAY4. Figure 3 , Figure 4 and Figure 52, and the like. The first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 may each include at least one cache line. Tags and data may be stored in each cache line. For example, tags TAG_a1, TAG_a2, TAG_a3, and TAG_a4 and data DATA_a1, DATA_a2, DATA_a3, and DATA_a4 for the first address group ADDa may be stored in the cache lines of the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 included in the first storage body 230_1, respectively. The first address group ADDa may include, for example, four first addresses ADDa1, ADDa2, ADDa3, and ADDa4. In this case, tag TAG_a1 may indicate the first address ADDa1, tag TAG_a2 may indicate the first address ADDa2, tag TAG_a3 may indicate the first address ADDa3, and tag TAG_a4 may indicate the first address ADDa4. For example, tags TAG_b1, TAG_b2, TAG_b3, and TAG_b4 for the second address group ADDb and data DATA_b1, DATA_b2, DATA_b3, and DATA_b4 may be stored in the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 included in the second memory bank 230_2, respectively. Tags TAG_b1, TAG_b2, TAG_b3, and TAG_b4 may indicate the second addresses ADDb1, ADDb2, ADDb3, and ADDb4 included in the second address group ADDb, respectively. The first power control signal PCS1 may be input into the cache controller 210 and the path selector 220. The first power control signal PCS1 may indicate that power is supplied to the first memory bank 230_1 and the second memory bank 230_2. The cache controller 210 may select the first hash function 211.

[0044] Reference Figure 3 , any first address ADDai included in the first transaction TXNa may be mapped to the first memory bank 230_1. That is, the first transaction TXNa may be sent to the first memory bank 230_1. For example, a Figure 1The processor 110 may output a first transaction TXNa including an arbitrary first address ADDai to the memory 200. The cache controller 210 may generate a first target TGT1 indicating the first storage body 230_1 based on the arbitrary first address ADDai and the first hash function 211. In addition, the cache controller 210 may output the first target TGT1 and the first transaction TXNa. In some implementations, the first target TGT1 and the first transaction TXNa may be sent to the path selector 220. The path selector 220 may generate the first path information WI1 based on the first power control signal PCS1, the first target TGT1 and the arbitrary first address ADDai. The path information may include a path to be mapped among multiple paths included in the storage body. For example, the first path information WI1 may indicate any one of the first path WAY1, the second path WAY2, the third path WAY3 and the fourth path WAY4 included in the first storage body 230_1. In some implementations, the first path information WI1 may include a path field. The path field may include information indicating a path to be shielded and a path not to be shielded among a plurality of paths included in the memory bank. The path not to be shielded may be accessed, while the path to be shielded may not be accessed. Figures 8 to 13 to describe the path field. The path selector 220 may output the first path information WI1 and the first transaction TXNa to the first memory bank 230_1. The first memory bank 230_1 may perform an operation according to a request of the first transaction TXNa in a specific path mapped to (or corresponding to) an arbitrary first address ADDai. For example, when the first transaction TXNa includes a read request and a first address ADDa1, the first memory bank 230_1 may determine a cache hit or a cache miss based on a tag TAG_a1 of a cache line stored in the first path WAY1, and read and output data (DATA_a1) when a cache hit occurs.

[0045] Reference Figure 4, any second address ADDbi included in the second transaction TXNb may be mapped to the second memory bank 230_2. That is, the second transaction TXNb may be sent to the second memory bank 230_2. For example, the cache controller 210 may output a second target TGT2 indicating the second memory bank 230_2 based on the arbitrary second address ADDbi and the first hash function 211. In some implementations, the second target TGT2 and the second transaction TXNb may be sent to the path selector 220. The path selector 220 may generate the second path information WI2 based on the first power control signal PCS1, the second target TGT2, and the arbitrary second address ADDbi. For example, the second path information WI2 may indicate any one of the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 included in the second memory bank 230_2. In some implementations, the second path information WI2 may include a path field.

[0046] In some implementations, the path selector 220 may be included in each of the first memory bank 230_1 and the second memory bank 230_2. However, the present disclosure is not limited thereto. In some implementations, the path selector 220 may be included only in a memory bank designed to always receive power. Figure 5 For example, when the second memory bank 230_2 is designed to always receive power when the memory 200 is turned on, the path selector 220 may be included in the second memory bank 230_2. A second transaction TXNb including an arbitrary second address ADDbi may be sent to the second memory bank 230_2. In this case, the path selector 220 may send the second transaction TXNb to the second memory bank 230_2 based on the second target TGT2 to access the second memory bank 230_2.

[0047] Figure 6 is a flow chart of an example of the operation of an electronic device.

[0048] Reference Figure 1 and Figure 6 In operation S110, the storage device 120 may receive a request to power off at least one storage bank. In this case, the request may correspond to the power control signal described above. For example, the power manager 130 may output a power control signal instructing to stop supplying power to the first storage bank group.

[0049] In operation S120, the storage device 120 may refresh at least one memory bank to be powered off. For example, the cache controller 121 may control the first memory bank group in response to the power control signal to refresh the first memory bank group, and the cache line included in the first memory bank group may be refreshed. The refresh operation may include: an operation of reading a tag of a cache line stored in a memory bank, and an operation of moving and storing data of the cache line stored in the memory bank to a memory or a storage device in a lower layer than the storage device 120 by using information included in the tag. As needed, when the information included in the tag does not need to be updated to the memory or storage device in the lower layer due to a state in which a dirty flag is not set, the operation of storing the data of the cache line in the memory or the storage device in the lower layer may be omitted from the refresh operation. The memory hierarchy may include a register, an L1 cache, an L2 cache, an L3 cache, a main memory, and an auxiliary memory included in a processor. For example, when the storage device 120 is an L1 cache, the memory in a layer lower than the storage device 120 may be an L2 cache, an L3 cache, or a main memory, and the storage device in a layer lower than the storage device 120 may be an auxiliary memory. However, the present disclosure is not limited thereto. The main memory may correspond to, for example, a double data rate synchronous dynamic RAM (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, or a Rambus dynamic RAM (RDRAM). The auxiliary memory may correspond to a memory card, a PC card, a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital (SD) card, a universal flash device, a hard disk drive (HDD), or a solid state disk / drive (SSD).

[0050] In operation S130, the storage device 120 may change a hash function in a master configured to generate a transaction request. For example, the master may be the cache controller 121. The cache controller 121 may receive an address, select a hash function as a target from among a plurality of hash functions for outputting hash values ​​according to the request of operation S110, and output a hash value of the selected hash function as a target.

[0051] In operation S140, the power manager 130 may power off at least one memory bank to be powered off. For example, the power manager 130 may stop supplying power to the first memory bank group after the first memory bank group is refreshed.

[0052] Figure 7 Shows when executing Figure 6 An example of sending a first transaction to a memory bank when operating.

[0053] Reference Figure 6 and Figure 7 , before the second power control signal PCS2 is input into the cache controller 210 and the path selector 220, the first memory body 230_1 may include a first path group, which may receive power PWR and store a first cache line corresponding to the first address ADDai in the first path group. The first path group may include a first path WAY1, a second path WAY2, a third path WAY3, and a fourth path WAY4. The second power control signal PCS2 may be input into the cache controller 210 and the path selector 220. The second power control signal PCS2 may indicate that power is supplied to only one of the first memory body 230_1 and the second memory body 230_2 (e.g., the second memory body 230_2). The first memory body 230_1 may refresh the first cache line. In this case, when the tag and data of the first cache line are updated, the data of the first cache line may be stored in a memory (or storage device) in a lower layer. With Figure 7 Unlike that shown in , when the tag and data of the first cache line are maintained without being updated, the data of the first cache line may not be stored in a lower layer memory (or storage device). The supply of power PWR to the first memory body 230_1 may be interrupted. The second memory body 230_2 may include a second path group configured to receive power PWR and store a second cache line corresponding to the second address ADDbi. The second path group may include a first path WAY1, a second path WAY2, a third path WAY3, and a fourth path WAY4. The second cache line corresponding to the second address ADDbi may be, for example, a cache line of the first path WAY1 or a cache line of the second path WAY2 in the second memory body 230_2.

[0054] When the second power control signal PCS2 is input into the memory 200, any first address ADDai may be remapped to the second memory bank 230_2. For example, the cache controller 210 may receive a first transaction TXNa. The first transaction TXNa may include any first address ADDai. The cache controller 210 may select a second hash function 212 in response to the second power control signal PCS2. The cache controller 210 may generate a second target TGT2 indicating the second memory bank 230_2 based on the second hash function 212 and the first transaction TXNa. The cache controller 210 may output the second target TGT2 and the first transaction TXNa to the path selector 220.

[0055] The path selector 220 may send the first transaction TXNa to at least one path of the second memory bank 230_2 based on the first transaction TXNa, the second power control signal PCS2, and the second target TGT2. In some implementations, the path selector 220 may send the first transaction TXNa to at least one path of the second memory bank 230_2 based on the first address ADDai in the first transaction TXNa and the second power control signal PCS2.

[0056] In some implementations, the path selector 220 may generate a second path field WF22 by using an arbitrary first address ADDai, a second power control signal PCS2, and a second target TGT2. In this case, in the second path field WF22, the shielded path MW may be a first path WAY1 and a second path WAY2, and the unshielded path UMW may be a third path WAY3 and a fourth path WAY4. However, the present disclosure is not limited thereto. The number of unshielded paths UMW may be preset. The first path WAY1 and the second path WAY2 may be included in a first path group, and the third path WAY3 and the fourth path WAY4 may be included in a second path group. The second memory bank 230_2 may perform an operation corresponding to the first transaction TXNa by accessing the third path WAY3 and / or the fourth path WAY4. For example, the second memory bank 230_2 may determine a cache hit or a cache miss based on a tag stored in the third path WAY3 and / or the fourth path WAY4. In this case, a cache miss may occur when a tag is not stored in the third way WAY3 and / or the fourth way WAY4 , or when information about an address different from the first address ADDai is stored in the third way WAY3 and / or the fourth way WAY4 .

[0057] Figure 8 Shows when executing Figure 6 The operation shown in is an example of sending a second transaction to the memory bank.

[0058] Reference Figure 6 and Figure 8, when the second power control signal PCS2 is input into the memory 200, the first memory bank 230_1 may refresh the first cache line, and the supply of power PWR to the first memory bank 230_1 may be interrupted. Any second address ADDbi may be remapped to the second memory bank 230_2, and a second transaction TXNb including any second address ADDbi may be sent to the second memory bank 230_2. For example, the cache controller 210 may select the second hash function 212, and generate a second target TGT2 based on the second hash function 212 and any second address ADDbi. The path selector 220 may generate a second path field WF21 based on the second power control signal PCS2 and any second address ADDbi. In the second path field WF21, the unshielded path UMW may be the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4, and the shielded path MW may not exist. That is, the second memory bank 230_2 may be reachable by a first path WAY1 , a second path WAY2 , a third path WAY3 , and a fourth path WAY4 .

[0059] Fig. 9 is a flow chart of an example of the operation of an electronic device.

[0060] Reference Figure 1 and Fig. 9 In operation S210, the storage device 120 may receive a request for powering on at least one storage body. In this case, the request may correspond to the above-mentioned power control signal. The at least one storage body may be, for example, the first storage body 230_1 and included in the first storage body group. For example, before generating a power control signal indicating that power is supplied to the first storage body group, the power manager 130 may stop supplying power to the first storage body group and supply power to the second storage body group. In addition, the power manager 130 may output the power control signal to the storage device 120.

[0061] In operation S220, the power manager 130 may power on at least one memory bank, and the memory device 120 may invalidate a cache line stored in at least one memory bank to be powered on. For example, the power manager 130 may supply power to the first memory bank group. The cache controller 121 may control the first memory bank group in response to the power control signal to invalidate a cache line included in the first memory bank group.

[0062] In operation S230, the storage device 120 may refresh all paths in at least one other memory bank that is not powered off. The at least one other memory bank that is powered off may include, for example, a second memory bank 230_2 and is included in a second memory bank group. For example, after a cache line included in a first memory bank group is invalidated, the cache controller 121 may control a second memory bank group (e.g., a second memory bank 230_2) to refresh a first path WAY1, a second path WAY2, a third path WAY3, and a fourth path WAY4 of the second memory bank 230_2 included in the second memory bank group. In this case, all cache lines included in the second memory bank 230_2 may be refreshed.

[0063] In operation S240, the memory device 120 may change a hash function in a master configured to generate a transaction request. That is, the hash function may be changed so that a first transaction TXNa including an arbitrary first address ADDai is sent to the first memory bank 230_1, and a second transaction TXNb including an arbitrary second address ADDbi is sent to the second memory bank 230_2. For example, the cache controller 210 may select the first hash function 211.

[0064] Fig.10 Shows when executing Fig. 9 The operations shown in FIG. 1 are example implementations of sending transactions to a memory bank.

[0065] Reference Fig. 9 and Fig.10 , the first power control signal PCS1 may be input into the memory 200. The first memory bank 230_1 may receive the power PWR and invalidate the cache lines stored in the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 included in the first memory bank 230_1. In addition, the second memory bank 230_2 may refresh all of the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4.

[0066] When the first power control signal PCS1 is input into the memory 200 , any first address ADDai may be remapped to the first memory bank 230_1 . Fig.10 The implementation shown in the reference Figure 3 The implementation described is the same. In the first path field WF1 output by the path selector 220, the unmasked path UMW may be the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4. The path selector 220 may send the first path field WF1 and the first transaction TXNa to the first memory bank 230_1.

[0067] In with Fig.10 In different implementations shown in the implementation, for example, as shown in the above reference Figure 4 As described, when the path selector 220 is included in the second memory bank 230_2 , the cache controller 210 may transmit the first transaction TXNa to the first memory bank 230_1 according to the first target TGT1 .

[0068] Fig.11 is a flow chart of an example of the operation of an electronic device.

[0069] Reference Figure 1 , Fig. 9 and Fig.11 Operation S210, operation S220 and operation S240 are the same as reference Fig. 9 The operations described are the same.

[0070] In operation S230, the storage device 120 may refresh the predefined path in at least one other storage bank that is not powered off. The at least one other storage bank that is not powered off may be, for example, the second storage bank 230_2, and the predefined path as the unshielded path UMW may be the above referenced Figure 7 The third way WAY3 and the fourth way WAY4 included in the second way group in the second memory bank 230_2 are described. The operation of refreshing the predefined ways may be referred to as a partial refresh.

[0071] Fig.12 Shows when executing Fig.11 The operations shown in FIG. 1 are example implementations of sending transactions to a memory bank.

[0072] Reference Figure 7 , Fig.11 and Fig.12 , when the first power control signal PCS1 is input into the memory 200, the first memory bank 230_1 may receive the power PWR and may invalidate the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 included in the first memory bank 230_1. In addition, the second memory bank 230_2 may partially refresh the predefined paths (e.g., the third path WAY3 and the fourth path WAY4) among the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4. As described above with reference to Figure 7 As described, this may be because a cache line corresponding to an arbitrary second address ADDbi may be stored in the first way WAY1 and the second way WAY2, and a cache line corresponding to an arbitrary first address ADDai may be stored in the third way WAY3 and the fourth way WAY4. In addition, a first transaction TXNa including an arbitrary first address ADDai may be sent to the first memory bank 230_1.

[0073] Fig.13 is a block diagram of an example of the path selector 300 .

[0074] Reference Fig.13 , the path selector 300 may include a hash function 310, a plurality of path field generators, and a path field selector 340. In some implementations, the path field selector 340 may be implemented as a multiplexer. The plurality of path field generators may include a first path field generator 320 and a second path field generator 330, without being limited thereto. In some implementations, at least three path field generators may be included in the path selector 300 according to the number of memory banks and the power control signal.

[0075] The hash function 310 may output a selection signal SEL indicating that any one of the path field generators (e.g., the first path field generator 320 and the second path field generator 330) is selected based on the address ADD and the target TGT. According to some implementations, the hash function 310 may receive the tag field and the index field of the address ADD, and output the selection signal SEL. In some implementations, the hash function 310 may be the same as the first hash function 211 of the cache controller 210. When the address ADD is the first address ADDai, the selection signal SEL may be a first value. When the selection signal SEL is a first value, a value output by each of the first registers 321 and 331 may be selected. When the address ADD is the second address ADDbi, the selection signal SEL may be a second value. When the selection signal SEL is a second value, a value output by each of the second registers 322 and 332 may be selected.

[0076] The first path field generator 320 and the second path field generator 330 may output the value of the previously stored path field. In some implementations, the first path field generator 320 and the second path field generator 330 may each include a plurality of registers and a register selector. The number of registers may be two, but is not limited thereto. In some implementations, at least three registers may be included in each path field generator according to the number of memory banks and the power control signal.

[0077] The first path field generator 320 may generate a path field for mapping the first address ADDai to the first memory bank 230_1 and mapping the second address ADDbi to the second memory bank 230_2. In some implementations, the first path field generator 320 may include a first register 321, a second register 322, and a register selector 323. In some implementations, the register selector 323 may be implemented as a multiplexer. The first register 321 may store a value of a path field WF11 for mapping the first address ADDai to the first memory bank 230_1, and output the value of the path field WF11 to the register selector 323. The second register 322 may store a value of a path field WF12 for mapping the second address ADDbi to the second memory bank 230_2, and output the value of the path field WF12 to the register selector 323. In some implementations, the value of each of the path fields WF11 and WF12 may be bit values ​​b4, b3, b2, and b1. Each bit value may indicate whether each path is shielded. The bit values ​​b4, b3, b2, and b1 may be configured in various forms such as "0001", "0011", "0111", and "1111". The bit value b4 may indicate whether the fourth path WAY4 is shielded, the bit value b3 may indicate whether the third path WAY3 is shielded, the bit value b2 may indicate whether the second path WAY2 is shielded, and the bit value b1 may indicate whether the first path WAY1 is shielded. For example, "0001" may indicate that the second path WAY2, the third path WAY3, and the fourth path WAY4 are shielded, and the first path WAY1 is not shielded. In some implementations in which the path selector 300 is included in the second memory bank 230_2, the first register 321 may be omitted. In some implementations, the path field WF12 may have a value indicating that all of the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4 are not shielded. The register selector 323 may select an output value of the first register 321 or the second register 322 in response to the selection signal SEL. For example, when the selection signal SEL has a first value, the register selector 323 may output the value of the path field WF11 stored in the first register 321. When the selection signal SEL has a second value, the register selector 323 may output the value of the path field WF12 stored in the second register 322.

[0078] The second path field generator 330 may generate a path field for mapping the first address ADDai to some predefined paths (e.g., the third path WAY3 and the fourth path WAY4) in the second memory bank 230_2 and mapping the second address ADDbi to the paths (e.g., the first path WAY1, the second path WAY2, the third path WAY3, and the fourth path WAY4) of the second memory bank 230_2. In some implementations, the second path field generator 330 may include a first register 331, a second register 332, and a register selector 333. In some implementations, the register selector 333 may be implemented as a multiplexer. The first register 331 may store the value of the path field WF21 for mapping the first address ADDai to some predefined paths, and output the value of the path field WF21 to the register selector 333. The second register 332 may store the value of the path field WF22 for mapping the second address ADDbi to the second memory bank 230_2, and output the value of the path field WF22 to the register selector 333. In some implementations, the value of each of the path fields WF21 and WF22 may be a bit value b4, b3, b2, and b1, each of which indicates that each path is shielded. For example, the bit values ​​b4, b3, b2, and b1 of the path field WF21 may correspond to "1100", and the bit values ​​b4, b3, b2, and b1 of the path field WF22 may correspond to "1111". However, the present disclosure is not limited thereto, and the bit value may be set by using various design methods. The register selector 333 may select the output value of the first register 331 or the second register 332 in response to the selection signal SEL.

[0079] The path field selector 340 may select an output value of the first path field generator 320 or the second path field generator 330 as the path field WR in response to the power control signal PCS. For example, when the power control signal PCS is the first power control signal PCS1, the path field selector 340 may output the output value of the first path field generator 320. The first power control signal PCS1 may indicate that power is supplied to the first memory bank 230_1 and the second memory bank 230_2. When the power control signal PCS is the second power control signal PCS2, the path field selector 340 may output the output value of the second path field generator 330. The second power control signal PCS2 may indicate that power is supplied only to the second memory bank 230_2.

[0080] Although not shown, in some implementations like the cache controller 210 , the path selector 300 may select any one of a plurality of hash functions in response to the power control signal PCS and output path information based on the selected hash function and the address ADD.

[0081] Fig.14 , Fig.15 and Fig.16 is a diagram illustrating the operation of an example of the electronic device 400 .

[0082] Reference Fig.14 , Fig.15 and Fig.16 , the electronic device 400 may include a cache using a memory structure. The cache included in the electronic device 400 may include multiple hash functions (e.g., 410 and 430), multiple arbiters (e.g., 420 and 440), and multiple memory bodies (e.g., 450 and 460). According to some implementations, the hash function 410 and the arbiter 420 may be implemented outside the cache. The cache included in the electronic device 400 may perform a hash function based on the address of the cache line by using a request arbitration logic, and determine the memory body to which the address or cache line is assigned. Accordingly, the memory bodies to which the address or cache line is assigned may be distinguished from each other according to the address pattern. When some memory bodies are powered off, the request arbitration logic may be changed so that the cache line assigned to the memory body that is powered off is assigned to another memory body that is powered on. In this case, by refreshing the cache line of the memory body to be powered off, the changed information in the cache may be updated. When the storage body of power failure is powered on again, the request arbitration logic can be restored to the original state so that the address is assigned to the other storage body previously powered on. Among the cache lines of the other storage body previously powered on, it may be necessary to refresh the cache lines to be assigned to the storage body newly powered on, to ensure the normal operation of the cache later. Because the complexity of the operation of searching the cache lines can be high, the method of refreshing all powered-on storage bodies can be used to reduce the complexity. The storage body can be selected based on the result obtained by applying the address value to the hash function hardwired with the CPU from the port and the main port. For example, the mode in which only one storage body is powered on, the mode in which only half of the storage bodies are powered on, or the mode in which all storage bodies are powered on can be selected. Among the hash functions hardwired with the CPU from the port and the main port in the replacement logic included in the specific storage body, the result of the specific hash function can indicate the storage body different from the specific storage body according to the selected mode. In this case, only the defined path can be selected.

[0083] Reference Fig.14 , when the requested address 411 of the transaction is input into the hash function 410, the hash function 410 and the arbitrator 420 may determine whether the transaction is arbitrated by the memory bank 0 450 or the memory bank 1 460. In some implementations, the hash function 410 and the arbitrator 420 may be included in Figure 1450. In some implementations, the hash function 410 and the arbitrator 420 may be implemented as a bridge of the electronic device 400. Through the hash function 410 and the arbitrator 420, the address group A 421 may be arbitrated by the memory bank 0 450 and sent to the memory bank 0 450, and the address group B 422 may be arbitrated by the memory bank 1 460 and sent to the memory bank 1 460. The address group A 421 arbitrated by the memory bank 0 450 may be arbitrated again by the hash function 430 and the arbitrator 440. When the memory bank 1 460 remains powered on, the address group A 441 may be allocated to all paths (i.e., Way0, Way1, Way2, and Way3) included in the memory bank 0 450. The address group B 442 may not be allocated to the memory bank 0 450. When the information 412 indicating that the memory bank 1 460 is powered off is input into the electronic device 400 , the cache line stored in the memory bank 1 460 may be refreshed.

[0084] Reference Fig.15 , information 412 indicating that the bank 1 460 is powered off may be transmitted to the hash function 410 and the hash function 430. Address group B 424 may not be arbitrated by the bank 1 460, but may be arbitrated by the bank 0 450 and transmitted to the bank 0 450 without being transmitted to the bank 1 460. That is, address group A and address group B 423 may be arbitrated by the bank 0 450 and transmitted to the bank 0 450. Through the hash function 430 and the arbiter 440, address group A 441 may be allocated to all paths (i.e., Way0, Way1, Way2, and Way3) included in the bank 0 450, and address group B 443 may be allocated to some predefined paths Way2 and Way3. Address group B 443 may be managed only in some paths Way2 and Way3.

[0085] Reference Fig.16 , information 413 indicating that the memory bank 1 460 is powered on may be input into the electronic device 400. In this case, because the hash function 410 and the arbiter 420 may no longer send the address group B 442 to the memory bank 0 450, all cache lines corresponding to the address group B 442 among all cache lines stored in the memory bank 0 450 may need to be refreshed. For example, only cache lines stored in some predefined paths Way2 and Way3 may be read. Whether the address stored in the cache line corresponds to the address group B may be checked via a tag. In addition, the cache line may be refreshed. However, the present disclosure is not limited thereto, and the process of checking the address using a tag may be omitted to increase the processing speed.

[0086] According to the above implementation, the number of paths for allocating cache lines to storage bodies other than a specific storage body can be preset, and when the specific storage body is changed from a power-off state to a power-on state, only the predefined paths in other storage bodies are refreshed. Therefore, the effect of reducing performance degradation, the effect of reducing response time, the effect of reducing refresh operation time, and the effect of reducing power consumption can be obtained.

[0087] Fig.17 is a flow chart illustrating examples of cache hit operations and cache miss operations.

[0088] Reference Fig.17 , in operation S310, the storage device may receive a transaction request. In operation S320, the storage device may check for cache hits / cache misses. In operation S330, the storage device may determine whether the transaction request is a cache hit. When the transaction request is a cache hit (S330, yes), in operation S340, the storage device may process the transaction request for a cache line hit. When the transaction request is a cache miss (S330, no), in operation S350, the storage device may check the address group by using a hash function used when all storage bodies are powered on. In operation S360, the storage device may determine whether the address group of the transaction request is the address group of the storage body. When the address group of the transaction request is the address group of the storage body (S360, yes), in operation S370, the storage device may select a victim line based on all paths. The victim line may be a cache line in which data stored in a memory or storage in a lower layer is to be stored when a cache miss occurs. When the address group of the transaction request is not the address group of the memory bank (S360, no), the storage device may select a victim line based on a predefined path. In operation S390, the storage device may perform a cache miss operation on the selected victim line.

[0089] Fig.18 is a block diagram of an example of a memory bank.

[0090] Reference Fig.18In a write operation, the memory body 500 may receive a command CMD, an address ADDR, a clock CLK, and input data DATA_IN. For example, the memory body 500 may receive a command CMD, an address ADDR, and input data DATA_IN as a write command, and the input data DATA_IN may be stored in a memory cell region corresponding to the address ADDR in the memory cell array 510. In a read operation, the memory body 500 may receive a command CMD, an address ADDR, and a clock CLK. For example, the memory body 500 may receive a command CMD and an address ADDR as a read command, read data stored in a memory cell region corresponding to the address ADDR, and output the read data to the outside as output data DATA_OUT.

[0091] In some implementations, the memory bank 500 may include a memory cell array 510 , a column decoder 520 , a row decoder 530 , a write driver / sense amplifier 540 , an input / output (I / O) circuit 550 , and control logic 560 .

[0092] The memory cell array 510 may include a plurality of memory cells (MC) 511. The plurality of memory cells 511 may be located at the intersection between a word line WL and a bit line BL. The column decoder 520 may select at least one bit line from among the plurality of bit lines BL based on a column address CA. The row decoder 530 may enable at least one word line from among the plurality of word lines WL based on a row address RA. That is, the row decoder 530 may select at least one word line from among the plurality of word lines WL.

[0093] In a write operation, the write driver / sense amplifier 540 may transmit input data DATA_IN received from the I / O circuit 550 to the column decoder 520. Alternatively, in a read operation, the write driver / sense amplifier 540 may transmit output data DATA_OUT to the I / O circuit 550 by amplifying the data received from the column decoder 520. The I / O circuit 550 may transmit the input data DATA_IN to the write driver / sense amplifier 540. Alternatively, the I / O circuit 550 may output the output data DATA_OUT received from the write driver / sense amplifier 540.

[0094] The control logic 560 may receive a command CMD, an address ADDR, and a clock CLK, and generate a row address RA, a column address CA, and a control signal CTR. For example, the control logic 560 may identify a read command by decoding the command CMD, and generate a row address RA, a column address CA, and a control signal CTR to read output data DATA_OUT from the memory cell array 510. In addition, the control logic 560 may identify a write command by decoding the command CMD, and generate a row address RA, a column address CA, and a control signal CTR to write input data DATA_IN to the memory cell array 510.

[0095] Fig.19 is a circuit diagram of an example of a memory cell.

[0096] Reference Fig.19, when the memory body 500 is included in the SRAM, the memory cell MC may be an SRAM cell including six transistors. The memory cell MC may be referred to as a 6T SRAM cell. The memory cell MC may include a first PMOS transistor P1 and a second PMOS transistor P2 and a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The first PMOS transistor P1 may be connected to a power supply voltage (VDD) line and a first node A, and the second PMOS transistor P2 may be connected between the VDD line and the second node B. The first NMOS transistor N1 may be connected between a ground voltage (VSS) line and the first node A, and the second NMOS transistor N2 may be connected between the ground voltage VSS and the second node B. The first node A may be connected to the gate of each of the second PMOS transistor P2 and the second NMOS transistor N2. The second node B may be connected to the gate of each of the first PMOS transistor P1 and the first NMOS transistor N1. The first node A and the second node B may be connected to the bit line BL and the complementary bit line / BL respectively through the third NMOS transistor N3 and the fourth NMOS transistor N4. The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 may be word lines WL. The third NMOS transistor N3 and the fourth NMOS transistor N4 may be referred to as access transistors or pass transistors. The memory cell MC may store data and complementary data in the first node A and the second node B, and maintain the data and complementary data in a latched state. Specifically, when the word line WL is enabled in a write operation, the data and complementary data sent to the bit line BL and the complementary bit line / BL by the third NMOS transistor N3 and the fourth NMOS transistor N4 may be latched in the first node A and the second node B, respectively. In the memory cell MC, when the word line WL is enabled in a read operation, the data latched in the first node A and the second node B may be sent to the bit line BL and the complementary bit line / BL by the third NMOS transistor N3 and the fourth NMOS transistor N4, respectively. In some implementations, the memory cell MC may include a first inverter and a second inverter. The first inverter may be formed by a first PMOS transistor P1 and a first NMOS transistor N1. The second inverter may be formed by a second PMOS transistor P2 and a second NMOS transistor N2.

[0097] Fig. 20 is a flowchart illustrating an example of an operating method of an electronic device.

[0098] Reference Fig. 20, the operating method of the electronic device may include receiving a power control signal ( S1000 ), selecting a memory bank group ( S2000 ), and sending a transaction to the selected memory bank group ( S3000 ).

[0099] In operation S1000 , the electronic device may receive a power control signal indicating whether to supply power to a first memory bank group including at least one of a plurality of independently operable memory banks.

[0100] In operation S2000, the electronic device may select a first memory bank group or a second memory bank group including remaining memory banks except the first memory bank group among a plurality of memory banks based on a transaction including an address and a power control signal.

[0101] In operation S3000, the electronic device may transmit a transaction to a selected memory bank group based on the transaction and the power control signal.

[0102] In some implementations, in operation S1000, a first power control signal indicating stopping supply of power to the first memory bank group may be sent to the memory device 120. Operation S2000 may include an operation in which the memory device 120 outputs a target indicating at least one memory bank included in the second memory bank group based on a first transaction including a first address corresponding to the first memory bank group and the first power control signal, and an operation in which the memory device 120 selects a path included in at least one memory bank in the second memory bank group based on the first transaction and the target. In this case, the operation method of the electronic device may further include refreshing the first memory bank group.

[0103] In some implementations, in operation S1000, a second power control signal indicating that power is supplied to the first memory bank group may be transmitted to the memory device 120. Operation S2000 may include an operation in which the memory device 120 outputs a target indicating at least one memory bank included in the first memory bank group based on a first transaction including a first address corresponding to the first memory bank group and the second power control signal, and an operation in which the memory device 120 selects a path included in at least one memory bank in the first memory bank group based on the first transaction and the target. In this case, the operation method of the electronic device may further include refreshing the second memory bank group.

[0104] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or on the scope that can be claimed, but rather as descriptions of features that can be specific to a specific implementation of a particular invention. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually in multiple implementations or in any suitable sub-combination. In addition, although features can be described above as working in certain combinations, in some cases, one or more features in a combination can be deleted from the combination, and a combination can involve a sub-combination or a variation of a sub-combination.

[0105] While the present disclosure has been shown and described with reference to implementations thereof, various changes in form and details may be made herein without departing from the spirit and scope of the following claims.

Claims

1. A storage device, comprising: A first memory bank, the first memory bank comprising a first path group, the first path group being configured as Receive power, and storing a first cache line corresponding to a first address; A second memory bank, the second memory bank comprising a second path group, the second path group being configured as Receive power, and storing a second cache line corresponding to a second address; a cache controller configured to output a second target indicating the second memory bank based on a power control signal indicating stopping supply of power to the first memory bank and the first address; as well as A path selector is configured to send the first address to the second memory bank based on the first address, the power control signal, and the second target.

2. The storage device according to claim 1, wherein: The cache controller comprises: A first hash function, wherein the first hash function is configured to receiving the first address, outputting a first target indicative of said first memory bank, receiving the second address, and outputting the second target; and a second hash function configured to output the second target, Among the first hash function and the second hash function, the second hash function is further configured to be selected based on the power control signal.

3. The storage device according to claim 1, wherein: The path selector comprises: A hash function, the hash function being configured as receiving the first address, and Output selection signal; a first path field generator configured to output a first path field that maps the first address to the first path group based on the selection signal and maps the second address to the second path group based on the selection signal; a second path field generator configured to output a second path field, the second path field mapping the first address to some predefined paths in the second path group based on the selection signal, and mapping the second address to the second path group based on the selection signal; and A path field selector is configured to output one of the first path field and the second path field based on a value of the power control signal.

4. The storage device according to claim 3, wherein: The first path field generator comprises: a first register configured to store a first plurality of bit values, the first plurality of bit values ​​comprising mapping information between the first address and the first path group; a second register configured to store a second plurality of bit values, the second plurality of bit values ​​comprising mapping information between the second address and the second path group; and A register selector is configured to output the first plurality of bit values ​​or the second plurality of bit values ​​based on a value of the selection signal.

5. The storage device according to claim 3, wherein: The second path field generator includes: a first register configured to store a first plurality of bit values, the first plurality of bit values ​​comprising mapping information between the first address and the some predefined paths; a second register configured to store a second plurality of bit values, the second plurality of bit values ​​comprising mapping information between the second address and the second path group; and A register selector is configured to output the first plurality of bit values ​​or the second plurality of bit values ​​based on a value of the selection signal.

6. The storage device according to claim 1, wherein: The cache controller is further configured to control the first memory bank to refresh the first cache line based on the power control signal.

7. The storage device according to claim 1, wherein: The cache controller is further configured to output the second target to the path selector based on the second address, and The path selector is further configured to send the second address to the second storage body to access the second storage body based on the second target.

8. The storage device according to claim 1, wherein: The second memory bank includes the path selector.

9. A storage device, comprising: a first storage bank, the first storage bank comprising a first path group; A second memory bank, the second memory bank comprising a second path group, the second path group being configured as Receive power, and storing a first cache line and a second cache line, the first cache line corresponding to a first address and the second cache line corresponding to a second address; a cache controller configured to output a first target indicating the first memory bank based on a power control signal indicating supply of power to the first memory bank and the first address; as well as A path selector is configured to send the first address to the first memory bank based on the first address, the power control signal, and the first target.

10. The storage device according to claim 9, wherein: The cache controller is further configured to control the first memory bank to invalidate a plurality of cache lines stored in the first way group based on the power control signal.

11. The storage device according to claim 9, wherein: The cache controller is further configured to control the second memory bank to refresh at least one cache line based on the power control signal, the at least one cache line being in the second way group.

12. The storage device according to claim 11, wherein: The cache controller is further configured to control the second memory bank to refresh all cache lines in the second way group.

13. The storage device according to claim 11, wherein: The cache controller is further configured to control the second memory bank to refresh the first cache line.

14. The storage device according to claim 9, wherein: The cache controller comprises: A first hash function, wherein the first hash function is configured to receiving the first address, Output the first target, receiving the second address, and outputting a second target indicative of the second memory bank; and a second hash function configured to output the second target, and The cache controller is further configured to select the first hash function based on the power control signal.

15. The storage device according to claim 9, wherein: The path selector comprises: A hash function, the hash function being configured as receiving the first address, and Output selection signal; a first path field generator configured to output a first path field, the first path field mapping the first address to the first memory bank based on the selection signal, and mapping the second address to the second memory bank based on the selection signal; a second path field generator configured to output a second path field, the second path field mapping the first address to some predefined paths in the second path group based on the selection signal, and mapping the second address to the second path group based on the selection signal; and A path field selector is configured to output the first path field or the second path field based on a value of the power control signal.

16. A method for operating a storage device, the method comprising: receiving a power control signal indicating whether to supply power to a first memory bank group, the first memory bank group including at least one memory bank of a plurality of memory banks, the plurality of memory banks being capable of operating independently; selecting the first memory bank group or the second memory bank group based on a transaction and the power control signal, the transaction comprising an address, the second memory bank group comprising at least one memory bank configured to receive power, and at least one memory bank in the second memory bank group being among the plurality of memory banks and different from at least one memory bank in the first memory bank group; as well as Based on the transaction and the power control signal, the transaction is sent to a selected group of memory banks.

17. The method according to claim 16, wherein: Receiving the power control signal includes receiving a first power control signal instructing to supply power to the first memory bank group, and Wherein, selecting the first storage bank group or the second storage bank group includes: outputting a target indicating at least one memory bank in the first memory bank group based on a first transaction and the first power control signal, the first transaction including a first address corresponding to the first memory bank group; and Based on the first transaction and the target, a path included in at least one memory bank in the first memory bank group is selected.

18. The method of claim 17, comprising refreshing the second memory bank group.

19. The method according to claim 16, wherein: Receiving the power control signal includes receiving a second power control signal instructing to stop supplying power to the first memory bank group, and Wherein, selecting the first storage bank group or the second storage bank group includes: outputting a target indicating at least one memory bank in the second memory bank group based on a first transaction and the second power control signal, the first transaction including a first address corresponding to the first memory bank group; and Based on the first transaction and the target, a path included in at least one memory bank in the second memory bank group is selected.

20. The method of claim 19, comprising refreshing the first memory bank group.

21. An electronic device, comprising: a processor configured to output an operation request and a transaction, the transaction including an address; A power manager configured to Generate electricity, and outputting a power control signal indicating whether power is supplied to a first memory bank group, the first memory bank group including at least one memory bank; as well as A memory, the memory comprising a plurality of memory banks, a cache controller and a path selector, the plurality of memory banks being capable of operating independently based on receiving power, the cache controller being configured to select the first memory bank group or the second memory bank group based on the transaction and the power control signal, the second memory bank group comprising at least one memory bank configured to receive power, at least one memory bank in the second memory bank group being among the plurality of memory banks and being different from at least one memory bank in the first memory bank group, and the path selector being configured to send the transaction to the selected memory bank group based on the transaction and the power control signal.

22. The electronic device according to claim 21, wherein: The power manager is further configured to stop supplying power to the first memory bank group and supply power to the second memory bank group before generating a first power control signal, the first power control signal indicating supplying power to the first memory bank group, outputting the first power control signal to the memory, and supplying power to the first memory bank group, and The cache controller is further configured to control the first memory bank group to invalidate a plurality of cache lines included in the first memory bank group based on the first power control signal.

23. The electronic device according to claim 22, wherein: The cache controller is further configured to control the second memory bank group to refresh the second memory bank group based on the plurality of cache lines being invalidated.

24. The electronic device according to claim 23, wherein: The processor is further configured to output a first transaction to the memory, the first transaction including a first address corresponding to the first memory bank group, The cache controller is further configured to output a first target and the first transaction to the path selector based on the first power control signal and the first address, the first target indicating the first memory bank group, and The path selector is further configured to send the first transaction to the first memory bank group based on the first address, the first power control signal, and the first target.

25. The electronic device according to claim 21, wherein: The power manager is further configured to output a second power control signal, the second power control signal instructing to stop supplying power to the first memory bank group, and The cache controller is configured to control the first memory bank group to refresh the first memory bank group in response to the second power control signal.

26. The electronic device according to claim 25, wherein: The power manager is further configured to stop supplying power to the first memory bank group based on the first memory bank group being refreshed.

27. The electronic device according to claim 26, wherein: The processor is further configured to output a first transaction to the memory, the first transaction including a first address corresponding to the first memory bank group, The cache controller is further configured to output a second target and the first transaction to the path selector based on the second power control signal and the first address, the second target indicating the second memory bank group, and The path selector is further configured to send the first transaction to the second memory bank group based on the first address, the second power control signal and the second target.

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