Techniques for identifying self-time and breakpoint of memory

Abstract

The disclosure relates to techniques for identifying self-time and breakpoints of a memory. Certain aspects of the present disclosure include methods for memory processing. The method generally includes determining, via one or more processors, and for each of a different number of each column of memory, a read signal based on at least one calculated slope of a bit line signal during a read window, the read signal indicating a change in the bit line signal during the read window, wherein a plurality of read signals are generated for read signals determined for each of a different number of each column of the memory; a difference between at least two of the plurality of read signals is determined, and a breakpoint within the memory is identified based on the difference between at least two of the plurality of read signals. The method also includes generating a representation of the memory based on the breakpoint.

Description

Technical Field

[0001] The present disclosure relates generally to memory processing, and more particularly to a memory compiler that identifies breakpoints of memory. Background Art

[0002] Memory plays an important role in electronic devices such as smartphones and computers. Memory compilers can be used to efficiently integrate memory into electronic devices. Memory compilers simplify the process of designing and improving memory structures. Memory compilers can be used to automatically generate memory arrays based on predefined specifications. Based on user specifications, memory compilers can provide memory architectures that can be implemented on-chip. Summary of the invention

[0003] A simplified summary of one or more aspects of the present disclosure is presented below to provide a basic understanding of these aspects. This summary is not an exhaustive review of all contemplated features of the present disclosure, and is neither intended to identify key or important elements of all aspects of the present disclosure, nor is it intended to describe the scope of any or all aspects of the present disclosure. Its sole purpose is to present some concepts of one or more aspects of the present disclosure in a simplified manner as a preface to a more detailed description that will be presented later.

[0004] Certain aspects of the present disclosure include a method for memory processing. The method generally includes: determining, via one or more processors, a read signal for each of a different number of each partial column of the memory based on at least one calculated slope of a bit line signal during a read window, the read signal indicating a change in the bit line signal during the read window, wherein the read signal determined for each of the different number of each partial column of the memory produces a plurality of read signals; determining a difference between at least two of the plurality of read signals, and identifying a breakpoint within the memory based on the difference between at least two of the plurality of read signals. The method also includes generating a representation of the memory based on the breakpoint.

[0005] Certain aspects of the present disclosure include an apparatus for memory processing. The apparatus generally includes a memory device. The apparatus also includes one or more processors coupled to the memory device, the one or more processors being configured to: determine, for each of a different number of each partial column of the memory, a read signal based on at least one calculated slope of the bit line signal during the read window, the read signal indicating a change in the bit line signal during the read window, wherein the read signal determined for each of the different number of each partial column of the memory generates a plurality of read signals; determine a difference between at least two of the plurality of read signals; identify a breakpoint within the memory based on the difference between at least two of the plurality of read signals; and generate a representation of the memory based on the breakpoint.

[0006] Certain aspects of the present disclosure include a non-transitory computer-readable medium having instructions stored thereon that, when executed by one or more processors, enable the one or more processors to: determine, for each of a different number of each partial column of a memory, a read signal based on at least one calculated slope of a bit line signal during a read window, the read signal indicating a change in the bit line signal during the read window, wherein the read signal determined for each of the different number of each partial column of the memory produces a plurality of read signals; determine a difference between at least two of the plurality of read signals; identify a breakpoint within the memory based on the difference between the at least two of the plurality of read signals; and generate a representation of the memory based on the breakpoint. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood according to the detailed description given below and the accompanying drawings according to the embodiments of the present disclosure. The accompanying drawings are used to provide an understanding and appreciation of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the accompanying drawings are not necessarily drawn to scale.

[0008] Figure 1 An example memory cell of a static random access memory (SRAM) is illustrated.

[0009] Figure 2 A memory system including a memory array having multiple rows and multiple columns is illustrated.

[0010] Figure 3 is a flow diagram illustrating example operations for memory tuning and breakpoint identification in accordance with certain aspects of the present disclosure.

[0011] Figure 4 is a graph illustrating a bit line (BL) voltage, a complementary BL (BLB) voltage, a word line (WL) voltage, and a complementary sense enable (SAEB) voltage according to certain aspects of the present disclosure.

[0012] Figure 5A is a table illustrating read signals calculated for different per-column portions of a memory in accordance with certain aspects of the present disclosure.

[0013] Figure 5B is a table illustrating calculated read signals for different per-part columns of a memory after RC mismatch reduction, according to certain aspects of the present disclosure.

[0014] Figure 5C is a table illustrating calculated and simulated wordline slopes for different per-column portions of memory in accordance with certain aspects of the present disclosure.

[0015] Figure 5Dis a table illustrating calculated and simulated effective read windows for different per-column portions of memory in accordance with certain aspects of the present disclosure.

[0016] Figure 6 is a flow diagram illustrating example operations for memory processing in accordance with certain aspects of the present disclosure.

[0017] Figure 7 An example collection of processes used during the design, verification, and manufacture of an article of manufacture is illustrated.

[0018] Figure 8 An example computer system with a compiler in accordance with certain aspects of the present disclosure is illustrated. DETAILED DESCRIPTION

[0019] Certain aspects of the present disclosure are directed to a memory compiler for generating a representation of a memory. The memory may include an array of memory cells, such as static random access memory (SRAM) memory cells, as described in detail herein. The memory compiler may calculate a read signal for each partial column of different numbers of memory. Based on the read signal, the compiler may identify breakpoints for the memory. The compiler may perform resistance matching and capacitance matching on different global lines of the memory to reduce the number of breakpoints. The compiler may use breakpoints to tune the memory (e.g., tune the read margin and write margin of the memory). Performing the tuning of the memory may involve various simulations of different parts of the memory based on breakpoints. Therefore, reducing the number of breakpoints results in reducing the simulation overhead of the compiler when tuning the memory.

[0020] Advantages of the present disclosure include, but are not limited to, increasing the efficiency associated with generating memory representations using a memory compiler. Thus, certain aspects provide faster memory design closure (e.g., memory characterization and tuning), reduce machine resources associated with the memory compiler, and improve memory design (e.g., by allowing more efficient tuning of read margins and write margins of the memory).

[0021] Figure 1An example memory cell 100 of an SRAM is illustrated. As shown, the memory cell 100 may include a cross-coupled inverter pair 124 having an output 114 and an output 116. As shown, the cross-coupled inverter pair output 114 is selectively coupled to a bit line (BL) 106 via a pass-gate transistor 102, and the cross-coupled inverter pair output 116 is selectively coupled to a complementary bit line (BLB) 120 via a pass-gate transistor 118. BL 106 and BLB 120 are configured to provide complementary digital signals to be written (e.g., stored) in the cross-coupled inverter pair 124. BL and BLB can be used to store bits in the memory cell 100. As shown, the gates of the pass-gate transistors 102, 118 can be coupled to a word line (WL) 104. For example, a digital signal to be written can be provided to the BL (and a complementary portion of the digital signal is provided to the BLB). Pass-gate transistors 102 , 118 , implemented herein as n-type field effect transistors (NFETs), are then turned on by providing a logic high signal to WL 104 , which causes the digital signal to be stored in the cross-coupled inverter pair 124 .

[0022] The size of any memory is represented by the product of rows and columns, where rows represent the number of WLs and columns represent the number of BLs. Access time and cycle time in embedded memories vary with rows and columns. Changes in rows and columns of memory can be tracked to automatically adjust the self-time associated with the memory. The circuit used to adjust the self-time can be called a self-time circuit, which sometimes includes resistor and capacitor tracking, logic delays, and pull-down circuits. Self-time generally refers to the delay associated with performing certain operations (such as read or write operations) on the memory. For example, a self-time signal (e.g., having a certain self-time pulse width) can be generated to control the read operation of the memory based on the calculated self-time parameters. It is important to reduce such self-time delays to provide faster operation for the memory. Each major activity of memory development (such as self-time tuning, margin closure, and characterization) will increase the number of simulations.

[0023] Creating an embedded memory compiler is a task that involves both design (self-time tuning) and computational resources (simulation). With the increase of column multiplexing, multi-bank memories, and many other options that require a memory compiler to implement, the memory compiler may have to run many simulations to improve (e.g., optimize) the self-time loop.

[0024] Implementing compiler-wide self-time tuning involves performing many simulations and accurate design tuning (e.g., resistor and capacitor (RC) tuning or delay tuning). Self-time tuning parameters (e.g., read signals, also referred to herein as minimum read signals) may be determined in certain aspects of the present disclosure. As described in detail herein, deviations in self-time tuning parameters across rows and columns of memory may be observed to determine design breakpoints for the compiler. For example, as described in detail herein, the number of design breakpoints may be reduced by reducing mismatches between resistor and capacitor values ​​associated with different signals included in the self-tuning.

[0025] Figure 2 A memory system 200 including a memory array having multiple rows and multiple columns is illustrated. Each row may include a row decoder and a WL buffer. The column may be coupled to a column multiplexer (labeled as "column MUX") controlled by a local control buffer. The column may be coupled to a sense amplifier (labeled as "sense Amp") and a write driver. During a read cycle, the sense amplifier may be used to sense (e.g., read) a digital signal on the BL. The sense amplifier may be enabled using an enable signal (e.g., a complementary enable signal labeled as "ENB"). The memory system may include an internal clock (CLK) generation circuit 204 for generating a CLK signal for the memory. The internal CLK from the internal CLK generation circuit 204 may be provided to a reference (REF) WL generator and timer 206, which may generate a reference WL signal (e.g., REF_WL) that may be used to operate the memory system. The CLK generation circuit 204 may receive a memory enable (Mem_En) signal and a write enable (WR_En) signal. The memory system may also include a read / write control circuit 202 for controlling read and write operations of the memory system (e.g., using read (RD) and write (WR) control signals as shown). In some cases, the control circuit 202 may generate a precharge (PRCH) signal that may be used to precharge various nodes of the memory system. As shown, the memory system may also include a global control buffer and various global input / output (I / O) interfaces for columns.

[0026] The user can select various features to be implemented for the memory system 100. For example, Figure 2As shown in , the memory system 100 may include rows for implementing various features, such as for redundancy control, write assist control, and power gating (GPG). The memory system 100 may be implemented without these features. User changes to various features of the memory system affect tuning parameters of the memory system, which may be reanalyzed by the compiler using simulation. Certain aspects of the present disclosure are directed to techniques for efficiently determining self-time tuning parameters, reducing the number of simulations performed by the compiler.

[0027] In some aspects, a large memory array can be divided into different parts based on identified breakpoints. For example, assume a memory with 256 rows and 256 columns. The access time and cycle time of the memory change with the rows and columns. Therefore, in order to effectively tune the memory array, the array can be divided into multiple parts. For example, the memory array can be divided into multiple parts with 32 rows and 32 columns. Each part can be tuned independently. The points at which the memory array is divided into corresponding parts are called breakpoints. Reducing the number of breakpoints (i.e., memory array parts) reduces the number of simulations that must be performed by the compiler to tune the memory array. In certain aspects of the present disclosure, the memory compiler can determine self-calling parameters and provide breakpoints to increase tuning efficiency.

[0028] Figure 3 is a flow chart illustrating example operations 300 for memory tuning and breakpoint identification according to certain aspects of the present disclosure. Operations 300 may be performed, for example, by a memory compiler such as Figure 8 At block 302, the compiler may receive netlist parasitics and bit cell parameters, based on which resistance and capacitance (RC) values ​​for global signals of the memory may be calculated at block 304. Global signals may include, for example, WLs (e.g. Figure 1 The memory may be configured to measure the read signal (e.g., a signal (e.g., a voltage) at a WL of the memory, a signal at a read WL (RWL) of the memory, or a signal at a sense amplifier enable (SAE) line of the memory. For each global signal of the memory, a read signal (e.g., a minimum read signal) may be calculated at block 306 (e.g., based on the calculated delay and slope values). The minimum read signal may be calculated using the following expression:

[0029]

[0030] Where Iread is the bit cell read current (e.g., the current consumption of the bit cell during a read operation), Vdd is the supply voltage of the bit cell, Vth is the device threshold voltage (e.g., the threshold voltage associated with pass-gate transistor 102, pass-gate transistor 118), Cbt@array is the bit line capacitance of the array memory cell, Cbt@io is the bit line capacitance in IO (e.g., the capacitance associated with the IO interface of the bit line), Rows is the total number of word lines of the memory, Vwl_target is the word line level target (e.g., the logic high voltage at WL), and EW is the effective read window. As described in detail herein, the effective read window can refer to the duration from 80% of the WL signal reaching the logic high voltage to 50% of the sense enable signal reaching the logic high voltage. Therefore, during the effective read window, the minimum read signal can correspond to the signal generated at the BLB (or BL) (e.g., the voltage change at the BLB).

[0031] Figure 4 4 is a diagram 400 illustrating a BL signal 404, a complementary BL (BLB) signal 406, a WL signal 402, and a sense enable (SAEB) signal 408 according to certain aspects of the present disclosure. As shown, the WL signal 402 (e.g., the WL voltage) can transition from a logic low to a logic high. Figure 1 As described above, the WL signal 402 transitions to logic high so that the pass-gate transistor is turned on. Therefore, the BLB signal 406 may go low (e.g., depending on the logic state stored in the memory cell). Figure 4 When the SAEB signal 408 in the BL signal 404 reaches 50% of the logic high voltage labeled "Vh"), a certain minimum voltage difference 420 should be reached between the BL signal 404 and the BLB signal 406. The calculated read signal described herein can correspond to the minimum voltage difference 420. The read signal is calculated based on the product of the duration of the effective read window and the slope of the BLB signal 406 during the effective read window. The slope can be the rate of change of the signal at the BLB in millivolts per picosecond.

[0032] In some cases, as shown, the effective read window can be divided into two parts, including a first duration (labeled as "t1") from 80% of the time when the WL signal 402 reaches a logic high voltage to 98% of the time when the WL signal 402 reaches a logic high voltage, and a second duration (labeled as "t2") from 98% of the time when the WL signal 402 reaches a logic high voltage to 50% of the time when the SAEB signal 408 reaches a logic high voltage. In certain aspects of the present disclosure, the read signal can be calculated based on the calculated slope of the BLB signal 406 during the first duration and the calculated slope of the BLB signal 406 during the second duration, thereby providing a more accurate calculation of the read signal. The read signal can be calculated for different numbers of columns per portion (CPS) of the memory array. In other words, different portions of the memory can be considered to have different numbers of columns. For example, as described in detail herein, the read signal can be calculated for 32 columns per portion of the memory, 48 columns per portion of the memory, etc. In the calculation of the slope of the read signal (BLB signal 406), the total capacitance from the top memory group row to the internal net of the sense amplifier can be considered. The read signal can be calculated using the expressions provided herein and used to calculate the deviation at different CPS of the memory array to determine the design breakpoints. For example, returning to reference Figure 3 Based on the read signal calculated at block 306, a design breakpoint may be determined at block 310, as described in more detail with respect to FIG 5. In certain aspects, at block 308, an effective bit line discharge window, a sense amplifier signal excursion, and an effective write window (e.g., together forming an effective read window) may be determined at block 308.

[0033] Figure 5A5 is a table 500 illustrating read signals calculated for different CPS of a memory according to certain aspects of the present disclosure. The read signal may increase as the number of columns in each part increases. As shown, for a CPS of 32, the read signal may be calculated as 71.82, for a CPS of 48, the read signal may be calculated as 73.78, and so on. Table 500 shows continuous Δ values ​​generated based on the calculated read signal. The continuous Δ values ​​correspond to the difference between two continuous read signals. For example, as shown, the difference between a read signal of 73.78 at a CPS of 32 and a read signal of 71.82 at a CPS of 48 provides a Δ value of 1.96. Similarly, as shown, the difference between a read signal of 73.78 at a CPS of 48 and a read signal of 75.78 at a CPS of 64 provides a Δ value of 2.00. The breakpoint of the memory array may be determined based on continuous Δ values. For example, if the delta value is greater than a certain threshold value (e.g., 3 mV), a breakpoint can be set for the corresponding column. In the example shown in table 500, the breakpoint can be set after column 96 because the delta value for a CPS of 122 is 7.22 (e.g., greater than the 3 mV threshold value, as an example).

[0034] Return to reference Figure 3 Once the breakpoints are determined, at block 312, the compiler can determine whether the breakpoints meet certain criteria (e.g., whether the number of breakpoints has dropped to a certain threshold). If not, at block 314, the compiler can reduce the RC mismatch of the memory between global signals (e.g., the mismatch between the WL line and the SAEB line). As described herein, after reducing the RC mismatch, the compiler can recalculate the read signal for a different CPS and output a new breakpoint.

[0035] Figure 5B 5 is a table 550 illustrating read signals calculated for different CPS of a memory after RC mismatch reduction according to certain aspects of the present disclosure. Figure 5B As shown in , the difference between read signals at different CPS is reduced. In this example, the difference between the read signal at a CPS of 160 and the read signal at a CPS of 32 is reduced to 1.3 (e.g., compared to Table 500 where the difference is 32.62). Therefore, by reducing the mismatch, breakpoints may not be needed in this case. As described herein, reducing the number of breakpoints reduces the simulation overhead associated with processing a memory array using a compiler.

[0036] Figure 5C is a table 590 illustrating calculated and simulated word line slopes for different CPS of a memory. Figure 5D592 is a table illustrating effective read windows calculated and simulated for different CPS of a memory. As shown, the simulated and calculated values ​​are correlated for word line signal slope and effective read window. As shown, without performing any simulation using resistance and capacitance values ​​associated with the design signals, a fallback point (e.g., a breakpoint) can be identified for a design (e.g., a calculation formula) using calculated values.

[0037] Return to reference Figure 3 Once the breakpoint is determined and output at block 310, the compiler may perform a characterization of the memory at block 316. For example, the compiler may tune the memory based on the breakpoint. The compiler may analyze different portions of the memory associated with the breakpoint separately to tune the memory (e.g., tune read and write margins) and generate a memory representation.

[0038] Figure 6 600 for memory processing according to certain aspects of the present disclosure. Operation 600 may be performed, for example, by a compiler such as Figure 8 's memory compiler 827) to execute.

[0039] At block 602, the compiler may determine, for each of the different numbers of columns of each portion of the memory (e.g., for the different CPSs shown in FIG. 5 ), a read signal based on at least one calculated slope of the bit line signal during the read window, the read signal (e.g., a minimum read signal) indicating that the bit line signal was at least 100% of the value during the read window (e.g., at least 100% of the value during the read window). Figure 4 The change in the bit line signal may include the difference between the signal at the bit line of the memory and the signal at the complementary bit line of the memory (e.g., Figure 4 4. The difference 420 between the BL signal 404 and the BLB signal 406 is shown in FIG. 4. The read signal determined for each of the different numbers of each partial columns of the memory produces multiple read signals.

[0040] In some aspects, the read window may include a duration from a rising edge of a word line signal of the memory (e.g., WL signal 402) to a rising edge of a sense amplifier enable signal of the memory (e.g., SAEB signal 408). The rising edge of the word line signal may include 80% of the time that the word line signal reaches a logic high voltage, and the rising edge of the sense amplifier enable signal may include 50% of the time that the sense amplifier enable signal reaches a logic high voltage.

[0041] In some aspects, at least one calculated slope may include a slope for a first portion of the read window (eg, Figure 4 t1) and for a second portion of the read window (e.g., at Figure 4 The first portion of the read window may include 80% of the time when the word line signal of the memory reaches a logic high voltage to 98% of the time when the word line signal reaches a logic high voltage. The second portion of the read window may include 98% of the time when the word line signal reaches a logic high voltage to 50% of the time when the sense amplifier enable signal of the memory reaches a logic high voltage.

[0042] At block 604, the compiler may determine a difference between at least two of the plurality of read signals. For example, the at least two of the plurality of read signals may be for each of two consecutive numbers of columns of the memory (e.g., for CPS 32 and CPS 48 as described with respect to FIG. 5).

[0043] At block 606, the compiler identifies a breakpoint within the memory based on a difference between at least two read signals in the plurality of read signals, and generates a representation of the memory based on the breakpoint at block 608. For example, generating the representation of the memory based on the breakpoint may include separately tuning different portions of the memory based on the breakpoint within the memory. In some aspects, the compiler may reduce a resistance or capacitance mismatch between at least two lines of the memory (e.g., a word line and a sense amplifier enable line) prior to determining the plurality of read signals.

[0044] In some aspects, at least one calculated slope can be calculated based on at least one of a read current associated with a bit cell of the memory (e.g., Iread), a power supply voltage for the memory (e.g., Vdd), a threshold voltage of the memory (e.g., Vth), a bit line capacitance associated with the memory (e.g., Cbt@array), a capacitance at a bit line input and output (I / O) interface of the memory (e.g., Cbt@io), a number of word lines of the memory (e.g., Rows), or a word line level target of the memory (e.g., Vwl_target).

[0045] The compiler described herein can use pre-simulation techniques to determine memory self-time breakpoints. For example, as described herein, resistance, capacitance, or bit cell parameters (such as read current and write time) can be used to calculate read signals to determine breakpoints. Certain aspects of the present disclosure reduce the simulation overhead of the compiler and provide design features early in the development stage, thereby reducing the repetition associated with self-time loop closure and improving productivity.

[0046] Certain aspects provide faster design closure and product improvements. The technology described in this article is used to identify design breakpoints and resistance and capacitance specifications before using the extracted netlist to design the tuning cycle, thereby reducing the iteration of self-time closure. For example, compared to traditional compilers, certain aspects improve productivity by reducing the number of breakpoints. Machine resource usage can be reduced by reducing the number of design breakpoints. Reducing the number of breakpoints allows for more efficient tuning of read and write margins. The reduction of design breakpoints also reduces trend mismatches on rows and columns. In some aspects, rebuffer breakpoints can be identified based on RC specifications.

[0047] Figure 7 An example set 700 of processes used during the design, verification, and processing of an article of manufacture such as an integrated circuit is illustrated, which is used to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or multiple operations. The term "EDA" stands for the term "electronic design automation." These processes begin with information provided by a designer to create a product idea 710, which is transformed to create an article of manufacture using a set of EDA processes 712. When the design is finalized, the design is taped out 734, at which time the drawings (e.g., geometric patterns) of the integrated circuit are sent to a foundry to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, the semiconductor die is processed 736, and packaging and assembly processes 738 are performed to produce 740 the finished integrated circuit.

[0048] The specification for a circuit or electronic structure can range from a low-level transistor material layout to a high-level description language. The high-level representation can be used to design circuits and systems using a hardware description language ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be converted to a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation as a more detailed description adds more useful details to the design description (e.g., more details for the modules that comprise the description). The lower-level representation as a more detailed description can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language in a lower-level representation language for specifying a more detailed description is SPICE, which is used to describe in detail circuits with many analog components. The description at each level of representation can be enabled for use by the corresponding tools for that layer (e.g., formal verification tools). The design process can use the Figure 7 The sequence depicted in . The described process is enabled by an EDA product (or EDA tool).

[0049] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction, etc. At this stage, partitioning the design into different types of modules or components may occur.

[0050] During logic design and functional verification 716, modules or components in a circuit are specified in one or more description languages, and the specifications are checked for functional accuracy. For example, components of a circuit can be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components referred to as "simulators" or "prototyping systems" are used to accelerate functional verification.

[0051] During synthesis and design for test 718, the HDL code is converted to a netlist. In some embodiments, the netlist can be a graph structure, wherein the edges of the graph structure represent components of the circuit, and wherein the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0052] During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence to the HDL code. During design planning 722, an overall floorplan for the integrated circuit is constructed and analyzed for timing and top-level routing.

[0053] During layout or physical implementation 724, physical placement (placement of circuit components such as transistors or capacitors) and wiring (connection of circuit components through multiple conductors) occur, and the selection of cells from the library can be performed to enable specific logic functions. As used in this article, the term "cell" can specify a transistor, other components, and interconnected collections that provide Boolean logic functions (such as AND, OR, NOT, XOR) or provide storage functions (such as flip-flops or latches). As used in this article, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components, and are implemented as physical structures and used in simulations. Parameters (such as size) are specified for the selected cells (based on "standard cells"), and these parameters are made accessible in a database for use by EDA products.

[0054] During analysis and extraction 726, circuit functionality is verified at the layout level, which allows refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints (e.g., DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit device functionality matches the HDL design specifications. During resolution enhancement 730, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0055] During tape-out, data is created that will be used for the production of lithography masks (after lithography application enhancements if appropriate).During mask data preparation 732, the "tape-out" data is used to produce lithography masks that are used to produce finished integrated circuits.

[0056] Computer systems (such as Figure 8 The storage subsystem of a computer system) can be used to store programs and data structures and products used by some or all of the EDA products described herein, the stored products being used for development of units of the library and for physical and logical design using the library.

[0057] Figure 8 An example machine of a computer system 800 is illustrated within which a set of instructions may be executed that causes the machine to perform any one or more of the methodologies discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a cloud computing infrastructure or environment.

[0058] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or a machine capable of executing a set of instructions (sequential instructions or other instructions) that specify actions to be taken by the machine. In addition, although a single machine is illustrated, the term "machine" should also be construed to include any combination of machines that individually or jointly execute an instruction set (or multiple instruction sets) to perform any one or more of the methods discussed herein.

[0059] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 818, which communicate with each other via a bus 830.

[0060] The processing device 802 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combined instruction set. The processing device 802 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 802 can be configured to run instructions 826 for performing the operations and steps described herein.

[0061] The computer system 800 may further include a network interface device 808 to communicate with the network 820. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), a letter input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), an image processing unit 822, a signal generating device 816 (e.g., a speaker), an image processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0062] The data storage device 818 may include a machine-readable storage medium 824 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying one or more of the methods or functions described herein. During execution of the instructions 826 by the computer system 800, the instructions 826 may also reside in whole or in part within the main memory 804 and / or within the processing device 802, which also constitute machine-readable storage media.

[0063] In some embodiments, the instructions 826 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 824 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be viewed as including a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more instruction sets. The term "machine-readable storage medium" should also be viewed as including any medium that can store or encode an instruction set executed by a machine and cause the machine and processing device 802 to perform any one or more methods of the present disclosure. The term "machine-readable storage medium" should accordingly be viewed as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0064] In some aspects of the disclosure, the processing device 802 may include a memory compiler 827. According to certain aspects of the disclosure, the memory compiler 827 may generate a representation of a memory.

[0065] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0066] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise indicated, as will be apparent from this disclosure, it should be understood that throughout this specification certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform such data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0067] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each type of medium being coupled to a computer system bus.

[0068] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used together with the program according to the teachings herein, or it may be convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0069] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.

[0070] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to the specific example implementation of the present disclosure. It is apparent that various modifications may be made to these implementations without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. In the case where the present disclosure relates to some elements of singular meaning, more than one element may be depicted in the accompanying drawings, and similar elements are marked with similar numbers. Therefore, the present disclosure and the accompanying drawings should be considered to have illustrative rather than restrictive meanings.

Claims

1. A method for memory processing, comprising: determining, via one or more processors and for each of a different number of each partial column of a memory, a read signal based on at least one calculated slope of a bit line signal during a read window, the read signal indicating a change in the bit line signal during the read window, wherein the read signal determined for each of the different number of each partial column of the memory produces a plurality of read signals; determining a difference between at least two read signals of the plurality of read signals; identifying a breakpoint within the memory based on a difference between the at least two read signals of the plurality of read signals; as well as A representation of the memory is generated based on the breakpoints. 2 . The method of claim 1 , wherein the bit line signal comprises a signal at a complementary bit line of the memory. 3 . The method of claim 1 , wherein generating the representation of the memory based on the breakpoints comprises separately tuning different portions of the memory based on the breakpoints within the memory. 4 . The method of claim 1 , wherein the at least two read signals of the plurality of read signals are directed to two consecutive numbers of each of the partial columns of the memory. 5 . The method of claim 1 , wherein the read window comprises a duration from a rising edge of a word line signal of the memory until a rising edge of a sense amplifier enable signal of the memory.

6. The method according to claim 5, wherein: The rising edge of the word line signal includes 80% of the time that the word line signal reaches a logic high voltage; and The rising edge of the sense amplifier enable signal includes 50% of the time that the sense amplifier enable signal reaches the logic high voltage.

7. The method of claim 1 , wherein the at least one calculated slope comprises: a first calculated slope of the bit line signal for a first portion of the read window; as well as A second calculated slope of the bit line signal for a second portion of the read window.

8. The method according to claim 7, wherein: The first portion of the read window includes 80% of the time that a word line signal of the memory reaches a logic high voltage until 98% of the time that the word line signal reaches the logic high voltage; and The second portion of the read window includes 98% of the time that the word line signal reaches the logic high voltage until 50% of the time that a sense amplifier enable signal of the memory reaches the logic high voltage.

9. The method of claim 1, wherein the change in the bit line signal comprises a difference between a signal at a bit line of the memory and a signal at a complementary bit line of the memory.

10. The method of claim 1 , wherein the at least one calculated slope is calculated based on at least one of: a read current associated with a bit cell of the memory, a supply voltage for the memory, a threshold voltage of the memory, a bit line capacitance associated with the memory, capacitance at a bit line input and output I / O interface for the memory, a number of word lines of the memory, or a word line level target for the memory.

11. The method according to claim 1, further comprising: Before determining the plurality of read signals, a resistance mismatch or a capacitance mismatch between at least two lines of the memory is reduced. 12 . The method of claim 11 , wherein the at least two lines include a word line and a sense amplifier enable line.

13. An apparatus for memory processing, comprising: Storage devices; as well as One or more processors are coupled to the storage device, the one or more processors being configured to: determining, for each of a different number of each partial column of a memory, a read signal based on at least one calculated slope of a bit line signal during a read window, the read signal indicating a change in the bit line signal during the read window, wherein the read signal determined for each of the different number of each partial column of the memory produces a plurality of read signals; determining a difference between at least two read signals of the plurality of read signals; identifying a breakpoint within the memory based on a difference between the at least two read signals of the plurality of read signals; as well as A representation of the memory is generated based on the breakpoints.

14. The apparatus of claim 13, wherein the bit line signal comprises a signal at a complementary bit line of the memory.

15. The device according to claim 13, wherein: To generate the representation of the memory based on the breakpoints, the one or more processors are configured to separately tune different portions of the memory based on the breakpoints within the memory. 16 . The apparatus of claim 13 , wherein the at least two of the plurality of read signals are directed to two consecutive numbers of each of the partial columns of the memory. 17 . The apparatus of claim 13 , wherein the read window comprises a duration from a rising edge of a word line signal of the memory until a rising edge of a sense amplifier enable signal of the memory.

18. The device according to claim 17, wherein: The rising edge of the word line signal includes 80% of the time that the word line signal reaches a logic high voltage; and The rising edge of the sense amplifier enable signal includes 50% of the time that the sense amplifier enable signal reaches the logic high voltage.

19. The apparatus of claim 13, wherein the at least one calculated slope comprises: a first calculated slope of the bit line signal for a first portion of the read window; as well as A second calculated slope of the bit line signal for a second portion of the read window.

20. A non-transitory computer readable medium having stored thereon instructions which, when executed by one or more processors, cause the one or more processors to: determining, for each of a different number of each partial column of a memory, a read signal based on at least one calculated slope of a bit line signal during a read window, the read signal indicating a change in the bit line signal during the read window, wherein the read signal determined for each of the different number of each partial column of the memory produces a plurality of read signals; determining a difference between at least two read signals of the plurality of read signals; identifying a breakpoint within the memory based on a difference between the at least two read signals of the plurality of read signals; as well as A representation of the memory is generated based on the breakpoints.

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