Operation method of memory, memory, memory controller and memory system

Abstract

The invention discloses an operation method of a memory, the memory, a memory controller and a memory system. The memory comprises a memory cell array of a plurality of memory cells, the memory cells store m pieces of bit information, the memory cells store n pieces of effective bit information through m groups of logic page data corresponding to 2n effective data states in 2m preset data states, and preset reading voltages corresponding to the preset data states are set corresponding to each group of logic page data, m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m. The method comprises the following steps of: receiving a reading command, corresponding to the received reading command comprising a prefix command, determining a special reading voltage for reading each valid data state in first to nth groups of logic page data according to the prefix command; the number of special reading voltages of the nth group of logic page data is smaller than the number of preset reading voltages of the nth group of logic page data. The reading frequency is reduced, the reading speed is improved, and the operation performance of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory operation method, a memory, a memory controller and a storage system. Background Art

[0002] The storage cells in the memory include single-level cells that store 1 bit of information and multi-level cells that store at least 2 bits of information. Although the memory with single-level cells has a faster write speed and higher reliability, it has a small storage capacity and high cost; although the memory with multi-level cells has a relatively slower write speed and relatively lower reliability, it has a large storage capacity and low cost.

[0003] The memory has both the fast writing speed and high reliability of a single-level cell and the large storage capacity and low cost of a multi-level cell. Therefore, how to flexibly configure the memory to shorten the data reading time has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a memory operation method, a memory, a memory controller and a memory system, which can shorten the data reading time and improve the response rate of the memory.

[0005] The present application provides a method for operating a memory, wherein the memory includes a memory cell array, wherein the memory cell array includes a plurality of memory cells, wherein the memory cells are used to store m bits of information, wherein the memory cells correspond to 2 m 2 of the preset data states n valid data states to store n valid bits of information, and a preset read voltage corresponding to each preset data state is provided corresponding to each set of logical page data, wherein m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m; the operation method comprises:

[0006] receiving a read command, corresponding to the received read command including a prefix command;

[0007] Determine a special read voltage for reading each valid data state in the first to nth groups of logical page data according to the prefix command;

[0008] The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

[0009] In one embodiment of the present application, the special read voltage of the nth group of logic page data includes: the nth page preset read voltage corresponding to different logic states of the bit information in each adjacent valid data state of the nth group of logic page data.

[0010] In one embodiment of the present application, the preset data state includes preset data, and the steps after receiving the read command include:

[0011] Receive a read command line, and obtain the logical address of the nth group of logical page data to be read according to the received address signal within the address cycle;

[0012] After receiving a command line for starting to execute a read, reading corresponding preset data according to a special read voltage of the nth group of logical page data;

[0013] The steps after determining the special reading voltage include:

[0014] The logic page data is obtained by using a calculation formula corresponding to the prefix command to perform a logic operation on the preset data corresponding to the valid data state read.

[0015] In one embodiment of the present application, it also includes:

[0016] When the difference between n and m is 1, the prefix command includes a first sub-prefix command; wherein the first sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on preset data corresponding to the valid data states;

[0017] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0018] In one embodiment of the present application, it also includes:

[0019] When the difference between n and m is 2, the prefix command includes a second sub-prefix command; wherein the second sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on the preset data corresponding to the valid data states,

[0020] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0021] In one embodiment of the present application, it also includes:

[0022] When the difference between n and m is 3, the prefix command includes a third sub-prefix command C; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data;

[0023] The nth group of logic page data is read from the storage cell array according to the third sub-prefix command, and a copy operation is performed on the nth group of logic page data to generate an (n+1)th group of logic page data.

[0024] In one embodiment of the present application, it also includes:

[0025] In response to the received read command not including the prefix command, m groups of logical page data are read from the memory cell array according to a preset read voltage of the nth group of logical page data.

[0026] In a second aspect, the present application further provides a memory controller, the memory controller is coupled to a memory, the memory includes a memory cell array, the memory cell array includes a plurality of memory cells, the memory cells are used to store m bits of information, the memory cells correspond to 2 through m groups of logical page data m 2 of the preset data states n valid data states to store n valid bits of information, and a preset read voltage corresponding to each preset data state is provided corresponding to each group of logical page data, wherein m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m; the memory controller is configured as follows:

[0027] Sending a read command including a prefix command to the memory, so that the memory determines a special read voltage for reading each valid data state in the first to nth logical pages of data according to the prefix command;

[0028] The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

[0029] In one embodiment of the present application, after sending the read command, the memory controller is configured to:

[0030] Sending a read command line to the memory, and sending an address signal to the memory during an address cycle, so that the memory obtains the logical address of the nth group of logical page data to be read according to the address signal;

[0031] A read command line is sent to the memory to start executing, so that the memory reads the corresponding preset data according to the special read voltage of the nth group of logic page data, and the memory adopts the operation formula corresponding to the prefix command to perform a logical operation on the preset data corresponding to the valid data state read to obtain the logic page data.

[0032] In one embodiment of the present application, the preset data state includes preset data, the prefix command includes a first sub-prefix command, the first sub-prefix command indicates to read the preset data corresponding to the three valid data states of the nth group of logical page data from the memory cell array for logical operation, the difference between n and m is 1, and the memory controller is configured as follows:

[0033] The first sub-prefix command is sent to the memory, so that the memory reads 2 from the memory cell array according to the n special read voltages of the nth group of logical page data and the first sub-prefix command. n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0034] In one embodiment of the present application, the prefix command includes a second sub-prefix command, the second sub-prefix command instructs to read the preset data corresponding to the two valid data states of the nth group of logical page data from the memory cell array for logical operation, and the difference between n and m is 2; the memory controller is further configured as:

[0035] The second sub-prefix command is sent to the memory, so that the memory reads 2 from the memory cell array according to the n special read voltages of the nth group of logical page data and the second sub-prefix command. n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0036] In one embodiment of the present application, the prefix command includes a third sub-prefix command C; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data, and the difference between n and m is 3;

[0037] The memory controller is specifically configured to: send the third sub-prefix command to the memory, so that the memory reads the nth group of logical page data from the storage cell array according to the third sub-prefix command, and performs a copy operation on the nth group of logical page data to generate the n+1th group of logical page data.

[0038] In a third aspect, the present application further provides a memory, the memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells, the memory cells being used to store m bits of information, the memory cells corresponding to 2 through m groups of logical page data m 2 of the preset data states n The memory is configured as follows:

[0039] Corresponding to the received read command including a prefix command, a special read voltage for reading each valid data state in the first to nth groups of logical page data is determined according to the prefix command; n is a positive integer greater than 1 and less than or equal to m;

[0040] Reading corresponding data from the storage unit according to the special read voltage;

[0041] The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

[0042] In one embodiment of the present application, the special read voltage of the nth group of logic page data includes: the nth page preset read voltage corresponding to different logic states of the bit information in each adjacent valid data state of the nth group of logic page data.

[0043] In one embodiment of the present application, the preset data state includes preset data, and after receiving the read command, the memory is further configured as:

[0044] Receive a read command line, and obtain the logical address of the nth group of logical page data to be read according to the received address signal within the address cycle;

[0045] After receiving a command line for starting to execute a read, reading corresponding preset data according to a special read voltage of the nth group of logical page data;

[0046] The steps after determining the special reading voltage include:

[0047] The logic page data is obtained by using a calculation formula corresponding to the prefix command to perform a logic operation on the preset data corresponding to the valid data state read.

[0048] In one embodiment of the present application, the memory is further configured as:

[0049] When the difference between n and m is 1, the prefix command includes a first sub-prefix command; wherein the first sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on preset data corresponding to the valid data states;

[0050] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0051] In one embodiment of the present application, the memory is further configured as:

[0052] When the difference between n and m is 2, the prefix command includes a second sub-prefix command; wherein the second sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on the preset data corresponding to the valid data states,

[0053] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0054] In one embodiment of the present application, the memory is further configured as:

[0055] When the difference between n and m is 3, the prefix command includes a third sub-prefix command C; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data;

[0056] The nth group of logic page data is read from the storage cell array according to the third sub-prefix command, and a copy operation is performed on the nth group of logic page data to generate an (n+1)th group of logic page data.

[0057] In one embodiment of the present application, the memory is further configured as:

[0058] In response to the received read command not including the prefix command, m groups of logical page data are read from the memory cell array according to a preset read voltage of the nth group of logical page data.

[0059] In a fourth aspect, the present application further provides a storage system, comprising one or more memories as described in the third aspect and the memory controller as described in the second aspect, wherein the memory controller is coupled to the memory and is configured to control the memory.

[0060] Due to the adoption of the above technical solution, the present application has the following significant advantages: receiving a read command, corresponding to the received read command including a prefix command, determining a special read voltage for reading each valid data state in the first to nth groups of logical page data according to the prefix command, since the number of special read voltages for the nth group of logical page data is less than the number of preset read voltages for the nth group of logical page data, the number of reads corresponding to the prefix command according to the special read voltage for the nth group of logical page data is less than the number of reads originally according to the preset read voltage for the nth group of logical page data. In this way, the number of data reads for the nth group of logical page data can be reduced by reducing the number of read voltages used, thereby saving the read time of the read operation, which is conducive to improving the read speed and the operating performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0062] Figure 1 A schematic diagram of an exemplary memory device according to some aspects of the present application is shown.

[0063] Figure 2 A schematic flow chart of a memory operation method according to some aspects of the present application is shown.

[0064] Figure 3 A schematic diagram of a memory executing a read command according to an embodiment of the present application is shown;

[0065] Figure 4 A timing diagram of a memory performing a read operation according to an embodiment of the present application is shown;

[0066] Figure 5 A schematic diagram of a Gray code lookup table according to an embodiment of the present application is shown;

[0067] Figure 6 A schematic diagram showing the distribution of threshold voltage and data state of a QLC used as TLC according to an embodiment of the present application is shown;

[0068] Figure 7A schematic diagram showing a QLC used as a valid data state corresponding to UP in TLC according to an embodiment of the present application is shown;

[0069] Figure 8 A schematic diagram showing the distribution of threshold voltage and data state of a QLC used as an MLC according to an embodiment of the present application is shown;

[0070] Fig. 9 A schematic diagram showing a QLC used as a valid data state corresponding to an MP in an MLC according to an embodiment of the present application is shown;

[0071] Fig.10 A schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0072] Fig.11 A schematic diagram of an exemplary memory device card having a memory system according to some aspects provided by the present application;

[0073] Fig.12 is a schematic diagram of an exemplary solid-state drive (SSD) having a storage system according to some aspects of the present application. DETAILED DESCRIPTION

[0074] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0075] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0076] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0077] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0078] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0079] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0080] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0081] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0082] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0083] Figure 1A schematic diagram of an exemplary memory 30 including a peripheral circuit 302 is shown. The memory 30 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, in which memory cells 306 are arranged in the form of an array of NAND memory strings 308, wherein each NAND memory string 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0084] like Figure 1 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and the DSG 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read and written from the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding DSG 312 via one or more DSG lines 313 and / or applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG 310) or a deselect voltage to a corresponding SSG 310 via one or more SSG lines 315.

[0085] like Figure 1As shown, the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit with an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage Vers (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 receives read and program operations. In some embodiments, the memory cells 306 coupled to the same word line 318 are referred to as a memory page 320. The memory page 320 is a basic data unit for a programming operation or a read operation, and the size of a memory page 320 in bits may be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding memory page 320 and a gate line coupling the control gates.

[0086] In some embodiments, each storage cell 306 is a single-level cell (SLC) having two possible data states and can therefore store one bit of data. A multi-level cell 306 (MLC) can store two bits of data, a triple-level cell 306 (TLC) stores three bits of data, or a quad-level cell 306 (QLC) stores four bits of data, or a penta-level cell 306 (PLC) stores four bits of data. As the capacity of NAND Flash increases, the number of bits of data stored in the storage cell 306 also increases. That is, the number of threshold voltage distributions corresponding to different data states of SLC→MLC→TLC→QLC→PLC increases, and multiple data states include an erased state and 2 m -1 programming state, m is the maximum number of bits of data that the memory cell 306 can store.

[0087] Due to the demand for higher storage capacity, the memory cells in NAND flash memory devices are configured to be able to store more than 1 bit of memory data. NAND memory cells can have 2 mdata states (e.g., charge ranges), and thus can store m bits of data.

[0088] In 2 m The data state can include an erase state and 2 m -1 programming state. NAND flash memory can program and / or read data page by page. During the programming operation, the NAND flash memory cell is programmed to have 2 m data states and writes m bits of data into the QLC NAND flash memory cell as one of these states. Each word line in the memory block is coupled to multiple pages of NAND flash memory cells, so that one page of NAND flash memory cells can store m pages of data. For example, SLC NAND flash memory cells can store 1 page of data, NAND flash memory cells can store 2 pages of data, TLC NAND flash memory cells can store 3 pages of data, and QLC NAND flash memory cells can store 4 pages of data, and so on.

[0089] Exemplarily, a storage cell of an SLC memory stores 1 bit of information, and the data states of the SLC memory include 1 erased state and 1 programmed state, the erased state is denoted as E, and the programmed state is denoted as P, the threshold voltage of the programmed state P is greater than the threshold voltage of the erased state E, and 1 page of data can be lower-level page data (LP).

[0090] The storage unit of the MLC memory stores 2 bits of information. The data states of the MLC memory include 1 erased state and 3 programmed states. The erased state is denoted as E, and the programmed states are denoted as P1, P2 and P3 from the 1st state to the 3rd state. From the P1 state to the P3 state, the threshold voltage gradually increases. The 2 pages of data can be the lower page data (LP) and the middle page data (MP), respectively.

[0091] The storage unit of the TLC memory stores 3 bits of information. The data states of the TLC memory include 1 erased state and 7 programmed states. The erased state is denoted as E, and the programmed states are denoted as P1, P2, P3, P4, P5, P6 and P7 from the 1st state to the 7th state. From the P1 state to the P7 state, the threshold voltage gradually increases. The 3 pages of data can be lower page data (LP), middle page data (MP) and upper page data (UP), respectively.

[0092] The storage unit of the QLC memory stores 4 bits of information. The data states of the QLC memory include 1 erased state and 15 programmed states. The erased state is denoted as E, and the programmed states are denoted as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 from the 1st state to the 15th state. From the P1 state to the P15 state, the threshold voltage gradually increases. The 4 pages of data can be lower page data (LP), middle page data (MP), upper page data (UP) and extra page data (XP), respectively.

[0093] The NAND memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit can write m groups of logical page data and the m+1th group of logical page data into the memory cell array, and can generate 2 n Different data states can be used to use part of the memory cells as at least one of SLC, MLC, TLC, and QLC. In this way, the NAND memory can be flexibly configured to achieve a variety of storage cell bit numbers and have the advantages of fast writing speed, high reliability, large storage capacity, and low cost. However, the reading rate of the memory data is not optimized.

[0094] The NAND memory of the present application is only one example of the memory 30. The memory 30 may include any suitable solid-state, non-volatile storage device, such as NOR flash memory, FeRAM, PCM, MRAM, or RRAM.

[0095] This application further proposes that Figure 2 The exemplary embodiment shown in the figure is a memory operation method, wherein the memory includes a memory cell array, the memory cell array includes a plurality of memory cells, the memory cells are used to store m bits of information, and the memory cells correspond to 2 m 2 of the preset data states n The memory is configured to store n valid bits of information by using a valid data state, and a preset read voltage corresponding to each preset data state is set corresponding to each group of logical page data, wherein m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m; the memory is configured to perform the following steps: Figure 2 The process shown in the figure, the process of the memory operation method includes the following steps:

[0096] S100: Receive a read command, wherein the received read command includes a prefix command.

[0097] S200, determining a special read voltage for reading each valid data state in the first to nth groups of logic page data according to the prefix command; wherein the number of special read voltages for the nth group of logic page data is less than the preset number of read voltages for the nth group of logic page data.

[0098] In some examples, the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array includes multiple memory cells, each memory cell can store m bits of information, for example, the memory is an MLC memory, that is, m=2, for another example, the memory is a TLC memory, that is, m=3, for another example, the memory is a QLC memory, that is, m=4; the peripheral circuit includes a logic control unit, a command register, a cache register, and a data register, etc.

[0099] In the embodiment of the present application, the m groups of logical page data include at least one of LP logical page data, MP logical page data, UP logical page data, and XP logical page data. m The preset data states include 1 erase state and 2 m- 1 programming state. Among them, the SLC flash memory cell can have 2 preset data states, so it can store 1 bit of data; the MLC flash memory cell can have 4 preset data states, so it can store 2 bits of data; the TLC flash memory cell can have 8 preset data states, so it can store 3 bits of data; the QLC flash memory cell can have 16 preset data states, so it can store 4 bits of data, and so on. For the memory, it can be programmed from 2 m Select 2 from the preset data states n The preset data states are used as valid data states for storing n valid bits of information. Different groups of logical page data are set to have corresponding 2 m The preset data states each correspond to a preset read voltage.

[0100] In one example, the memory is an MLC memory, and the MLC memory can correspond to 2 sets of logical page data. 2 = 4 preset data states to store 2 bits of information. When part of the storage cells in the MLC memory needs to be used as SLC, the peripheral circuit writes the LP logic page data and the MP logic page data into the storage cell array according to the write command, and 1 valid bit of information can be stored in part of the storage cells of the MLC memory, and 2 1 = 2 different valid data states, that is, m = 2, n = 1. In this way, at least part of the memory cells in the MLC memory can be used as SLC to meet the application requirements of the SLC memory.

[0101] In one example, the memory is a TLC memory, and the TLC memory can correspond to 2 of the 3 sets of logical page data. 3= 8 preset data states to store 3 bits of information. When part of the storage cells in the TLC memory needs to be used as MLC, the peripheral circuit writes the LP logic page data, the MP logic page data and the UP logic page data into the storage cell array according to the write command, and 2 valid bits of information can be stored in part of the storage cells of the TLC memory, and 2 2 = 4 different valid data states, that is, m = 3, n = 2. In this way, at least part of the memory cells in the TLC memory can be used as MLC to meet the application requirements of the MLC memory.

[0102] In one example, the memory is a TLC memory, and the TLC memory can correspond to 2 of the 3 sets of logical page data. 3 = 8 preset data states to store 3 bits of information. When part of the storage cells in the TLC memory needs to be used as SLC, the peripheral circuit writes the LP logic page data and the MP logic page data into the storage cell array according to the write command, and 1 valid bit of information can be stored in part of the storage cells of the TLC memory, and 2 1 = 2 different valid data states, that is, m = 3, n = 1. In this way, at least part of the storage cells in the TLC memory can be used as SLC to meet the application requirements of the SLC memory.

[0103] In one example, the memory is a QLC memory, and the QLC memory can correspond to 2 4 = 16 preset data states to store 4 bits of information. When part of the storage cells in the QLC memory needs to be used as TLC, the peripheral circuit writes the LP logic page data, MP logic page data, UP logic page data and XP logic page data into the storage cell array according to the write command, and 3 valid bits of information can be stored in part of the storage cells of the QLC memory, and 2 3 = 8 different valid data states, that is, m = 4, n = 3. In this way, at least part of the memory cells in the QLC memory can be used as TLC to meet the application requirements of the TLC memory.

[0104] In one example, the memory is a QLC memory, and the QLC memory can correspond to 2 4 = 16 preset data states to store 4 bits of information. When part of the storage cells in the QLC memory needs to be used as MLC, the peripheral circuit writes the LP logic page data, the MP logic page data and the UP logic page data into the storage cell array according to the write command, and 2 valid bits of information can be stored in part of the storage cells of the TLC memory, and 2 2 = 4 different valid data states, that is, m = 4, n = 2. In this way, at least part of the memory cells in the QLC memory can be used as MLC to meet the application requirements of the MLC memory.

[0105] In one example, the memory is a QLC memory, and the QLC memory can correspond to 2 4 = 16 preset data states to store 4 bits of information. When part of the storage cells in the QLC memory needs to be used as SLC, the peripheral circuit writes the LP logic page data and the MP logic page data into the storage cell array according to the write command, and 1 valid bit of information can be stored in part of the storage cells of the QLC memory, and 2 1 = 2 different valid data states, that is, m = 4, n = 1. In this way, at least part of the storage cells in the QLC memory can be used as SLC to meet the application requirements of the SLC memory.

[0106] In some embodiments, before reading data from the memory, it is necessary to program the storage power supply of the memory to write data. One method of programming and writing data may be that the peripheral circuit determines the n+1th group of logical page data according to the received prefix command and the received n groups of logical page data; wherein n is a positive integer, and n+1 is a positive integer less than or equal to m. The n groups of logical page data and the n+1th group of logical page data are written into the memory cell array to generate 2 n For the specific programming writing method, please refer to the prior application with publication number CN115527587A.

[0107] In some embodiments, the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit includes a logic control unit, a command register, a page buffer, a cache register, and a data register.

[0108] In step S100, the memory may receive a read command sent by the memory controller. If the read command received by the memory includes a prefix command, it indicates that part of the memory cells are used as at least one or more of SLC, MLC, and TLC. The logic control unit in the peripheral circuit of the memory may read the prefix command in the read command stored in the command register.

[0109] In step S200, the logic control unit in the peripheral circuit of the memory may control the memory according to the prefix command and the 2 stored in the cache register or the data register. mA preset data state is used to determine the special read voltage for reading each valid data state in the first to nth groups of logical page data. In this way, the storage controller can read the corresponding data from the memory according to the special read voltage corresponding to the prefix command. Since the number of special read voltages for the nth group of logical page data is less than the preset number of read voltages for the nth group of logical page data, the number of reads corresponding to the prefix command according to the special read voltage of the nth group of logical page data is less than the number of reads originally according to the preset read voltage of the nth group of logical page data. The first to nth groups of logical page data include at least a first group of logical page data, a second group of logical page data, a third group of logical page data, and a fourth group of logical page data. For the convenience of explanation, in the embodiment of the present application, the first group of logical page data is set to be LP logical page data, the second group of logical page data is set to be MP logical page data, the third group of logical page data is set to be UP logical page data, and the fourth group of logical page data is set to be XP logical page data.

[0110] In some embodiments, the read data may be directly temporarily stored in the page buffer and then output to the receiving end. The receiving end may include the same memory controller as the one that sends the read command, or may include an electronic device, such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player and / or a digital video recorder and a digital video player. In some embodiments, the host may include a portable electronic device, such as a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player, and a portable game console.

[0111] In the embodiment disclosed in the present application, when some storage units of the memory are used as SLC, MLC, and TLC without structurally modifying the storage units, since the number of special read voltages for the nth group of logic page data is less than the number of preset read voltages for the nth group of logic page data, the number of reads corresponding to the prefix command according to the special read voltage for the nth group of logic page data is less than the number of reads originally according to the preset read voltage for the nth group of logic page data. In this way, the number of data reads for the nth group of logic page data can be reduced by reducing the number of read voltages used, thereby saving the read time of the read operation, which is conducive to improving the read speed and the operating performance of the memory.

[0112] In some embodiments, the special read voltage of the nth group of logic page data includes: a preset read voltage of the nth page corresponding to different logic states of the bit information in adjacent valid data states of the nth group of logic page data.

[0113] Specifically, storage unit 2 m Each preset data state corresponds to 2m -1 preset read voltage, where 2 m -1 preset read voltage is configured according to the preset read voltage corresponding to the logical page data of different layers. The preset read voltage of the present application is essentially the threshold voltage for reading data. In order to determine the storage state of the storage cell and read out the data stored therein, for SLC, a read operation is performed on the selected word line. After applying a read voltage on the word line, the data can be sensed, and the data stored in the corresponding storage cell can be read out. However, for storage cells that store multi-bit information such as MLC and TLC, since each storage cell has more than two storage states, it is necessary to perform multiple consecutive read operations on the same storage cell and apply multiple read voltages of different sizes on the word line to sense the stored data, so that the actual storage state of the storage cell can be determined and the data stored in the storage cell can be read out. In other words, a NAND storage cell can have 2 m preset data states (e.g., charge ranges), and uses 2 m -1 preset read voltage to read the data.

[0114] Since the present application can increase the number of storage bits of some storage units of the memory to "SLC" bits, "MLC" bits, "TLC" bits or even more bits without making structural changes to the storage units, the application scenarios of the storage device are greatly enriched. In this way, the first to nth groups of logical page data can include 2 n valid data states, each group of logic page data includes a corresponding number of valid data states, and the logic state of the bit information in the corresponding adjacent valid data states is searched from the same logic page data, and the preset read voltage between the changes in the logic state of the bit information is used as the special read voltage.

[0115] like Figure 8 As shown, taking QLC as MLC as an example, it has 2 4 = 16 preset data states, then its valid data states include 2 2 = 4 valid data states. Figure 3 As shown, the memory reads the MP logical page data including Figure 8There are a total of 4 valid data states, namely R3, R7, R9 and R13, because among the 4 valid data states, only the logic state of the bit information of 2 valid data states, R3 and R13, changes between each other, that is, the valid data state between adjacent R7 and R9 corresponds to the bit information of the MP logic page data is "0", and no change in the logic state occurs, while the valid data state between adjacent R3 and R7 corresponds to the bit information of the MP logic page data changes from "1" to "0", and the valid data state between adjacent R9 and R13 corresponds to the bit information of the MP logic page data changes from "0" to "1", therefore, the MP logic page data can be read according to the preset read voltage corresponding to R3 and R13.

[0116] In some embodiments, the preset data state includes preset data, and the steps after receiving the read command include:

[0117] Receive a read command line, and obtain the logical address of the nth group of logical page data to be read according to the received address signal within the address cycle;

[0118] After receiving a command line for starting to execute a read, the corresponding preset data is read according to n special read voltages of the nth group of logic page data; the n special read voltages are preset read voltages corresponding to the logic states of the preset data between adjacent valid data states;

[0119] The steps after determining the special reading voltage include:

[0120] The logic page data is obtained by using a calculation formula corresponding to the prefix command to perform a logic operation on the preset data corresponding to the valid data state read.

[0121] Specifically, Figure 3 As shown, taking QLC memory as an example, Figure 3 As shown in (a), the QLC memory receives a read command line (e.g., 00h) to read the preset data corresponding to all preset data states from the QLC memory. Figure 3 As shown in (b), the QLC memory receives the first sub-prefix command A and a read command line (eg, 00h) to read the preset data corresponding to the valid data state from the logical address used as TLC in the QLC memory. Figure 3 As shown in (c), the QLC memory receives the second sub-prefix command B and a read command line (eg, 00h) to read the preset data corresponding to the valid data state from the logical address used as MLC in the QLC memory. Figure 3 As shown in (d), the QLC memory receives the second sub-prefix command B and a read command line (eg, 00h) to read the preset data corresponding to the valid data state from the logical address used as SLC in the QLC memory.

[0122] Figure 4 shows a read timing diagram, such as Figure 4 The read sequence shown in FIG. 1 first receives a prefix command (Prefix command, i.e. Figure 4 CMD in the command), and then receive and read the command line after determining the type of the prefix command (for example Figure 4 00h), then receiving an address signal in an address period (ADDR) to obtain a logic address where the nth group of logic page data to be read is located, and finally reading corresponding preset data according to a special read voltage of the nth group of logic page data.

[0123] Taking QLC memory as an example, the memory controller sends the first sub-prefix command A and LP data, MP data and UP data to the peripheral circuit. The peripheral circuit performs an exclusive OR (XOR) operation on the LP data, MP data and UP data according to the first sub-prefix command A to generate XP data. A write command (for example, 80h) is sent to the peripheral circuit, and the peripheral circuit starts to write the LP data, MP data, UP data and XP data into the memory cell array to store 4 bits of information in the memory cell and generate 8 different data states, that is, some memory cells in the QLC memory are used as TLC. In this way, Figure 4 As shown in (b), the QLC memory receives the first sub-prefix command A sent by the memory controller. The QLC memory can determine the data that needs to be read for storage in the TLC according to the first sub-prefix command A. After the QLC memory receives the read command line (00h), it receives the address signal in the address cycle (ADDR) so as to determine the logical address of the nth group of logical page data to be read according to the address signal, and then refers to the special read voltage of the nth group of logical page data corresponding to the first prefix sub-command A in the above embodiment, and reads the preset data corresponding to the corresponding target data state from the logical address, wherein the target data state is a valid data state in which the preset data between adjacent valid data states in the nth group of logical page data has a logical state change. Here, the logical address includes a logical unit number (lun), a plane, a storage block (block), and a storage page (page) address. It should be noted that the first sub-prefix command A is received before the 00h command. Similarly, if Figure 4 As shown in (c), the QLC memory receives the second sub-prefix command B sent by the memory controller, and reads data with reference to the embodiment shown in 4(b). Figure 4 As shown in (d), the QLC memory receives the third sub-prefix command C sent by the memory controller, and reads data with reference to the embodiment shown in 4(d).

[0124] Read 2 in the above way nAfter the preset data corresponding to the valid data state, the calculation formula corresponding to the prefix command is used to read the 2 n The preset data corresponding to the valid data states are logically operated to obtain the nth group of logical page data.

[0125] When the memory of the present application receives a prefix command (CMD), the special read voltage corresponding to the logical change (for example, "0" changes to "1" or "1" changes to "0") in the valid data state of the nth group of logical page data is determined according to the prefix command. n The preset data of the valid data state is used to read the preset data of the nth group of logical page data, so that the number of reads is less than the number of reads of the preset data of all preset data states in the nth group of logical page data according to the preset read voltage of the nth group of logical page data. In this way, the number of data reads of the nth group of logical page data can be reduced by reducing the number of read voltages used, thereby saving the read time of the read operation, which is conducive to improving the read speed and improving the operating performance of the memory.

[0126] In some embodiments, it also includes:

[0127] When the difference between n and m is 1, the prefix command includes a first sub-prefix command A; wherein the first sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on preset data corresponding to the valid data states;

[0128] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0129] Specifically, when the difference between n and m is 1, that is, n+1=m, the peripheral circuit reads 2 of the nth group of logic page data from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command A. n valid data state, and according to the logical operation formula corresponding to the first sub-prefix command A, the 2 read n The preset data corresponding to the valid data states are logically operated to generate the nth group of logic page data so as to read the nth group of logic page data.

[0130] For example, it is assumed that a Gray code lookup table used in the embodiment of the present application is as follows: Figure 5 As shown, Figure 6 and Figure 7 As shown, taking the QLC memory as an example, if part of the storage cells in the QLC memory are used as TLC, then m=n+1=4. 2 of the third group of logical page data (ie, UP logical page data) 3 = 8 valid data states include P0, P2, P4, P6, P8, P10, P12, and P14. The 4 preset read voltages corresponding to the third set of logic page data in these 8 valid data states include R5, R10, R12, and R15. Since the preset data corresponding to the adjacent valid data states between R12 and R15 in the UP logic page data do not undergo logic changes, for example Figure 6 and Figure 7 The preset data corresponding to the adjacent valid data states between R12 and R15 remain unchanged at "0", so R15 has no effect on the logical operation of the preset data. Therefore, the three preset read voltages of R5, R10, and R12 are determined to be specific read voltages for reading the UP logical page data. In this way, the number of reads of the preset data of the third group of logical page data (i.e., UP logical page data) according to the three special read voltages is equal to 3 times, which can save 1 / 4 of the reading time compared to the number of reads of the preset data according to the four preset read voltages of the third group of logical page data, i.e., 4 times. For the present application, the number of read voltages used to read data is reduced, and the number of data reads for the nth group of logical page data is reduced, thereby saving the reading time of the read operation, which is conducive to improving the reading speed and improving the operating performance of the memory.

[0131] Exemplarily, taking a TLC memory as an example, if some of the memory cells in the TLC memory are used as MLC, that is, m=n+1=3. Exemplarily, taking an MLC memory as an example, if some of the memory cells in the MLC memory are used as SLC, that is, m=n+1=2. Referring to the above example, the specific read voltage of the nth group of logical page data is determined, and then the data is read according to the specific read voltage less than the preset read voltage, which can reduce the number of times the data is read, thereby saving the read time of the read operation, which is conducive to improving the read speed and improving the operating performance of the memory.

[0132] In some embodiments, it also includes:

[0133] When the difference between n and m is 2, the prefix command includes a second sub-prefix command B; wherein the second sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on the preset data corresponding to the valid data states,

[0134] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix commandn The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0135] Specifically, when the difference between n and m is 2, that is, n+2=m, the peripheral circuit reads 2 of the nth group of logic page data from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix command B. n valid data state, and according to the logical operation formula corresponding to the second sub-prefix command B, the 2 read n The preset data corresponding to the valid data states are logically operated to generate the nth group of logic page data so as to read the nth group of logic page data.

[0136] For example, it is assumed that a Gray code lookup table used in the embodiment of the present application is as follows: Figure 5 As shown, Figure 8 and Fig. 9 As shown, taking the QLC memory as an example, if part of the storage cells in the QLC memory are used as MLC, then m=n+2=4. 2 of the second group of logical page data (i.e., MP logical page data) 2 = 4 valid data states include P0, P5, P10, and P15. The 4 preset read voltages corresponding to the third set of logic page data in these 4 valid data states include R5, R10, R12, and R15. Since the preset data corresponding to the adjacent valid data states between R7 and R9 in the MP logic page data do not undergo logic changes, for example Figure 8 and Fig. 9 The preset data of the adjacent valid data states between R12 and R15 remain unchanged at "0", so R12 and R15 have no effect on the logical operation of the preset data, so it is determined that the two preset read voltages R3 and R13 are specific read voltages for reading the MP logical page data. In this way, the number of reads of the preset data of the second group of logical page data (i.e., MP logical page data) according to the two special read voltages is equal to 2 times, which can save 1 / 2 of the reading time compared to the number of reads of the preset data according to the 4 preset read voltages of the second group of logical page data, i.e., 4 times. The present application reduces the number of read voltages used to read the data, reduces the number of data reads for the nth group of logical page data, and thus can save the reading time of the reading operation, which is conducive to improving the reading speed and improving the operating performance of the memory. Similarly, the data reading of the third group of logical page data (UP) and the data reading of the fourth group of logical page data (XP) are also 2 times, the same as the number of reads for the second group of logical page data (MP), which can also save 1 / 2 of the reading time.

[0137] For example, taking a TLC memory as an example, if some storage cells in the TLC memory are used as SLC, that is, m=n+2=3. Referring to the above example, a specific read voltage of the nth group of logical page data is determined, and then data is read according to a specific read voltage that is less than a preset read voltage, which can reduce the number of times data is read, thereby saving the read time of the read operation, which is conducive to improving the read speed and improving the operating performance of the memory.

[0138] In some embodiments, it also includes:

[0139] When the difference between n and m is 3, the prefix command includes a third sub-prefix command C; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data;

[0140] The nth group of logic page data is read from the storage cell array according to the third sub-prefix command, and a copy operation is performed on the nth group of logic page data to generate an (n+1)th group of logic page data.

[0141] Specifically, when the difference between n and m is 3, that is, n+3=m, the peripheral circuit reads 2 of the nth group of logic page data from the memory cell array according to the n special read voltages of the nth group of logic page data. n A valid data state can be obtained, and a copy operation can be directly performed on the nth group of logical page data according to the third sub-prefix command C to generate the (n+1)th group of logical page data.

[0142] For example, it is assumed that a Gray code lookup table used in the embodiment of the present application is as follows: Figure 5 As shown, taking the QLC memory as an example, if part of the storage cells in the QLC memory are used as SLC, then m=n+3=4. 2 of the first group of logical page data (i.e., LP logical page data) 1 =2 valid data states include P0 and P8. In this way, when reading the second group of logical page data (MP logical page data), there is no need to read the storage unit again. The second group of logical page data (MP logical page data) can be obtained by directly performing a copy operation based on the first group of logical page data (i.e., LP logical page data) read previously. In other words, when some storage units in the QLC memory are used as SLC, the second group of logical page data (MP logical page data) is equal to the first group of logical page data (i.e., LP logical page data). The present application can reduce the number of read voltages used to read the n+1th group of logical page data through a copy operation, reduce the number of data reads for the n+1th group of logical page data, and thereby save the reading time of the read operation, which is conducive to improving the reading speed and improving the operating performance of the memory.

[0143] In some embodiments, it also includes:

[0144] In response to the received read command not including the prefix command, m groups of logical page data are read from the memory cell array according to a preset read voltage of the nth group of logical page data.

[0145] Specifically, Figure 3 As shown, when the received read command does not include the prefix command, as shown in Figure 3 As shown in (a), a NAND memory cell can have 2 m The preset data state is directly read according to the preset voltage of the nth group of logic page data, so 2 m -1 preset read voltage reads m groups of logical page data from the memory cell array of the memory. Taking the QLC memory cell as an example, the QLC memory cell stores 16 preset data states, and the four groups of logical page data read are the preset data corresponding to all the preset data states stored in the QLC memory cell.

[0146] For example, for a QLC NAND memory, a 16-16 two-pass programming scheme may be used to program and / or read memory cells. Figure 5 A Gray code lookup table for programming and / or reading a QLC NAND memory is shown. The Gray code lookup table describes the mapping relationship between the state of a storage cell in a QLC NAND memory and n sets of logical page data planes. In a read operation, Figure 5 As shown, in order to read the state of the storage unit in the QLC NAND memory, when using the 16-16 two-pass programming scheme, it is necessary to read LP 4 times, MP 4 times, UP 4 times, and XP 3 times. Among them, when the data of the adjacent data states in the same logical page data plane changes, it is recorded as a transition. By counting all the transitions of a logical page data plane, it can be seen that the transition count of LP is 4, the transition count of MP is 4, the transition count of UP is 4, and the transition count of XP is 3. When determining the reading range during data reading, the number of reads needs to be determined according to the number of transitions of the data of the adjacent data states, that is, the number of transitions of the data of the adjacent data states is equal to the number of reads.

[0147] In the above embodiments, the arrangement of the preset data of each data state of different storage units is only an example, and other arrangements of the preset data are also within the protection scope of the present application.

[0148] The embodiment of the present application further provides a memory controller, the memory controller is coupled to a memory, the memory includes a memory cell array, the memory cell array includes a plurality of memory cells, the memory cells are used to store m bits of information, the memory cells store n valid bits of information by corresponding 2n valid data states in 2m preset data states to m groups of logic page data, and a preset read voltage corresponding to each preset data state is provided corresponding to each group of logic page data, wherein m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m; the memory controller is configured as follows:

[0149] Sending a read command including a prefix command to the memory, so that the memory determines a special read voltage for reading each valid data state in the first to nth logical pages of data according to the prefix command;

[0150] The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

[0151] In some embodiments, after sending the read command, the memory controller is configured to:

[0152] Sending a read command line to the memory, and sending an address signal to the memory during an address cycle, so that the memory obtains the logical address of the nth group of logical page data to be read according to the address signal;

[0153] A read command line is sent to the memory to start executing, so that the memory reads the corresponding preset data according to the special read voltage of the nth group of logic page data, and the memory adopts the operation formula corresponding to the prefix command to perform a logical operation on the preset data corresponding to the valid data state read to obtain the logic page data.

[0154] In some embodiments, the preset data state includes preset data, the prefix command includes a first sub-prefix command, the first sub-prefix command indicates to read the preset data corresponding to the three valid data states of the nth group of logical page data from the memory cell array for logical operation, the difference between n and m is 1, and the memory controller is configured as follows:

[0155] The first sub-prefix command is sent to the memory, so that the memory reads 2 from the memory cell array according to the n special read voltages of the nth group of logical page data and the first sub-prefix command. n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0156] In some embodiments, the prefix command includes a second sub-prefix command, the second sub-prefix command instructs to read preset data corresponding to two valid data states of the nth group of logical page data from the memory cell array for logical operation, and the difference between n and m is 2; the memory controller is further configured to:

[0157] The second sub-prefix command is sent to the memory, so that the memory reads 2 from the memory cell array according to the n special read voltages of the nth group of logical page data and the second sub-prefix command. n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0158] In some embodiments, the prefix command includes a third sub-prefix command C; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data, and the difference between n and m is 3;

[0159] The memory controller is specifically configured to: send the third sub-prefix command to the memory, so that the memory reads the nth group of logical page data from the storage cell array according to the third sub-prefix command, and performs a copy operation on the nth group of logical page data to generate the n+1th group of logical page data.

[0160] like Fig.10 As shown, an embodiment of the present application further provides a memory, the memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells, the memory cells being used to store m bits of information, the memory cells storing n valid bits of information by corresponding 2n valid data states in 2m preset data states to m groups of logic page data, and a preset read voltage corresponding to each preset data state is provided corresponding to each group of logic page data, wherein m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m; the memory is configured as follows:

[0161] Corresponding to the received read command including a prefix command, a special read voltage for reading each valid data state in the first to nth groups of logical page data is determined according to the prefix command; n is a positive integer greater than 1 and less than or equal to m;

[0162] Reading corresponding data from the storage unit according to the special read voltage;

[0163] The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

[0164] In some embodiments, the special read voltage of the nth group of logic page data includes: a preset read voltage of the nth page corresponding to different logic states of the bit information in adjacent valid data states of the nth group of logic page data.

[0165] In some embodiments, the preset data state includes preset data, and after receiving the read command, the memory is further configured as:

[0166] Receive a read command line, and obtain the logical address of the nth group of logical page data to be read according to the received address signal within the address cycle;

[0167] After receiving a command line for starting to execute a read, reading corresponding preset data according to a special read voltage of the nth group of logical page data;

[0168] The steps after determining the special reading voltage include:

[0169] The logic page data is obtained by using a calculation formula corresponding to the prefix command to perform a logic operation on the preset data corresponding to the valid data state read.

[0170] In some embodiments, the memory is further configured to:

[0171] When the difference between n and m is 1, the prefix command includes a first sub-prefix command A; wherein the first sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on preset data corresponding to the valid data states;

[0172] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0173] In some embodiments, the memory is further configured to:

[0174] When the difference between n and m is 2, the prefix command includes a second sub-prefix command B; wherein the second sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on the preset data corresponding to the valid data states,

[0175] Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix command nThe preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

[0176] In some embodiments, the memory is further configured to:

[0177] When the difference between n and m is 3, the prefix command includes a third sub-prefix command C; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data;

[0178] The nth group of logic page data is read from the storage cell array according to the third sub-prefix command, and a copy operation is performed on the nth group of logic page data to generate an (n+1)th group of logic page data.

[0179] In some embodiments, the memory is further configured to:

[0180] In response to the received read command not including the prefix command, m groups of logical page data are read from the memory cell array according to a preset read voltage of the nth group of logical page data.

[0181] Specifically, if the read command received by the memory does not include the prefix command, then the logic control unit in the peripheral circuit of the memory may call the 2 stored in the cache register or the data register according to the read command. m The preset data states each correspond to a preset read voltage. In this way, the storage controller can read the corresponding data from the memory according to the preset read voltage corresponding to the read command. In other words, the present application can use a full sequence programming method to write or program data to each storage unit, and use a full sequence reading method to read data from each storage unit.

[0182] An embodiment of the present application also provides a storage system, comprising one or more memories described in the above embodiments and the memory controller described in the above embodiments, wherein the memory controller is coupled to the memory and is configured to control the memory.

[0183] It should be noted that the storage system here includes the aforementioned memory controller and the aforementioned memory, and the two have the same technical characteristics. The aforementioned has already described in detail the structure of the memory device, the memory controller and the nouns appearing in the technical solution of this application. Therefore, the nouns appearing here can be understood according to the meaning of the aforementioned description and will not be repeated here.

[0184] Among them, the storage system can be integrated into various types of storage devices, for example, included in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0185] In some examples, such as Fig.10 As shown, the storage system 50 includes a memory controller 502 and a memory 501. The storage system can be integrated into Fig.11 The memory device card 150 is shown.

[0186] Among them, the memory device card 150 includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital (SD) card, and a UFS.

[0187] In other embodiments, the storage system 50 includes a memory controller 502 and a plurality of memories 501, and the storage system 50 is integrated into a solid state drive (SSD).

[0188] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0189] like Fig.10As shown, the electronic device 1000 may include the storage system 50 described above, and may also include at least one of a central processing unit (CPU) and a cache. The electronic device may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The electronic device 1000 may include a host 20 and a storage system 50, and the storage system 50 has one or more memories 501 and a memory controller 502. The host 20 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 20 may further include a storage interface for coupling with the storage system 50, the storage interface being configured to comply with a corresponding protocol (e.g., NVMe, PCIe, etc.), and the host 20 may be configured to send data to or receive data from the storage 501 through, for example, the storage interface. In order to send data to or receive data from the storage 501, in addition to the data, the host 20 may also send instructions to the storage system 50. The storage 501 may be any storage 501 disclosed in the present application.

[0190] According to some embodiments, the memory controller 502 is coupled to the memory 501 and the host 20, and is configured to control the memory 501. The memory controller 502 may be implemented by a microprocessor, a micro memory controller 502 (also known as a micro memory controller 502 unit (MCU)), a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gated logic unit, a discrete hardware circuit, or a combination thereof, and other suitable hardware, firmware, and / or software configured to perform various functions described in detail below. The memory controller 502 may manage data stored in the memory 501 and communicate with the host 20 through its front-end interface. In some embodiments, the memory controller 502 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 502 is designed to operate in a high duty cycle environment SSD or an embedded multi-media-card (eMMC) used as data storage and enterprise memory cell arrays for mobile devices such as smartphones, tablet computers, laptop computers, etc. The memory controller 502 can be configured to control operations of the memory 501, such as read, erase, and program operations.

[0191] The memory controller 502 may also be configured to manage various functions regarding data stored or to be stored in the memory 501, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 502 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 501. The memory controller 502 may also perform any other suitable functions, such as formatting the memory 501. The memory controller 502 may communicate with an external device (e.g., the host 20) according to a specific communication protocol. For example, the memory controller 502 can communicate with an external device through at least one of various interface protocols, and the interface protocol can be, for example, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0192] The memory controller 502 and the one or more memories 501 can be integrated into various types of storage systems, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 50 can be implemented and packaged into different types of terminal electronic products. Fig.11In one example shown in FIG. 1 , a memory controller 502 and a single memory 501 may be integrated into a memory device card 150. The memory device card 150 may include a PC card (personal computer memory card international association, PCMCIA), a personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMC micro), an SD card (SD, miniSD, micro SD, SDHC), UFS, etc. The memory device card 150 may also include a memory card connector 1501, which is configured to couple the memory device card 150 to the host 20. In the example shown in FIG. 1 , a memory controller 502 and a single memory 501 may be integrated into a memory device card 150. In the example shown in FIG. 1 , a memory card connector 1501 is configured to couple the memory device card 150 to the host 20. Fig.12 In another example shown in , the memory controller 502 and the plurality of memories 501 may be integrated into the SSD 151. The SSD 151 may also include an SSD connector 1511 configured to couple the SSD 151 to the host 20. In some embodiments, the storage capacity and / or operating speed of the SSD 151 is greater than the storage capacity and / or operating speed of the memory device card 150.

[0193] The above is a detailed introduction to a memory operation method, a memory, a memory controller and a storage system provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for operating a memory, characterized in that: The memory includes a storage cell array, the storage cell array includes a plurality of storage cells, the storage cells are used to store m bits of information, the storage cells correspond to 2 through m groups of logical page data m 2 of the preset data states n valid data states to store n valid bits of information, and a preset read voltage corresponding to each preset data state is provided corresponding to each set of logical page data, wherein m is a positive integer greater than 1, and n is a positive integer greater than 1 and less than m; the operation method comprises: receiving a read command, corresponding to the received read command including a prefix command, and determining a special read voltage for reading each valid data state in the first to nth groups of logical page data according to the prefix command; The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

2. The memory operation method according to claim 1, characterized in that: The special read voltage of the nth group of logic page data includes: the nth page preset read voltage corresponding to different logic states of the bit information in adjacent valid data states of the nth group of logic page data.

3. The memory operation method according to claim 1, characterized in that: The preset data state includes preset data, and the steps after receiving the read command include: Receive a read command line, and obtain the logical address of the nth group of logical page data to be read according to the received address signal within the address cycle; After receiving a command line for starting to execute a read, reading corresponding preset data according to a special read voltage of the nth group of logical page data; The steps after determining the special reading voltage include: The logic page data is obtained by using a calculation formula corresponding to the prefix command to perform a logic operation on the preset data corresponding to the read valid data state.

4. The memory operation method according to claim 3, characterized in that: Also includes: When the difference between n and m is 1, the prefix command includes a first sub-prefix command; wherein the first sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on preset data corresponding to the valid data states; Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

5. The memory operation method according to claim 3, characterized in that: Also includes: When the difference between n and m is 2, the prefix command includes a second sub-prefix command; wherein the second sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on the preset data corresponding to the valid data states, Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

6. The memory operation method according to claim 3, characterized in that: Also includes: When the difference between n and m is 3, the prefix command includes a third sub-prefix command; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data; The nth group of logic page data is read from the storage cell array according to the third sub-prefix command, and a copy operation is performed on the nth group of logic page data to generate an (n+1)th group of logic page data.

7. The memory operation method according to any one of claims 1 to 6, characterized in that: Also includes: In response to the received read command not including the prefix command, m groups of logical page data are read from the memory cell array according to a preset read voltage of the nth group of logical page data.

8. A memory controller, the memory controller is coupled to a memory, the memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells, the memory cells being used to store m bits of information, the memory cells corresponding to 2 m 2 of the preset data states n valid data states to store n valid bits of information, and a preset read voltage corresponding to each preset data state is provided corresponding to each set of logic page data, wherein: m is a positive integer greater than 1, n is a positive integer greater than 1 and less than m; The memory controller is configured to: Sending a read command including a prefix command to the memory, so that the memory determines a special read voltage for reading each valid data state in the first to nth logical pages of data according to the prefix command; The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

9. The memory controller according to claim 8, wherein: After sending the read command, the memory controller is configured to: Sending a read command line to the memory, and sending an address signal to the memory during an address cycle, so that the memory obtains the logical address of the nth group of logical page data to be read according to the address signal; A read command line is sent to the memory to start executing, so that the memory reads the corresponding preset data according to the special read voltage of the nth group of logic page data, and the memory adopts the operation formula corresponding to the prefix command to perform a logical operation on the preset data corresponding to the valid data state read to obtain the logic page data.

10. The memory controller according to claim 9, characterized in that: The preset data state includes preset data, the prefix command includes a first sub-prefix command, the first sub-prefix command indicates to read preset data corresponding to three valid data states of the nth group of logical page data from the memory cell array for logical operation, the difference between n and m is 1, and the memory controller is configured as follows: The first sub-prefix command is sent to the memory, so that the memory reads 2 from the memory cell array according to the n special read voltages of the nth group of logical page data and the first sub-prefix command. n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

11. The memory controller according to claim 9, wherein: The prefix command includes a second sub-prefix command, wherein the second sub-prefix command indicates to read preset data corresponding to two valid data states of the nth group of logic page data from the memory cell array for logical operation, and the difference between n and m is 2; the memory controller is further configured as follows: The second sub-prefix command is sent to the memory, so that the memory reads 2 from the memory cell array according to the n special read voltages of the nth group of logical page data and the second sub-prefix command. n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

12. The memory controller according to claim 9, wherein: The prefix command includes a third sub-prefix command; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data, and the difference between n and m is 3; The memory controller is specifically configured to: send the third sub-prefix command to the memory, so that the memory reads the nth group of logical page data from the storage cell array according to the third sub-prefix command, and performs a copy operation on the nth group of logical page data to generate the n+1th group of logical page data.

13. A memory, characterized in that: The memory includes a storage cell array, the storage cell array includes a plurality of storage cells, the storage cells are used to store m bits of information, the storage cells correspond to 2 through m groups of logical page data m 2 of the preset data states n The memory is configured as follows: Corresponding to the received read command including a prefix command, a special read voltage for reading each valid data state in the first to nth groups of logical page data is determined according to the prefix command; n is a positive integer greater than 1 and less than or equal to m; Reading corresponding data from the storage unit according to the special read voltage; The number of special read voltages for the n-th group of logic page data is less than the number of preset read voltages for the n-th group of logic page data.

14. The memory according to claim 13, characterized in that: The special read voltage of the nth group of logic page data includes: the nth page preset read voltage corresponding to different logic states of the bit information in adjacent valid data states of the nth group of logic page data.

15. The memory according to claim 13, characterized in that: The preset data state includes preset data, and after receiving the read command, the memory is further configured as: Receive a read command line, and obtain the logical address of the nth group of logical page data to be read according to the received address signal within the address cycle; After receiving a command line for starting to execute a read, reading corresponding preset data according to a special read voltage of the nth group of logical page data; The steps after determining the special reading voltage include: The logic page data is obtained by using a calculation formula corresponding to the prefix command to perform a logic operation on the preset data corresponding to the read valid data state.

16. The memory according to claim 13, characterized in that: The memory is further configured to: When the difference between n and m is 1, the prefix command includes a first sub-prefix command; wherein the first sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on preset data corresponding to the valid data states; Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the first sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

17. The memory according to claim 13, characterized in that: The memory is further configured to: When the difference between n and m is 2, the prefix command includes a second sub-prefix command; wherein the second sub-prefix command indicates to read 2 of the nth group of logical page data from the storage cell array. n Performing logic operations on the preset data corresponding to the valid data states, Reading 2 from the memory cell array according to the n special read voltages of the nth group of logic page data and the second sub-prefix command n The preset data corresponding to the valid data state, and the 2 n The preset data corresponding to the valid data states are logically operated to generate the nth group of logical page data.

18. The memory according to claim 13, characterized in that: The memory is further configured to: When the difference between n and m is 3, the prefix command includes a third sub-prefix command; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data; The nth group of logic page data is read from the storage cell array according to the third sub-prefix command, and a copy operation is performed on the nth group of logic page data to generate an (n+1)th group of logic page data.

19. The memory according to any one of claims 13 to 18, characterized in that: The memory is further configured to: In response to the received read command not including the prefix command, m groups of logical page data are read from the memory cell array according to a preset read voltage of the nth group of logical page data.

20. A storage system, characterized in that: Comprising one or more memories as claimed in any one of claims 13 to 19, and a memory controller as claimed in any one of claims 8 to 12, the memory controller being coupled to the memories and configured to control the memories.

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