Method for improving height uniformity of grid electrode of device

Abstract

The invention discloses a method for improving the height uniformity of a device grid electrode, and the method comprises the steps: S1, providing a substrate, forming an oxide layer on the surface of the substrate, and forming a plurality of projection structures which are arranged at intervals on the substrate; s2, a grid polycrystalline silicon layer is deposited on the oxide layer, the grid polycrystalline silicon layer is higher than the protruding structure, and a first low-lying area is formed on the surface layer of the grid polycrystalline silicon layer; s3, depositing a silicon nitride layer on the surface of the grid polycrystalline silicon layer, wherein a second low-lying area is formed on the surface layer of the silicon nitride layer; s4, a protection polycrystalline silicon layer is formed on the silicon nitride layer, a third low-lying area is formed on the surface layer of the protection polycrystalline silicon layer, and the third low-lying area is located above the second low-lying area; s5, performing a chemical mechanical grinding process on the protective polycrystalline silicon layer, and stopping the chemical mechanical grinding process on the surface of the silicon nitride layer; and S6, carrying out an etchback process until the thickness of the residual gate polycrystalline silicon layer reaches the target thickness. According to the scheme, the height uniformity of the grid electrode of the device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor processes, and in particular to a method for improving the uniformity of device gate height. Background Art

[0002] At present, in a semiconductor device, the polysilicon film structure usually adopts polysilicon-silicon nitride-oxide layer, and uses chemical mechanical polishing process and back etching process to make the polysilicon reach the required height. However, due to the different density of the graphics in the chip, there will be a load problem after the film structure is deposited. After the chemical mechanical polishing process and back etching process, the load problem will be further increased, thereby affecting the consistency of the device gate height, resulting in large fluctuations in device uniformity. Summary of the invention

[0003] In order to solve the above problems, the present application provides a method for improving the uniformity of device gate height.

[0004] The embodiment of the present application provides a method for improving the uniformity of gate height of a device, comprising: S1: providing a substrate, an oxide layer is formed on the surface of the substrate, a plurality of convex structures are formed on the substrate and are arranged at intervals, the convex structures penetrate the oxide layer and are higher than the oxide layer; S2: depositing a gate polysilicon layer on the oxide layer, wherein the gate polysilicon layer is higher than the protruding structure, and a first low-lying area is formed on the surface of the gate polysilicon layer; S3: depositing a silicon nitride layer on the surface of the gate polysilicon layer, wherein a second low-lying area is formed on the surface of the silicon nitride layer, and the second low-lying area is located above the first low-lying area; S4: forming a protective polysilicon layer on the silicon nitride layer, wherein a third low-lying area is formed on the surface of the protective polysilicon layer, and the third low-lying area is located above the second low-lying area; S5: performing a chemical mechanical polishing process on the protective polysilicon layer and stopping on the surface of the silicon nitride layer, wherein the polishing liquid used in the chemical mechanical polishing process contains an inhibitor, and the inhibitor slows down the polishing rate of the third low-lying area; S6: performing an etch-back process until the thickness of the remaining gate polysilicon layer reaches a target thickness.

[0005] In some embodiments, in S2 , a gate polysilicon layer is deposited on the oxide layer using a chemical vapor deposition process.

[0006] In some embodiments, in S3, a silicon nitride layer is deposited on the surface of the gate polysilicon layer using a chemical vapor deposition process.

[0007] In some embodiments, after the chemical mechanical polishing process is performed on the protective polysilicon layer and stops on the surface of the silicon nitride layer, the protective polysilicon layer remains in the second low-lying area on the surface of the silicon nitride layer, and the remaining protective polysilicon layer is removed in the back etching process.

[0008] In some embodiments, the protective polysilicon layer is deposited to have a thickness greater than that of the gate polysilicon layer.

[0009] The technical solution of this application has at least the following advantages: 1. By using a film structure of a gate polysilicon layer-silicon nitride layer-protective polysilicon layer to replace the film structure of a gate polysilicon layer-silicon nitride layer-protective oxide layer in the prior art, during the chemical mechanical polishing process, the inhibitor in the polishing liquid will slow down the polishing rate of the protective polysilicon layer under the low-lying area, so that after the subsequent back etching process is completed, the depth of the low-lying area on the remaining gate polysilicon layer is reduced, making the surface of the remaining gate polysilicon layer flatter, thereby improving the uniformity of the gate height of the final device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 is a flow chart of a method for improving the uniformity of device gate height provided by an exemplary embodiment of the present application; Figure 2~Figure 8 is a schematic diagram of a device structure during the execution of a method for improving the uniformity of device gate height provided by an exemplary embodiment of the present application; Fig. 9 is a schematic diagram of an exemplary embodiment of the present application for reflecting the online film thickness measurement result before executing the method for improving the uniformity of the device gate height; Fig.10 It is a schematic diagram of an exemplary embodiment of the present application for reflecting the online film thickness measurement result after executing the method for improving the uniformity of the device gate height.

[0012] Explanation of the reference numerals: 1. substrate; 2. oxide layer; 3. protruding structure; 4. gate polysilicon layer; 41. first low-lying area; 5. silicon nitride layer; 51. second low-lying area; 6. protective polysilicon layer; 61. third low-lying area. DETAILED DESCRIPTION

[0013] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0015] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0016] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0017] The present application provides a method for improving the uniformity of device gate height, referring to Figure 1 , the method comprises the following steps: S1: providing a substrate, wherein an oxide layer is formed on the surface of the substrate, and a plurality of convex structures are formed on the substrate and are spaced apart from each other, wherein the convex structures penetrate through the oxide layer and are higher than the oxide layer.

[0018] S2: depositing a gate polysilicon layer on the oxide layer, wherein the gate polysilicon layer is higher than the protruding structure, and a first low-lying area is formed on the surface of the gate polysilicon layer.

[0019] S3: depositing a silicon nitride layer on the surface of the gate polysilicon layer, forming a second low-lying area on the surface of the silicon nitride layer, and the second low-lying area is located above the first low-lying area.

[0020] S4: forming a protective polysilicon layer on the silicon nitride layer, wherein a third depressed area is formed on the surface of the protective polysilicon layer, and the third depressed area is located above the second depressed area.

[0021] S5: performing a chemical mechanical polishing process on the protective polysilicon layer and stopping on the surface of the silicon nitride layer. The polishing liquid used in the chemical mechanical polishing process contains an inhibitor, which slows down the polishing rate of the third low-lying area.

[0022] S6: performing an etch-back process until the thickness of the remaining gate polysilicon layer reaches a target thickness.

[0023] Specifically, refer to Figure 2~Figure 8 , Figure 2-Figure 8 1 is a schematic diagram of the device structure in each process step of the method for improving the uniformity of the device gate height provided in an embodiment of the present application. Next, the method for improving the uniformity of the device gate height provided in an embodiment of the present application is introduced in detail.

[0024] First, execute S1, refer to Figure 2 A substrate 1 is provided, and an oxide layer 2, such as silicon oxide, is formed on the surface of the substrate 1. At the same time, a plurality of convex structures 3 are formed on the surface of the substrate 1 at intervals, and the convex structures 3 penetrate the oxide layer 2 and are higher than the top of the oxide layer 2.

[0025] After that, execute S2, refer to Figure 3 , a gate polysilicon layer 4 is deposited on the oxide layer 2, and the top of the gate polysilicon layer 4 is higher than the protruding structure 3. During the deposition process, due to the different densities of the patterns in the chip, a first low-lying area 41 that is recessed downward is formed on the top of the formed gate polysilicon layer 4.

[0026] Furthermore, the gate polysilicon layer 4 may be deposited on the oxide layer 2 by using a chemical vapor deposition process.

[0027] After that, execute S3, refer to Figure 4 A silicon nitride layer 5 is deposited on the surface of the gate polysilicon layer 4. Since there is a first depressed area 41 that is recessed downward on the surface of the gate polysilicon layer 4, the silicon nitride layer 5 at the corresponding position will also be deposited in the first depressed area 41, and then a second depressed area 51 that is recessed downward will be formed on the surface of the silicon nitride layer 5, and the second depressed area 51 is located above the first depressed area 41.

[0028] Furthermore, a chemical vapor deposition process may be used to deposit a silicon nitride layer 5 on the surface of the gate polysilicon layer 4 .

[0029] After that, execute S4, refer to Figure 5A protective polysilicon layer 6 is formed on the silicon nitride layer 5. Since a second low-lying area 51 is formed on the surface of the silicon nitride layer 5, a third low-lying area 61 which is recessed downwards will also exist on the surface of the protective polysilicon layer 6 located above the second low-lying area 51.

[0030] Furthermore, the thickness of the deposited protection polysilicon layer 6 is greater than the thickness of the gate polysilicon layer 4 .

[0031] Then, S5 is executed to perform a chemical mechanical polishing process on the protective polysilicon layer 6. Figure 6 Since the polishing liquid used in the chemical mechanical polishing process contains inhibitors, during the chemical mechanical polishing process, there will be inhibitors covering the surface of the protective polysilicon layer 6 in the third low-lying area 61, slowing down the polishing rate of the third low-lying area 61. Therefore, in the early stage of the chemical mechanical polishing process, when the third low-lying area 61 still exists, the polishing speed of the protective polysilicon layer 6 below the third low-lying area 61 will be slower than that of the protective polysilicon layer 6 in the flat area. As the chemical mechanical polishing process proceeds, the shape of the third low-lying area 61 will not be inherited downward, and the depth of the low-lying area on the surface of the remaining protective polysilicon layer 6 will gradually decrease. Afterwards, refer to Figure 7 , the chemical mechanical polishing process stops at the silicon nitride layer 5. At this time, the protective polysilicon layer 6 remains in the second low-lying area 51 on the surface of the silicon nitride layer 5.

[0032] After that, execute S6, refer to Figure 8 , and a back-etching process is performed to remove the remaining protective polysilicon layer 6, silicon nitride layer 5 and the top portion of the gate polysilicon layer 4 until the thickness of the remaining gate polysilicon layer 4 reaches the target thickness. The value of the target thickness can be specifically set according to the device size, functional requirements, etc. After the back-etching process is completed, the depth of the low-lying area on the surface of the remaining gate polysilicon layer 4 is less than the depth of the first low-lying area 41, that is, the surface of the gate polysilicon layer 4 is flatter, thereby improving the load problem and improving the uniformity of the device gate height.

[0033] Reference Fig. 9 and 10 , respectively, are the online film thickness measurement results before and after using this method. It can be found that compared with Fig. 9 , Fig.10 The variation range of the middle membrane thickness was significantly reduced.

[0034] An embodiment of the present application provides a method for improving the uniformity of the gate height of a device. By using a film layer structure of a gate polysilicon layer-silicon nitride layer-protective polysilicon layer, the film layer structure of a gate polysilicon layer-silicon nitride layer-protective oxide layer in the prior art is replaced. When performing a chemical mechanical polishing process, an inhibitor in the polishing liquid will slow down the polishing rate of the protective polysilicon layer 6 under the low-lying area, so that after the subsequent back-etching process is completed, the depth of the low-lying area on the remaining gate polysilicon layer 4 is reduced, making the surface of the remaining gate polysilicon layer 4 flatter, thereby improving the uniformity of the gate height of the final device.

[0035] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for improving the uniformity of device gate height, characterized in that: include: S1: providing a substrate, wherein an oxide layer is formed on the surface of the substrate, and a plurality of convex structures are formed on the substrate and are arranged at intervals, wherein the convex structures penetrate the oxide layer and are higher than the oxide layer; S2: depositing a gate polysilicon layer on the oxide layer, wherein the gate polysilicon layer is higher than the protruding structure, and a first low-lying area is formed on the surface of the gate polysilicon layer; S3: depositing a silicon nitride layer on the surface of the gate polysilicon layer, wherein a second low-lying area is formed on the surface of the silicon nitride layer, and the second low-lying area is located above the first low-lying area; S4: forming a protective polysilicon layer on the silicon nitride layer, wherein a third low-lying area is formed on the surface of the protective polysilicon layer, and the third low-lying area is located above the second low-lying area; S5: performing a chemical mechanical polishing process on the protective polysilicon layer and stopping on the surface of the silicon nitride layer, wherein the polishing liquid used in the chemical mechanical polishing process contains an inhibitor, and the inhibitor slows down the polishing rate of the third low-lying area; S6: performing an etch-back process until the thickness of the remaining gate polysilicon layer reaches a target thickness.

2. The method for improving the uniformity of device gate height according to claim 1, characterized in that: In S2, a gate polysilicon layer is deposited on the oxide layer using a chemical vapor deposition process.

3. The method for improving the uniformity of device gate height according to claim 1, characterized in that: In S3, a silicon nitride layer is deposited on the surface of the gate polysilicon layer using a chemical vapor deposition process.

4. The method for improving the uniformity of device gate height according to claim 1, characterized in that: After the chemical mechanical polishing process is performed on the protective polysilicon layer and stops on the surface of the silicon nitride layer, the protective polysilicon layer remains in the second low-lying area on the surface of the silicon nitride layer, and the remaining protective polysilicon layer is removed in the etching back process.

5. The method for improving the uniformity of device gate height according to claim 1, characterized in that: The thickness of the deposited protection polysilicon layer is greater than the thickness of the gate polysilicon layer.

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