Method for improving gate height uniformity of a device

Abstract

The application discloses a method for improving the uniformity of the height of a device gate, and comprises the following steps: S1, providing a substrate, the surface of the substrate is formed with an oxide layer, and a plurality of protruding structures are formed on the substrate in a spaced manner; S2, depositing a gate polysilicon layer on the oxide layer, the gate polysilicon layer is higher than the protruding structures, and a first low-lying area is formed on the surface of the gate polysilicon layer; S3, depositing a silicon nitride layer on the surface of the gate polysilicon layer, a second low-lying area is formed on the surface of the silicon nitride layer; S4, forming a protective polysilicon layer on the silicon nitride layer, a third low-lying area is formed on the surface of the protective polysilicon layer, and the third low-lying area is located above the second low-lying area; S5, performing a chemical mechanical polishing process on the protective polysilicon layer and stopping on the surface of the silicon nitride layer; and S6, performing a back etching process until the thickness of the remaining gate polysilicon layer reaches a target thickness. Through the above scheme, the uniformity of the height of the device gate can be improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor processes, and more specifically to a method for improving the uniformity of device gate height. Background Technology

[0002] Currently, in a certain semiconductor device, the polysilicon film structure typically employs a polysilicon-silicon nitride-oxide layer, and chemical mechanical polishing (CMP) and etch-back processes are used to achieve the required polysilicon height. However, due to the varying density of patterns within the chip, load issues arise after film deposition. These load issues are further amplified after CMP and etch-back processes, affecting the uniformity of the device gate height and leading to significant fluctuations in device uniformity. Summary of the Invention

[0003] To address the aforementioned issues, this application provides a method for improving the uniformity of device gate height.

[0004] This application provides a method for improving the uniformity of device gate height, including: S1: providing a substrate, wherein an oxide layer is formed on the surface of the substrate, and a plurality of protrusion structures are formed on the substrate at intervals, wherein the protrusion structures penetrate the oxide layer and protrude above the oxide layer;

[0005] S2: A gate polysilicon layer is deposited on the oxide layer, the gate polysilicon layer is higher than the protrusion structure, and a first low-lying region is formed on the surface of the gate polysilicon layer;

[0006] S3: A silicon nitride layer is deposited on the surface of the gate polysilicon layer, and a second low-lying region is formed on the surface of the silicon nitride layer, the second low-lying region being located above the first low-lying region;

[0007] S4: A protective polysilicon layer is formed on the silicon nitride layer, and a third low-lying region is formed on the surface of the protective polysilicon layer, the third low-lying region being located above the second low-lying region;

[0008] S5: Perform a chemical mechanical polishing process on the protective polysilicon layer and stop on the surface of the silicon nitride layer. The polishing slurry used in the chemical mechanical polishing process contains an inhibitor, which slows down the polishing rate of the third depression region.

[0009] S6: Perform a back-etching process until the remaining thickness of the gate polysilicon layer reaches the target thickness.

[0010] In some embodiments, in S2, a gate polysilicon layer is deposited on the oxide layer using a chemical vapor deposition process.

[0011] In some embodiments, in S3, a silicon nitride layer is deposited on the surface of the gate polysilicon layer using a chemical vapor deposition process.

[0012] In some embodiments, after the chemical mechanical polishing process is performed on the protective polysilicon layer and stops on the surface of the silicon nitride layer, a protective polysilicon layer remains in the second low-lying area of ​​the surface of the silicon nitride layer, and the remaining protective polysilicon layer is removed in the etch-back process.

[0013] In some embodiments, the thickness of the deposited protective polysilicon layer is greater than the thickness of the gate polysilicon layer.

[0014] The technical solution of this application has at least the following advantages:

[0015] 1. By using a gate polysilicon layer-silicon nitride layer-protective polysilicon layer film structure instead of the existing gate polysilicon layer-silicon nitride layer-protective oxide layer film structure, during the chemical mechanical polishing process, the inhibitor in the polishing slurry slows down the polishing rate of the protective polysilicon layer in the low-lying area. This results in a reduction in the depth of the low-lying area on the remaining gate polysilicon layer after the subsequent etch-back process, making the surface of the remaining gate polysilicon layer smoother and improving the gate height uniformity of the final device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a method for improving the uniformity of device gate height provided in an exemplary embodiment of this application;

[0018] Figures 2-8 This is a schematic diagram of the device structure during the execution of a method for improving the uniformity of device gate height provided in an exemplary embodiment of this application;

[0019] Figure 9 This is a schematic diagram illustrating online film thickness measurement results prior to performing a method for improving device gate height uniformity, provided by an exemplary embodiment of this application;

[0020] Figure 10 This is a schematic diagram illustrating the results of online film thickness measurement after performing a method to improve the uniformity of device gate height, provided by an exemplary embodiment of this application.

[0021] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Oxide layer; 3. Protrusion structure; 4. Gate polysilicon layer; 41. First depression region; 5. Silicon nitride layer; 51. Second depression region; 6. Protective polysilicon layer; 61. Third depression region. Detailed Implementation

[0022] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection between two components; and they can refer to wireless connections or wired connections. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0026] This application provides a method for improving the gate height uniformity of a device, referring to... Figure 1 The method includes the following steps:

[0027] S1: A substrate is provided, an oxide layer is formed on the surface of the substrate, and a plurality of protrusions are formed on the substrate at intervals, the protrusions penetrating the oxide layer and extending above the oxide layer.

[0028] S2: A gate polysilicon layer is deposited on the oxide layer. The gate polysilicon layer is higher than the bump structure, and a first low-lying region is formed on the surface of the gate polysilicon layer.

[0029] S3: A silicon nitride layer is deposited on the surface of the gate polysilicon layer, and a second depression region is formed on the surface of the silicon nitride layer, which is located above the first depression region.

[0030] S4: A protective polysilicon layer is formed on the silicon nitride layer. A third depression region is formed on the surface of the protective polysilicon layer. The third depression region is located above the second depression region.

[0031] S5: Perform chemical mechanical polishing on the protective polysilicon layer and stop on the silicon nitride layer surface. The polishing slurry used in the chemical mechanical polishing process contains an inhibitor, which slows down the polishing rate on the third depression region.

[0032] S6: Perform the etch-back process until the remaining gate polysilicon layer reaches the target thickness.

[0033] For details, please refer to Figures 2-8 , Figures 2-8 This is a schematic diagram of the device structure in each process step of the method for improving the uniformity of device gate height provided in the embodiments of this application. The method for improving the uniformity of device gate height provided in the embodiments of this application will be described in detail below.

[0034] First, execute S1, referring to... Figure 2 The system provides a substrate 1 on which an oxide layer 2, such as silicon oxide, is formed. Simultaneously, a plurality of spaced-apart protrusions 3 are formed on the surface of the substrate 1, the protrusions 3 penetrating the oxide layer 2 and extending beyond the top of the oxide layer 2.

[0035] Next, execute S2, refer to Figure 3 A gate polysilicon layer 4 is deposited on the oxide layer 2, with the top of the gate polysilicon layer 4 higher than the bump structure 3. During the deposition process, due to the different densities of the patterns within the chip, a first recessed region 41 is formed on the top of the gate polysilicon layer 4.

[0036] Furthermore, a chemical vapor deposition process can be used to deposit a gate polysilicon layer 4 on the oxide layer 2.

[0037] Next, execute S3, refer to Figure 4 A silicon nitride layer 5 is deposited on the surface of the gate polysilicon layer 4. Since there is a first depression region 41 on the surface of the gate polysilicon layer 4, the silicon nitride layer 5 at the corresponding position will also be deposited in the first depression region 41. As a result, a second depression region 51 will be formed on the surface of the silicon nitride layer 5, and the second depression region 51 is located above the first depression region 41.

[0038] Furthermore, a silicon nitride layer 5 can be deposited on the surface of the gate polysilicon layer 4 using a chemical vapor deposition process.

[0039] Next, execute S4, refer to Figure 5 A protective polysilicon layer 6 is formed on the silicon nitride layer 5. Since a second depression region 51 is formed on the surface of the silicon nitride layer 5, a third depression region 61 with downward indentation will also exist on the surface of the protective polysilicon layer 6 located above the second depression region 51.

[0040] Furthermore, the thickness of the deposited protective polysilicon layer 6 is greater than the thickness of the gate polysilicon layer 4.

[0041] Next, step S5 is performed to conduct a chemical mechanical polishing process on the protective polysilicon layer 6. (Refer to...) Figure 6 Because the polishing slurry used in chemical mechanical polishing (CMP) contains inhibitors, these inhibitors will coat the surface of the protective polysilicon layer 6 in the third depression region 61 during the CMP process, slowing down the polishing rate of the third depression region 61. Therefore, in the early stages of the CMP process, when the third depression region 61 still exists, the polishing speed of the protective polysilicon layer 6 below the third depression region 61 will be slower than that of the protective polysilicon layer 6 in the flat region. As the CMP process continues, the shape of the third depression region 61 will not be inherited downwards, and the depth of the depression region on the surface of the remaining protective polysilicon layer 6 gradually decreases. Then, referring to... Figure 7 The chemical mechanical polishing process stops at the silicon nitride layer 5. At this point, the protective polysilicon layer 6 remains in the second depression region 51 on the surface of the silicon nitride layer 5.

[0042] Next, execute S6, refer to Figure 8 A reverse etching process is performed to remove the remaining protective polysilicon layer 6, silicon nitride layer 5, and the top portion of the gate polysilicon layer 4 until the remaining gate polysilicon layer 4 reaches the target thickness. The target thickness can be set according to device size, functional requirements, and other specific factors. After the reverse etching process, the depth of the low-lying area on the surface of the remaining gate polysilicon layer 4 is less than the depth of the first low-lying area 41, meaning the surface of the gate polysilicon layer 4 is smoother, thus improving the load problem and enhancing the uniformity of the device gate height.

[0043] Reference Figure 9 and 10 The figures show the online film thickness measurement results before and after using this method, respectively. It can be seen that compared to... Figure 9 , Figure 10 The variation range of the medium film thickness was significantly reduced.

[0044] This application provides a method for improving the gate height uniformity of a device. By using a gate polysilicon layer-silicon nitride layer-protective polysilicon layer film structure instead of the existing gate polysilicon layer-silicon nitride layer-protective oxide layer film structure, during the chemical mechanical polishing process, the inhibitor in the polishing slurry slows down the polishing rate of the protective polysilicon layer 6 under the low-lying area. This results in a reduction in the depth of the low-lying area on the remaining gate polysilicon layer 4 after the subsequent etch-back process, making the surface of the remaining gate polysilicon layer 4 smoother and improving the gate height uniformity of the final device.

[0045] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for improving the gate height uniformity of a device, characterized in that, include: S1: A substrate is provided, an oxide layer is formed on the surface of the substrate, and a plurality of protrusions are formed on the substrate at intervals, the protrusions penetrating the oxide layer and protruding above the oxide layer; S2: A gate polysilicon layer is deposited on the oxide layer, the gate polysilicon layer is higher than the protrusion structure, and a first low-lying region is formed on the surface of the gate polysilicon layer; S3: A silicon nitride layer is deposited on the surface of the gate polysilicon layer, and a second low-lying region is formed on the surface of the silicon nitride layer, the second low-lying region being located above the first low-lying region; S4: A protective polysilicon layer is formed on the silicon nitride layer, and a third low-lying region is formed on the surface of the protective polysilicon layer, the third low-lying region being located above the second low-lying region; The thickness of the deposited protective polysilicon layer is greater than the thickness of the gate polysilicon layer; S5: Perform a chemical mechanical polishing process on the protective polysilicon layer and stop on the surface of the silicon nitride layer. The polishing slurry used in the chemical mechanical polishing process contains an inhibitor, which slows down the polishing rate of the third depression region. S6: Perform a back-etching process until the remaining thickness of the gate polysilicon layer reaches the target thickness.

2. The method for improving the uniformity of device gate height according to claim 1, characterized in that, In step S2, a gate polysilicon layer is deposited on the oxide layer using a chemical vapor deposition process.

3. The method for improving the uniformity of device gate height according to claim 1, characterized in that, In S3, a silicon nitride layer is deposited on the surface of the gate polysilicon layer using a chemical vapor deposition process.

4. The method for improving the uniformity of device gate height according to claim 1, characterized in that, After the chemical mechanical polishing process is performed on the protective polysilicon layer and the process stops on the surface of the silicon nitride layer, a protective polysilicon layer remains in the second depression area on the surface of the silicon nitride layer. The remaining protective polysilicon layer is removed in the etch-back process.

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