Substrate and method for manufacturing same

Abstract

The invention provides a substrate and a method of manufacturing the same. A substrate according to an implementation includes a glass core having an upper surface. The Rs / z value of the ratio value of the roughness to the degree of asymmetry of the upper surface of the glass core according to the following formula 1 is-5 nm <-2 > to 50 nm <-2 >; in the formula 1: # imgabs0 #, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm). In the case of such a substrate, an electrically conductive layer can be achieved which has a substantially uniformly improved bonding force for the glass core. The conductive layer is configured so as to be capable of efficiently transmitting a signal even when high-frequency power is applied.

Description

Technical Field

[0001] The implementation example relates to a substrate and a manufacturing method thereof. Background Art

[0002] In the manufacture of electronic products, the realization of circuits on semiconductor chips is called the front-end process (FE), and the assembly of chips into a state that can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] Recently, the four core technologies of the semiconductor industry that enable the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as line widths of nanometer units below microns, more than tens of millions of cells, high-speed operation, and large amounts of heat dissipation, but there is no corresponding perfect packaging technology to back it up. Therefore, compared to the performance of semiconductor technology itself, the electrical performance of semiconductors depends more on packaging technology and its corresponding electrical connections.

[0004] As the material of the package substrate, ceramic or resin is suitable. In the case of a ceramic substrate, the resistance value is high or the dielectric constant is high, so it is not easy to mount high-performance and high-frequency semiconductor components. In the case of a resin substrate, relatively high-performance and high-frequency semiconductor components can be mounted, but there are limitations in reducing the pitch of wiring.

[0005] Recently, research is being conducted on the use of silicon or glass as a high-end packaging substrate. By forming through holes in a silicon or glass substrate and applying a conductive material to the through holes, the wiring length between the element and the motherboard can be shortened and excellent electrical characteristics can be achieved.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Japanese Patent Publication No. 2014-201446

[0009] International Patent Publication No. 2018 / 221379 Summary of the invention

[0010] Technical problems to be solved

[0011] An object of an implementation example is to provide a substrate and a method for manufacturing the same, which can realize a conductive layer having substantially uniform and improved bonding strength and capable of effectively transmitting signals even when high-frequency power is applied.

[0012] Technical solutions to solve problems

[0013] According to an embodiment of the present specification, the substrate includes a glass core having an upper surface. The upper surface of the glass core has a roughness to asymmetry ratio value R of the following formula 1: s / z The value is -5nm -2 Up to 50nm -2 .

[0014] (Formula 1)

[0015]

[0016] In Formula 1, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

[0017] The Rsk value may be -0.5 to 1.8.

[0018] The Rz value may be 3 nm to 30 nm.

[0019] The upper surface of the glass core may include a total of 3 measurement areas selected arbitrarily.

[0020] The standard deviation of the Rsk values ​​of the respective measurement areas may be 0.5 or less.

[0021] The standard deviation of the Rz values ​​of the respective measurement regions may be 1.5 nm or less.

[0022] The substrate may include: a conductive layer disposed on the glass core.

[0023] The conductive layer may include a seed layer and a conductive layer disposed on the seed layer.

[0024] The seed layer may have a thickness of 50 nm to 1500 nm.

[0025] The conductive layer may have a pattern shape.

[0026] The conductive layer may have a width of 1 μm to 5 μm.

[0027] The thickness of the conductive layer may be 1 μm to 5 μm.

[0028] The conductive layer may include a first conductive layer formed in contact with an upper surface of the glass core.

[0029] When viewed from a cross section of the first conductive layer, a maximum height roughness Rz value of an interface formed between the first conductive layer and the glass core may be 5 nm to 200 nm.

[0030] A bonding force between the first conductive layer and the glass core measured by a 180° peel test may be 0.2 kgf to 3 kgf.

[0031] The substrate may be used for semiconductor packaging.

[0032] According to another embodiment of the present specification, a method for manufacturing a substrate includes: a preparation step of preparing a basic glass plate; and a roughening step of preparing a substrate, wherein the substrate includes a glass core formed by roughening an upper surface of the basic glass plate.

[0033] The glass core has an upper surface.

[0034] The roughness to asymmetry ratio value R of the upper surface of the glass core is given by the following formula 1: s / z The value is -5nm -2 Up to 50nm -2 .

[0035] (Formula 1)

[0036]

[0037] In Formula 1, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

[0038] The roughening step may include a process of plasma treating the upper surface of the base glass sheet to form a glass core.

[0039] Technical Effects

[0040] In the case of the substrate of the embodiment, a conductive layer having substantially uniformly improved bonding strength to a glass core can be realized, and the conductive layer is configured to effectively transmit a signal even when high-frequency power is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 FIG. 1 is a top view of a substrate according to an embodiment of the present specification.

[0042] Figure 2 is a top view of a substrate according to another embodiment of the present specification.

[0043] Figure 3 is a top view of a substrate according to still another embodiment of the present specification.

[0044] Figure 4 is a top view of a substrate according to still another embodiment of the present specification.

[0045] Description of Reference Numerals

[0046] 100: substrate; 10: glass core; 11: upper surface of glass core; 12: lower surface of glass core; 20: conductive layer; 21: seed layer; 22: conductive layer; 25: first conductive layer; 26: second conductive layer; 30: insulating layer; 50: core distribution layer; L: interface formed between the first conductive layer and the glass core DETAILED DESCRIPTION

[0047] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those with common knowledge in the technical field to which the present invention belongs can easily implement it. However, the present invention can be implemented in various forms and is not limited to the embodiments described herein. In the entire specification, the same reference numerals are given to similar parts.

[0048] Throughout this specification, the term "combination of these" included in the Markush form expression refers to a mixture or combination of one or more selected from the group consisting of the constituent elements described in the Markush form expression, and means that one or more selected from the group consisting of the constituent elements is included.

[0049] Throughout the present specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. In addition, for singular expressions, unless otherwise clearly defined in the text, plural expressions are included.

[0050] In the present specification, "~" may refer to a compound containing a compound corresponding to "~" or a derivative of "~".

[0051] In this specification, disposing B on A means disposing B on A in direct contact with A or disposing B on A with another layer between A and B, and is not limited to disposing B in contact with the surface of A.

[0052] In this specification, the meaning of connecting B on A is that A and B are directly connected or connected through other components between A and B, and unless otherwise specified, it is not limited to the direct connection between A and B.

[0053] In the present specification, unless otherwise specified, an expression in the singular number is interpreted as including the singular or plural number as interpreted in the context.

[0054] In this specification, the shapes, relative sizes, angles, etc. of various structures in the drawings are exemplary and may be exaggerated for the purpose of explanation, and should not be interpreted as limiting the scope of rights to the drawings.

[0055] In this specification, A and B are adjacent to each other, which means that A and B are arranged in contact, or A and B are arranged close to each other without contacting each other. In this specification, the expression that A and B are adjacent to each other should not be interpreted as limited to A and B being arranged in contact unless otherwise specified.

[0056] In this specification, high frequency refers to a frequency of about 1 GHz to about 300 GHz, and more specifically, may refer to a frequency of about 1 GHz to about 30 GHz, and may refer to a frequency of about 1 GHz to about 15 GHz.

[0057] In this specification, unless otherwise specified, a fine line refers to a line having a width of 5 μm or less, and as an example, refers to a line having a width of 1 μm to 4 μm or less.

[0058] The inventor of the implementation example confirmed that by controlling the roughness characteristics of the glass core surface, etc., it is possible to realize a conductive layer that has an overall uniformly improved bonding force to the glass core surface, and when high-frequency power is applied, the excessive increase in resistance of the conductive layer is suppressed so that the signal can be transmitted efficiently, thereby completing the implementation example.

[0059] The following is a specific description of an implementation example.

[0060] Figure 1 1 is a top view of a substrate according to an embodiment of the present specification. Figure 1 , describing the substrate of the implementation example.

[0061] Glass core

[0062] The substrate 100 according to an embodiment of the present specification includes a glass core 10 having an upper surface 11 .

[0063] The glass core 10 plays a role of a supporter in the substrate 100. The glass core 10 is distinguished from a core distribution layer (not shown) or a bump (not shown) disposed above or below the glass core 10.

[0064] Implementation Example Using a core made of glass material can suppress the generation of parasitic elements and power loss in the core due to the application of high-frequency power.

[0065] As an example, the material of the glass core 10 may be alkali borosilicate, alkali-free borosilicate, alkali-free alkaline earth borosilicate, or the like, and any material may be used as long as it is a plate glass material used as an electronic component.

[0066] The thickness of the glass core 10 may be 50 μm or more. The thickness may be 100 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. When the glass core 10 having such a thickness is used, it can have excellent utilization as a core for semiconductor packaging.

[0067] The roughness to asymmetry ratio R of the glass core upper surface 11 is given by the following formula 1: s / z The value is -5nm -2 Up to 50nm -2 .

[0068] (Formula 1)

[0069]

[0070] In Formula 1, Rsk is the asymmetry value, and Rz is the maximum height of profile (unit: nm).

[0071] In the case where the roughness of the glass core upper surface 11 is simply increased in order to improve the bonding force of the conductive layer to be formed on the glass core upper surface 11, the height deviation of the metal layer deposited on the core upper surface may be too large, or the contact area between the core upper surface and the conductive layer may be reduced. Therefore, the conductive layer formed on the upper surface may have a problem of uneven bonding force as a whole.

[0072] In addition, the conductive layer formed on the upper surface 11 of the glass core having the above characteristics may have too high resistance in an environment where high-frequency power is supplied. Specifically, when high-frequency power is applied to the substrate 100 in order to increase the transmission speed and transmission amount of the signal, a skin effect may occur in the conductive layer. Therefore, the current may flow concentratedly on the surface of the conductive layer.

[0073] When a conductive layer is formed on the upper surface 11 of the glass core with excessive roughness, the cross-sectional profile of the conductive layer may have a rough and irregular shape. When a high-frequency current flows through the conductive layer having such a shape, the area in which the current can substantially flow is reduced in the conductive layer, and the resistance of the conductive layer may become quite high. The degree of resistance increase of the conductive layer caused by the wrinkle effect is greater as the conductive layer is thinner.

[0074] The implementation example can control the ratio of the roughness to the asymmetry of the upper surface 11 of the glass core. s / zIn this case, while the roughness of the glass core upper surface 11 is not excessively increased on the glass core 10, a more stable interlocking structure between the glass core 10 and the conductive layer can be formed on the entire glass core upper surface 11, thereby effectively improving the bonding force of the conductive layer as a whole. At the same time, in the substrate 100 having the above-mentioned characteristics, even if high-frequency power is applied, signals can be efficiently transmitted without excessive heat generation.

[0075] For R s / z The value can be measured by the following method.

[0076] A total of three measurement regions (not shown) arbitrarily selected are designated on the glass core upper surface 11. The measurement regions are regions of 5 μm in the lateral direction and 5 μm in the longitudinal direction, and the respective measurement regions can be selected so as not to overlap with each other.

[0077] The Rsk value as the asymmetry value and the Rz value as the maximum height roughness in each measurement area are measured in a non-contact mode using an atomic force microscope according to the method specified in ISO 4287. As an example, the atomic force microscope may be a Parker Biotech model XE-100.

[0078] The average value of the Rsk values ​​of the respective measurement areas is taken as the Rsk value of the upper surface of the glass core. The average value of the Rz values ​​of the respective measurement areas is taken as the Rz value of the upper surface of the glass core.

[0079] Calculate R in formula 1 from the calculated Rsk and Rz values ​​of the top surface of the glass core. s / z value.

[0080] The R of the upper surface 11 of the glass core s / z The value can be -5nm -2 Up to 50nm -2 The R s / z The value can be -3nm -2 Above. s / z The value can be 0nm -2 Above. s / z The value can be 5nm -2 Above. s / z The value can be 45nm -2 The following R s / z The value can be 40nm -2 The following R s / z The value can be 30nm -2 The following Rs / z The value can be 20nm -2 The following R s / z The value can be 15nm -2 In this case, when a thin conductive layer is formed on the glass core 10, the bonding strength of the conductive layer to the glass core 10 is substantially uniformly increased over the entire area of ​​the glass core upper surface 11, and the resistance of the conductive layer can be suppressed from becoming excessively high when high-frequency power is applied.

[0081] In the surface profile, the peak is the portion that is higher than the baseline (the average height of the surface profile), and the valley is the portion that is lower than the baseline. In the implementation example, the asymmetry Rsk value of the glass core upper surface 11 is adjusted to within the range pre-set in the implementation example, thereby being able to control the shape and height distribution of the peaks and valleys distributed on the glass core upper surface 11. In the case where the glass core 10 has the above-mentioned characteristics, it is possible to prevent the peaks and valleys in the profile of the glass core upper surface 11 from being relatively narrow and sharp. Accordingly, by appropriately adjusting the surface area of ​​the glass core upper surface 11 in contact with the metal layer deposited on the upper surface 11, the metal layer can have a stable bonding force. In addition, a metal layer with a more uniform height distribution can be formed on the glass core upper surface 11.

[0082] The Rsk value of the upper surface 11 of the glass core may be -0.5 to 1.8. The Rsk value may be greater than -0.2. The Rsk value may be greater than 0. The Rsk value may be greater than 0.2. The Rsk value may be less than 1.5. The Rsk value may be less than 1.2. The Rsk value may be less than 1.0. The Rsk value may be less than 0.8. The Rsk value may be less than 0.6. In this case, the shape of the lower surface of the conductive layer in contact with the upper surface of the glass core is particularly adjusted, so that even if a wrinkle effect occurs in the conductive layer, the signal can be smoothly transmitted.

[0083] The Rz value of the upper surface 11 of the glass core may be 4 nm to 30 nm. The Rz value may be 5 nm or more. The Rz value may be 20 nm or less. The Rz value may be 10 nm or less. In this case, the peeling resistance of the conductive layer on the surface of the glass core 10 can be stably adjusted. At the same time, even if high-frequency power is applied to the conductive layer, the resistance characteristics of the conductive layer can be prevented from becoming too high.

[0084] In the implementation example, by controlling the deviation of the roughness characteristics of a plurality of different regions, it is possible to help the bonding force and resistance characteristics of the conductive layer to be formed on the glass core 10 to be uniformly exhibited on the glass core upper surface 11 as a whole.

[0085] The standard deviation of the Rsk values ​​of the respective measurement areas may be 0.5 or less.

[0086] The standard deviation of the Rz values ​​of the respective measurement regions may be 1.5 nm or less.

[0087] The standard deviation is the sample standard deviation.

[0088] The standard deviation of the Rsk values ​​of each measurement area may be 0.5 or less. The standard deviation may be 0.4 or less. The standard deviation may be 0.3 or less. The standard deviation may be 0.2 or less. The standard deviation may be 0.001 or more.

[0089] The standard deviation of the Rz values ​​of each measurement area may be 1.5 nm or less. The standard deviation may be 1 nm or less. The standard deviation may be 0.5 nm or less. The standard deviation may be 0.3 nm or less. The standard deviation may be 0.15 nm or less. The standard deviation may be 0.08 nm or less. The standard deviation may be 0.001 nm or more.

[0090] In this case, a uniform roughness characteristic can be formed on the glass core upper surface 11 as a whole.

[0091] The lower surface of the glass core may have the same roughness characteristics as the roughness characteristics of the upper surface 11 of the glass core described above. In this case, a conductive layer having uniformly improved bonding strength can be formed on the lower surface of the glass core, and the conductive layer can be applied to high-frequency power to achieve efficient signal transmission.

[0092] The description of the roughness characteristics of the lower surface of the glass core overlaps with the above content, and thus the description is omitted.

[0093] Core distribution layer

[0094] Figure 2 1 is a top view of a substrate according to another embodiment of the present specification. Figure 2 , describing the substrate of the implementation example.

[0095] The substrate 100 includes a glass core 10 having an upper surface 11. The specific structure of the substrate 100 is directly applicable to the above-mentioned Figure 1 The following description will focus on the differences.

[0096] The substrate of the implementation example may include a conductive layer 20 disposed on a glass core. The conductive layer 20 may have a pattern shape. The conductive layer 20 is formed above and / or below the glass core 10 and may perform a function of transmitting a signal.

[0097] The conductive layer 20 may have a width of 1 μm to 5 μm. The width may be 4.5 μm or less. The width may be 4 μm or less.

[0098] The conductive layer 20 may have a thickness of 1 μm to 5 μm. The thickness may be 4.5 μm or less. The thickness may be 4 μm or less.

[0099] In this case, a high-density pattern of the conductive layer 20 can be realized on the substrate 100 , which can help the conductive layer 20 have a stable resistance characteristic under high-frequency current.

[0100] Figure 3 1 is a top view of a substrate according to another embodiment of the present specification. Figure 3 , describing the substrate of the implementation example.

[0101] The substrate 100 includes a glass core 10 having an upper surface 11. The specific structure of the substrate 100 is directly applicable to the above-mentioned Figure 1 and Figure 2 The following description will focus on the differences.

[0102] The conductive layer 20 may include a seed layer 21 and a conductive layer 22 disposed on the seed layer 21 .

[0103] The seed layer 21 can exhibit a bonding force of a predetermined level or more to the surface of the bonding object (especially, the upper surface 11 of the glass core). The conductive layer 22 can be stably bonded to the surface of the glass core 10 through the seed layer 21 .

[0104] The seed layer 21 may contain an element different from the metal element applicable to the conductive layer. The seed layer 21 may contain a metal element applicable to the conductive layer and a metal element different from the metal element. The seed layer 21 may include a first seed layer (not shown) and a second seed layer (not shown), wherein the first seed layer contains an element different from the metal element applicable to the conductive layer, and the second seed layer is arranged on the first seed layer and contains the same element as the metal element applicable to the conductive layer. As an example, the first seed layer may contain a material such as titanium, chromium, nickel, etc., and the second seed layer may contain a material such as copper, nickel, aluminum, gold or silver.

[0105] At least a portion of the seed layer 21 may be formed by a sputtering process. The seed layer 21 may help to easily form the conductive layer 22 on the glass core 10.

[0106] In an implementation example, by adjusting the thickness of the seed layer 21 , a structure in which the upper surface 11 of the glass core with controlled roughness characteristics and the seed layer 21 are stably matched can be formed.

[0107] The thickness of the seed layer 21 may be 50 nm to 1500 nm. The thickness may be 80 nm or more. The thickness may be 100 nm or more. The thickness may be 150 nm or more. The thickness may be 200 nm or more. The thickness may be 250 nm or more. The thickness may be 300 nm or more. The thickness may be 1200 nm or less. The thickness may be 1000 nm or less.

[0108] In this case, the seed layer 21 may contribute to the excellent bonding force of the conductive layer 20 , and the conductive layer 20 can be efficiently formed.

[0109] The conductive layer 22 may be formed on the seed layer 21 by a gold plating process. A conductive material may be used as a material for the conductive layer 22. As an example, the conductive layer 22 may include at least one of copper, nickel, aluminum, gold, or silver.

[0110] Figure 4 1 is a top view of a substrate according to another embodiment of the present specification. Figure 4 , describing the substrate of the implementation example.

[0111] The substrate 100 includes a glass core 10 having an upper surface 11. The specific structure of the substrate 100 is directly applicable to the above-mentioned Figures 1 to 3 The following description will focus on the differences.

[0112] The substrate 100 may include a core distribution layer 50 disposed on the glass core 10. The core distribution layer 50 may include a conductive layer 20 and an insulating layer 30 surrounding at least a portion of the conductive layer 20.

[0113] The core distribution layer 50 may be mixed with the insulating layer 30 and the conductive layer 20. The core distribution layer 50 may be formed in a form in which the conductive layer 20 having a predetermined position and form is buried in the insulating layer 30. The conductive layer 20 may be formed as a thin line at least in a portion of the core distribution layer 50.

[0114] The core distribution layer 50 may be formed by repeatedly forming and removing the insulating layer 30 and the conductive layer 20 .

[0115] As for the insulating layer 30, any material that can be used as an insulating layer in a semiconductor element or a package substrate can be used. As an example, an epoxy resin containing a filler can be used for the insulating layer 30. As an example, the insulating layer 30 can be formed by a stacked laminate material such as ABF (Ajinomoto Build-up Film) of Ajinomoto Co., Ltd., a primer material, etc., but is not limited thereto.

[0116] The insulating layer 30 may be formed by laminating uncured or semi-cured insulating films and then curing them.

[0117] The conductive layer 20 may include a first conductive layer 25 disposed in contact with the surface of the glass core 10. The conductive layer 20 may include a second conductive layer 26 not in contact with the surface of the glass core 10.

[0118] When viewed from a cross section of the first conductive layer 25 , the Rz value of the maximum height roughness of the interface L formed between the first conductive layer and the glass core may be 5 nm to 200 nm.

[0119] In an implementation example, the roughness characteristics of the interface L formed between the first conductive layer and the glass core can be controlled. Thus, while the resistance and heat generation characteristics of the first conductive layer 25 caused by the wrinkle effect are stably controlled, the bonding force of the first conductive layer 25 to the glass core 10 can be further improved through the anchor effect.

[0120] The Rz value of the interface L can be measured by the following method.

[0121] The cross section of the first conductive layer 25 is photographed by a transmission electron microscope (TEM). The cross section of the first conductive layer 25 refers to a cross section in a direction perpendicular to the upper surface 11 of the glass core. In the case where the first conductive layer 25 has a pattern shape, the cross section of the first conductive layer 25 refers to a cross section in a direction perpendicular to the upper surface 11 of the glass core and perpendicular to the length direction of the first conductive layer 25. After tracing the outline of the interface L formed between the first conductive layer and the glass core from the cross-sectional image of the first conductive layer 25, the Rz value of the maximum height roughness of the interface L is calculated from the traced outline.

[0122] The Rz value is measured according to the method specified in ISO 4287. Specifically, in the traced profile of the interface L, the sum of the height value of the highest peak and the depth value of the lowest valley is the Rz value.

[0123] The Rz value of the interface L formed between the first conductive layer and the glass core may be 200 nm or less. The Rz value may be 180 nm or less. The Rz value may be 150 nm or less. The Rz value may be 100 nm or less. The Rz value may be 5 nm or more. The Rz value may be 10 nm or more. In this case, a first conductive layer 25 having excellent peeling resistance and suitable for application of high-frequency power may be realized on the surface of the glass core 10.

[0124] In an implementation example, by controlling the bonding force of the first conductive layer 25 to the surface of the glass core to be above a predetermined level, it is possible to help prevent the first conductive layer 25 from being peeled off during the manufacturing and processing of the substrate.

[0125] The bonding strength between the first conductive layer 25 and the glass core 10 measured by a 180° peel test is measured using an adhesive tester. When measuring the bonding strength, the measuring speed (peeling speed) is set to 10 mm / s and the measuring distance (peeling distance) is set to 70 mm. As an example, the bonding strength can be measured using a push-pull tester (Condor Sigma) of XYZ TEC.

[0126] The bonding force between the first conductive layer 25 and the glass core 10 measured by the 180° peel test may be greater than 0.2 kgf. The bonding force may be greater than 0.3 kgf. The bonding force may be greater than 0.4 kgf. The bonding force may be less than 3 kgf. In this case, the conductive layer 20 may be stably bonded and formed on the surface of the glass core 10 during the manufacturing and processing of the substrate.

[0127] Other components in the package substrate

[0128] The glass core 10 may include a core through hole (not shown) that penetrates the glass core 10 in the thickness direction. The core distribution layer 50 may be formed on the glass core upper surface 11 and in the core through hole. The core distribution layer 50 may be formed above the glass core upper surface 11, below the glass core lower surface 12, and in the core through hole. In this case, the core distribution layer 50 can connect the upper surface 11 and the lower surface 12 of the glass core at a relatively short distance. In addition, electrical signals can be transmitted more quickly between components and the like arranged on the upper portion of the substrate 100 and a motherboard arranged on the lower portion of the substrate 100, and the occurrence of signal loss can be suppressed.

[0129] The core through hole may include an inner space and a side surface surrounding the inner space. In the core through hole, the conductive layer may be formed in contact with the side surface of the core through hole. The conductive layer may be formed to fill the inner space of the core through hole.

[0130] The core through hole can be formed by processing a predetermined area in the glass core 10. Specifically, the core through hole is formed by physically and / or chemically etching the glass core 10. As an example, as a method of forming the core through hole, after forming a defect on the surface of the glass core 10 by a laser or the like, a chemical etching method, a laser etching method, etc. can be applied.

[0131] A cavity region (not shown) for accommodating components may be disposed in the glass core 10. The cavity region may include an accommodating portion, which is a space formed by a portion of the glass core 10 being recessed. The accommodating portion may be formed by penetrating the glass core 10 from top to bottom. The accommodating portion may be formed by a portion of the upper or lower portion of the glass core 10 being recessed.

[0132] The components can be placed in the receiving portion. As for the components, in addition to semiconductor components such as CPU, GPU, memory chip, etc., capacitor components, transistor components, impedance components and other modules can also be used. In other words, as long as it is a semiconductor component installed in a semiconductor device, it can be used as the above-mentioned component without limitation.

[0133] The substrate 100 may further include an upper layer (not shown) on the core distribution layer 50 disposed on the glass core 10 .

[0134] The upper layer may include an upper distribution layer and an upper surface contact layer disposed on the upper distribution layer. The elements disposed on the substrate 100 may be electrically connected to the substrate 100 through the upper surface contact layer.

[0135] The upper distribution layer may include a conductive layer and an insulating layer surrounding at least a portion of the conductive layer. The conductive layer and the insulating layer of the upper distribution layer may be made of the same materials as the conductive layer and the insulating layer of the core distribution layer. The upper distribution layer may electrically connect the element and the core distribution layer.

[0136] The substrate 100 may further include a lower layer (not shown) below the core distribution layer (not shown) disposed on the side of the glass core lower surface 12 .

[0137] The lower layer may include a lower distribution layer and a board connection portion disposed below the lower distribution layer. The main board disposed below the substrate 100 may be electrically connected to the substrate 100 through the board connection portion. The core distribution layer may be electrically connected to the main board via the lower layer.

[0138] The lower distribution layer may include a conductive layer and an insulating layer surrounding at least a portion of the conductive layer. The conductive layer and the insulating layer of the lower distribution layer may be made of the same materials as the conductive layer and the insulating layer of the core distribution layer.

[0139] The substrate 100 may be used for semiconductor packaging, and may be used to mount semiconductor elements, protect semiconductors, and electrically connect elements and a motherboard.

[0140] Semiconductor packaging

[0141] A semiconductor package according to still another embodiment of the present specification includes a substrate 100 and a main board (not shown) electrically connected to the substrate.

[0142] The substrate 100 can be mounted on a mainboard and electrically connected to the mainboard. The mainboard is not limited as long as it is generally applicable to the field of semiconductor devices.

[0143] The description of the substrate 100 overlaps with the above content, so the description is omitted.

[0144] Method for manufacturing substrate

[0145] A method for manufacturing a substrate according to still another embodiment of the present specification includes: a preparation step of preparing a base glass plate; and a roughening step of preparing a substrate including a glass core formed by roughening an upper surface of the base glass plate.

[0146] The glass core has an upper surface, and the roughness to asymmetry ratio value R of the upper surface of the glass core is given by the following formula 1 s / z The value is -5nm -2 Up to 50nm -2 .

[0147] (Formula 1)

[0148]

[0149] In Formula 1, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

[0150] In the manufacturing step, the base glass sheet may be processed to prepare a glass core.

[0151] As for the basic glass plate, any plate glass material used as electronic components can be used. As examples, the basic glass plate can be an alkali borosilicate glass plate, an alkali-free borosilicate glass plate, an alkali-free alkaline earth borosilicate glass plate, etc. As examples, commercially available products manufactured by manufacturers such as Corning, Schott, and AGC can be used as the basic glass plate.

[0152] The roughening step of the implementation example may include: a process of plasma treating the upper surface of the base glass plate to form a glass core. The roughening step may include: a process of plasma treating the upper surface of the base glass plate by an inert gas to form a glass core. Accordingly, a glass core having an upper surface with adjusted roughness characteristics can be prepared to avoid excessive roughness while having an asymmetry within a range preset in the implementation example.

[0153] The inert gas may be any one selected from the group consisting of helium, argon, xenon, krypton, and combinations thereof. The inert gas may be argon. In this case, while suppressing chemical changes in the upper surface of the base glass sheet in the roughening step, it is possible to help form a glass core having a desired surface roughness characteristic in the embodiment.

[0154] In the roughening step, the atmosphere pressure may be 100 mTorr or less. The atmosphere pressure may be 80 mTorr or less. The atmosphere pressure may be 50 mTorr or less. The atmosphere pressure may be 30 mTorr or less. The atmosphere pressure may be 1 mTorr or more. In this case, the ionized inert gas collides with the surface of the roughening object without much hindrance in the roughening step, so that the roughness characteristics of the upper surface of the glass core can be easily adjusted.

[0155] In the roughening step, the flow rate of the introduced inert gas may be 100 sccm or more. The flow rate may be 150 sccm or more. The flow rate may be 200 sccm or more. The flow rate may be 1000 sccm or less. In this case, a sufficient amount of ionized inert gas may collide with the upper surface of the base glass plate at an appropriately adjusted speed.

[0156] In the roughening step, the source power may be 0.1 kW or more. The source power may be 0.3 kW or more. The source power may be 0.5 kW or more. The source power may be 5 kW or less.

[0157] In the roughening step, the bias power may be 0.1 kW or more. The bias power may be 0.3 kW or more. The bias power may be 0.5 kW or more. The bias power may be 1 kW or more. The source power may be 8 kW or less. The source power may be 5 kW or less.

[0158] In this case, by adjusting the movement speed of the ionized inert gas within an appropriate range, it is possible to help form a glass core having a desired surface roughness characteristic.

[0159] The roughening step may be performed for more than 10 seconds. The roughening step may be performed for more than 15 seconds. The roughening step may be performed for more than 30 seconds. The roughening step may be performed for less than 1000 seconds. This may help to form a glass core upper surface having a roughness and asymmetry within a range preset in the implementation example.

[0160] In addition to being performed on the upper surface of the base glass plate, the roughening step can also be performed on the lower surface of the base glass plate. The roughening step in the above manner can be applied to the lower surface of the base glass plate.

[0161] According to the requirements, a core through hole can be formed in the glass core. Specifically, a defect can be formed at a predetermined position on the surface of the glass core. The core through hole can be formed by physically or chemically etching the defect. The description of the method for forming the core through hole is repeated with the above content, so the description is omitted.

[0162] The manufacturing method of the substrate of the implementation example may further include: a core distribution layer forming step of forming a core distribution layer on the glass core.

[0163] The description of the core distribution layer overlaps with the above content, so the description is omitted.

[0164] The core distribution layer forming step may include: a conductive layer forming process of forming a conductive layer on the glass core; and an insulating layer forming process of forming an insulating layer surrounding at least a portion of the conductive layer.

[0165] In the process of forming the conductive layer, the sputtering process conditions pre-set in the implementation example are applied to form the seed layer, which can suppress the roughness characteristics of the upper surface of the glass core from being excessively changed due to the collision of sputtered particles with the upper surface of the glass core. Accordingly, the seed layer formed by sputtering forms a stable interlocking structure with the surface of the glass core on the entire upper surface of the glass core, which can help to improve the bonding force of the conductive layer. In addition, it can help to effectively suppress the increase in resistance of the conductive layer caused by the wrinkle effect.

[0166] The seed layer may include a first seed layer and a second seed layer disposed on the first seed layer, the first seed layer including an element different from a metal element applicable to the conductive layer, and the second seed layer including an element the same as a metal element applicable to the conductive layer. As an example, the first seed layer may include a material such as titanium, chromium, nickel, etc., and the second seed layer may include a material such as copper, nickel, aluminum, gold, or silver.

[0167] The description of the seed layer overlaps with the above content, so the description is omitted.

[0168] In the sputtering process for forming the seed layer, the atmospheric pressure may be greater than or equal to 0.1 Pa. The pressure may be greater than or equal to 0.3 Pa. The pressure may be less than or equal to 5 Pa. In this case, the seed layer can be formed at a more improved deposition speed.

[0169] The sputtering power applicable in the sputtering process for forming the seed layer may be 10 kW or more. The sputtering power may be 15 kW or more. The sputtering power may be 20 kW or more. The sputtering power may be 100 kW or less. The sputtering power may be 50 kW or less. In this case, the sputtered particles may have regulated kinetic energy and collide with the surface of the deposition object. Accordingly, while the seed layer is more firmly formed on the glass core, the roughness characteristics of the surface of the glass core can be prevented from changing excessively.

[0170] In the sputtering process for forming the seed layer, the initial temperature of the substrate bed as the substrate holder may be 180° C. or less. The temperature may be 150° C. or less. The temperature may be 30° C. or more. In this case, adjusting the movement characteristics of the deposited sputtered particles can further improve the durability of the seed layer.

[0171] In the sputtering process for forming the seed layer, the sputtering gas may be an inert gas, which may be argon.

[0172] The sputtering process for forming the first seed layer may be performed for more than 1 minute, more than 2 minutes, or less than 20 minutes.

[0173] The sputtering process for forming the second seed layer may be performed for more than 1 minute, more than 2 minutes, or less than 20 minutes.

[0174] In this case, a seed layer having a structure stably connected to the upper surface of the glass core can be formed.

[0175] After the formation of the seed layer is completed, the portion where the conductive layer is not required to be formed can be removed from the seed layer. In the seed layer, the portion where the conductive layer is required to be formed and the portion where the conductive layer is not required to be formed can be subjected to gold plating activation / deactivation treatment respectively. As an example, the gold plating activation / deactivation treatment can be applied to light irradiation treatment using a laser of a specific wavelength, chemical treatment, etc. However, the above-mentioned treatment may not be applied, and a conductive layer may be formed on the seed layer.

[0176] The description of the structure and material of the seed layer overlaps with the above content, so the description is omitted.

[0177] By a gold plating process, a conductive layer is formed on the seed layer, and then a conductive layer can be prepared. The description of the material of the conductive layer is repeated with the above content, so the description is omitted. After the conductive layer is formed, the conductive layer can be etched so that the conductive layer has a pre-designed pattern shape.

[0178] After forming the conductive layer, an insulating layer surrounding at least a portion of the conductive layer is disposed, and the core distribution layer can be formed. As an example, the insulating layer can be applied to an epoxy resin containing a filler. As an example, the insulating layer can be formed by a stacked laminate material such as Ajinomoto's Ajinomoto ABF, a primer material, etc., but is not limited thereto.

[0179] The insulating layer may be formed by laminating uncured or semi-cured insulating films and then curing them.

[0180] The core distribution layer forming step may be a step of forming a core distribution layer on the glass core. The core distribution layer forming step may be a step of forming a core distribution layer above and below the glass core. The core distribution layer forming step may be a step of forming a core distribution layer above and below the glass core and in the core through-hole. The description of the method of forming the core distribution layer above and below the glass core and in the core through-hole is repeated in the above content, so the description is omitted.

[0181] According to the requirements, the manufacturing method of the substrate of the implementation example may further include: forming an upper distribution layer above the core distribution layer arranged on the glass core. The upper distribution layer includes a conductive layer and an insulating layer surrounding at least a portion of the conductive layer.

[0182] The manufacturing method of the substrate of the implementation example may further include: forming a lower distribution layer and / or a bump below the core distribution layer below the glass core. The lower distribution layer includes a conductive layer and an insulating layer surrounding at least a portion of the conductive layer.

[0183] The conductive layer and the insulating layer applicable to the upper distribution layer and the lower distribution layer may be made of the same materials and manufactured by the same method as those applicable to the conductive layer and the insulating layer applicable to the core distribution layer.

[0184] The following specific embodiments are described in more detail. The following embodiments are only examples to help understand the present invention, and the scope of the present invention is not limited thereto.

[0185] Manufacturing example: Manufacturing substrate

[0186] Example 1: An alkali-free glass plate from Schott was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 10 to 30 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 0.8 kW, and the bias power was 0.8 kW.

[0187] Example 2: A soda lime glass plate from Schott was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 10 to 30 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 0.5 kW, and the bias power was 0.5 kW.

[0188] Example 3: A SG 7.8 glass plate from Corning was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 20 seconds to 40 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 0.5 kW, and the bias power was 0.5 kW.

[0189] Example 4: An alkali-free glass plate from Schott was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 20 to 40 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.0 kW, and the bias power was 1.0 kW.

[0190] Example 5: An alkali-free glass plate from Schott was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 30 to 50 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.2 kW, and the bias power was 1.5 kW.

[0191] Comparative Example 1: A SG7.8 glass plate from Corning was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 90 seconds to 120 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.2 kW, and the bias power was 2.0 kW.

[0192] Comparative Example 2: An alkali-free glass plate from Schott was used as a base glass plate, and an argon plasma treatment was performed on the surface of the base glass plate for 90 to 120 seconds to prepare a glass core. During the argon plasma treatment, the atmosphere pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.5 kW, and the bias power was 2.5 kW.

[0193] Evaluation example: Roughness characteristics measurement

[0194] A total of three measurement areas with a width of 5 μm and a length of 5 μm were randomly selected on the upper surface of the glass core of the example and the comparative example. The measurement areas were selected so as not to overlap with each other.

[0195] According to ISO 4287, the Rsk value and the Rz value of each measurement area were measured in a non-contact mode using an atomic force microscope XE-100 manufactured by Parker Biotechnology.

[0196] The average value of the Rsk values ​​of the respective measurement areas was taken as the Rsk value of the upper surface of the glass core, and the average value of the Rz values ​​of the respective measurement areas was taken as the Rz value of the upper surface of the glass core.

[0197] Calculate R from the Rsk value and Rz value s / z value.

[0198] The measurement and calculation results of different embodiments and comparative examples are recorded in the following Tables 1 and 2.

[0199] Evaluation example: Roughness uniformity measurement

[0200] The standard deviations of the Rsk value and the Rz value were calculated from the Rsk value and the Rz value measured in each measurement area on the upper surface of the glass core of the example.

[0201] The calculated values ​​according to different embodiments are recorded in Table 2 below.

[0202] Evaluation example: Conductive layer bonding strength evaluation

[0203] By sputtering, a titanium layer with a thickness of 300 nm is formed on the upper surface of the glass core of the embodiment and the comparative example, and a copper layer with a thickness of 300 nm is formed on the titanium layer to form a seed layer. In the sputtering process for forming the seed layer, the atmosphere pressure is set to 0.4 Pa, the sputtering power is set to 30 kW, and the substrate temperature is set to 120° C. The titanium layer and the copper layer are deposited by sputtering for 3 minutes respectively under the above conditions. By a copper plating process, a conductive layer with a thickness of 20 μm is formed on the seed layer to prepare a conductive layer.

[0204] Then, the bonding force of the conductive layer to the glass core was measured according to a 180° peel test using an adhesion tester (Condor Sigma) manufactured by XYZ TEC.

[0205] The measurement results of different embodiments and comparative examples are recorded in Table 1 below.

[0206] Evaluation example: Evaluation of whether the conductive layer peels off

[0207] A 300 nm thick titanium layer was formed on the upper surface of the glass core of the embodiment and the comparative example by sputtering, and a 300 nm thick copper layer was formed on the titanium layer to form a seed layer. A 20 μm thick conductive layer was formed on the seed layer by a copper plating process to prepare a conductive layer.

[0208] The glass core having the conductive layer formed thereon is singulated. Specifically, a laser device is used to irradiate energy along a dicing path on the upper surface of the glass core, and a physical force is applied to cut the glass core. Then, the edges of the cut glass core are ground.

[0209] The cross section of the cut glass core was checked using an optical microscope to determine whether the conductive layer had peeled off.

[0210] According to the different examples and comparative examples, the case where no peeling of the conductive layer occurred was evaluated as P, and the case where peeling of the conductive layer occurred was evaluated as F.

[0211] The measurement results of different embodiments and comparative examples are recorded in Table 1 below.

[0212] Table 1

[0213]

[0214] Table 2

[0215]

[0216] In Table 1, the Rs / z value is controlled at -5nm -2 Up to 50nm -2 In the case of Examples 1 to 5, the conductive layer exhibited a bonding force of 0.2 kgf or more, and no peeling of the conductive layer occurred in the peeling evaluation. On the other hand, in the case of Rs / z values ​​less than -5 nm -2 or greater than 55nm -2 In the case of Comparative Examples 1 and 2, the measured bonding force of the conductive layer was less than 0.15 kgf, and peeling of the conductive layer occurred in the peeling evaluation.

[0217] In Table 2, the standard deviation of the Rsk value of each measurement area of ​​Examples 1 to 5 was calculated to be 0.4 or less, and the standard deviation of the Rz value was calculated to be 0.9 nm or less. This means that the roughness characteristics of the upper surface of the glass core of the Examples are uniform as a whole.

[0218] The preferred embodiments of the present invention are described in detail above, but the scope of rights of the present invention is not limited thereto, and various deformations and improved forms made by practitioners in the field of the present invention using the basic concepts of the present invention defined in the attached claims also fall within the scope of rights of the present invention.

Claims

1. A substrate, wherein: including a glass core having an upper surface, The roughness to asymmetry ratio of the upper surface of the glass core is R s / z The value is -5nm -2 Up to 50nm -2 : Formula 1 In Formula 1, the Rsk value is the asymmetry value, the Rz value is the maximum height roughness, and the unit of the Rz value is nm.

2. The substrate according to claim 1, wherein The Rsk value is -0.5 to 1.

8.

3. The substrate according to claim 1, wherein The Rz value is 3 nm to 30 nm.

4. The substrate according to claim 1, wherein The upper surface of the glass core includes a total of 3 measurement areas selected arbitrarily, The standard deviation of the Rsk values ​​of the respective measurement areas is 0.5 or less.

5. The substrate according to claim 1, wherein The upper surface of the glass core includes a total of 3 measurement areas selected arbitrarily, The standard deviation of the Rz value of each of the measurement areas is 1.5 nm or less.

6. The substrate according to claim 1, wherein include: The conductive layer is disposed on the glass core.

7. The substrate according to claim 6, wherein The conductive layer includes a seed layer and a conductive layer configured on the seed layer. The seed layer has a thickness of 50 nm to 1500 nm.

8. The substrate according to claim 6, wherein The conductive layer has a pattern shape, The width of the conductive layer is 1 μm to 5 μm; The thickness of the conductive layer is 1 μm to 5 μm.

9. The substrate according to claim 6, wherein The conductive layer includes a first conductive layer, the first conductive layer is formed in contact with the upper surface of the glass core, When observed from a cross section of the first conductive layer, a maximum height roughness, ie, Rz value, of an interface formed between the first conductive layer and the glass core is 5 nm to 200 nm.

10. The substrate according to claim 6, wherein The conductive layer includes a first conductive layer, the first conductive layer is formed in contact with the upper surface of the glass core, The bonding force between the first conductive layer and the glass core measured by a 180° peel test is 0.2 kgf to 3 kgf.

11. The substrate according to claim 1, wherein The substrate is used for semiconductor packaging.

12. A method for manufacturing a substrate, in, include: a preparatory step of preparing a base glass sheet; and a roughening step of preparing a substrate, the substrate comprising a glass core formed by roughening the upper surface of the base glass plate, The glass core has an upper surface, The roughness to asymmetry ratio of the upper surface of the glass core is R s / z The value is -5nm -2 Up to 50nm -2 : Formula 1 In Formula 1, the Rsk value is the asymmetry value, the Rz value is the maximum height roughness, and the unit of the Rz value is nm.

13. The method for manufacturing a substrate according to claim 12, wherein: The roughening step comprises: The process of plasma treating the upper surface of the base glass sheet to form a glass core.

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