Semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of inspecting a bonding wire. A semiconductor device is provided with: a base (11); one or more chips comprising a semiconductor chip (20) disposed on the base; a first bonding wire (32) connected to at least one of the one or more chips; second bonding wires (41 to 44) extending in a direction intersecting with an extending direction of the first bonding wires when viewed from a thickness direction of the base; and a resin layer provided on the base and sealing the one or more chips, the first bonding wire, and the second bonding wire, the first bonding wire and the second bonding wire being not in contact, and the first bonding wire being capable of being in contact with the second bonding wire when the first bonding wire is inclined toward the second bonding wire.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known to mount a chip on a conductive base and connect a bonding wire to the chip (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-113284

[0006] When the chip and the bonding wire are sealed with resin, if the shape of the bonding wire changes, the characteristics will change. If the shape of the bonding wire in the sealing resin is inspected using an X-ray transmission inspection device, the manufacturing process will increase. Summary of the invention

[0007] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to enable inspection of bonding wires.

[0008] One embodiment of the present disclosure is a semiconductor device, comprising: a base; one or more chips, including a semiconductor chip arranged on the base; a first bonding wire connected to at least one of the one or more chips; a second bonding wire extending in a direction intersecting with an extension direction of the first bonding wire when viewed from the thickness direction of the base; and a resin layer, arranged on the base, sealing the one or more chips, the first bonding wire and the second bonding wire, the first bonding wire not contacting the second bonding wire, and being able to contact the second bonding wire when the first bonding wire is inclined toward the second bonding wire.

[0009] Effects of the Invention

[0010] According to the present disclosure, bonding wires can be inspected. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a top view of the semiconductor device of Example 1.

[0012] Figure 2 yes Figure 1 A-A section view.

[0013] Figure 3 yes Figure 1 B-B section view.

[0014] Figure 4 This is a circuit diagram of one integrated component in the semiconductor device of Example 1.

[0015] Figure 5 This is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figure 6 is a cross-sectional view of a semiconductor device according to Comparative Example 1.

[0017] Figure 7 yes Figure 6 A-A section view.

[0018] Figure 8 is a cross-sectional view of the semiconductor device of Example 1.

[0019] Fig. 9 This is a side view of the bonding wire in Example 1 when viewed from the Y direction.

[0020] Fig.10 This is a side view of the bonding wire in Example 1 when viewed from the X direction.

[0021] Fig.11 This is a top view of the bonding wire in Example 1.

[0022] Fig.12 This is a top view of the bonding wire in Example 1.

[0023] Fig.13 It is a top view of the semiconductor device of Example 2.

[0024] Fig.14 yes Fig.13 A-A section view.

[0025] Fig.15 This is a circuit diagram of an integrated circuit in the semiconductor device of Example 2.

[0026] Fig.16 It is a top view of the semiconductor device of Example 3.

[0027] Description of Reference Numerals

[0028] 10: Lead frame;

[0029] 11: base;

[0030] 12, 13: terminal;

[0031] 14: resin layer;

[0032] 16a, 16b: integrated parts;

[0033] 18: Matching circuit;

[0034] 19: VBW circuit;

[0035] 20: semiconductor chips;

[0036] 21, 26: substrate;

[0037] 22, 23, 24, 27, 27a, 27b, 28, 29: electrodes;

[0038] 25, 25a: Passive component chips;

[0039] 29a: via;

[0040] 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45, 46: bonding lines;

[0041] 36: bonding layer;

[0042] 48: conductor layer;

[0043] 50: arrow;

[0044] 100 , 102 , 104 , 110 : semiconductor devices. DETAILED DESCRIPTION

[0045] [Description of Embodiments of the Present Disclosure]

[0046] First, the contents of the embodiments of the present disclosure will be listed and described.

[0047] (1) One embodiment of the present disclosure is a semiconductor device comprising: a base; one or more chips, including a semiconductor chip disposed on the base; a first bonding wire connected to at least one of the one or more chips; a second bonding wire extending in a direction intersecting with an extending direction of the first bonding wire when viewed from a thickness direction of the base; and a resin layer disposed on the base to seal the one or more chips, the first bonding wire, and the second bonding wire, wherein the first bonding wire is not in contact with the second bonding wire, and when the first bonding wire is tilted toward the second bonding wire, the first bonding wire can be in contact with the second bonding wire. Thus, the tilt of the first bonding wire can be detected.

[0048] (2) In the above (1), the device may include: a first terminal connected to the first bonding wire in a direct current manner; and a second terminal connected to the second bonding wire in a direct current manner, wherein the base is not connected to the first terminal or the second terminal in a direct current manner. Thus, the tilt of the first bonding wire can be detected.

[0049] (3) In the above (1) or (2), when the first bonding line is inclined by 45° or more from the thickness direction of the base toward the second bonding line, the first bonding line may contact the second bonding line. Thus, the inclination of the first bonding line can be detected.

[0050] (4) In any of the above (1) to (3), when the second joining line is divided into three parts when viewed from the thickness direction of the base, the point on the second joining line that is farthest from the base is located in the part closest to the first joining line among the divided parts. In this way, the inclination of the first joining line can be detected.

[0051] (5) In any of the above (1) to (4), when viewed from the thickness direction of the base, the angle between the extending direction of the first bonding wire and the extending direction of the second bonding wire may be greater than 45°. This can reduce the influence of the second bonding wire on the characteristics of the first bonding wire.

[0052] (6) In any one of (1) to (5) above, a plurality of second joining lines may be provided, and at least two of the plurality of second joining lines may be arranged with the first joining line disposed therebetween. This allows detection of inclination of the first joining line in any direction.

[0053] (7) In any one of the above (1) to (6), both ends of the second bonding wire may be bonded to the base. Thus, the second bonding wire can be set to a reference potential.

[0054] (8) In any of the above (1) to (7), both ends of the first bonding wire may be bonded to one of the one or more chips, and a first end of the second bonding wire closer to the first bonding wire may be bonded to the one chip. Thus, the inclination of the first bonding wire bonded to the chip can be detected.

[0055] (9) In any one of (1) to (8) above, the first bonding wire may be the longest among bonding wires that transmit signals in the semiconductor device. This allows detection of the tilt of the first bonding wire that is prone to tilt.

[0056] (10) In any one of the above (1) to (9), the first bonding wire may transmit a high-frequency signal. Thus, a change in high-frequency characteristics of the first bonding wire can be detected.

[0057] (11) In the above (10), the one or more chips may include the semiconductor chip and a passive component chip, and the first bonding wire may electrically connect the semiconductor chip and the passive component chip. Thus, the tilt of the first bonding wire, which is difficult to adjust, can be detected.

[0058] [Details of the embodiments of the present disclosure]

[0059] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0060] [Example 1]

[0061] Figure 1 1 is a top view of the semiconductor device of Example 1. Figure 2 yes Figure 1 A-A section view. Figure 3 yes Figure 1 It should be noted that in Figure 2 and Figure 3 , bonding lines 31 to 33 and bonding lines 41 to 44 near the section line are also shown. The thickness direction of the base 11 is set as the Z direction, the extension direction of the straight line connecting the terminal 13 and the terminal 12 is set as the X direction, and the direction orthogonal to the X direction and the Z direction is set as the Y direction.

[0062] like Figures 1 to 3 As shown, the semiconductor device 100 of the first embodiment has the following structure: the semiconductor chip 20 and the passive component chip 25 mounted on the base 11 of the conductive lead frame 10 are sealed by the resin layer 14. The lead frame 10 has a base 11, a terminal 12 and a terminal 13. The base 11, the terminal 12 and the terminal 13 are not in contact with each other. The base 11 is a die pad, and the terminal 12 and the terminal 13 are leads. The illustration of the connecting strip connecting the base 11, the terminal 12 and the terminal 13 before cutting is omitted. The lower surface of the base 11, the terminal 12 and the terminal 13 is exposed from the lower surface of the resin layer 14.

[0063] The terminal 12, the semiconductor chip 20, the passive component chip 25, and the terminal 13 are arranged in the negative (-) direction of the X direction. There are two integrated components 16a and 16b having the terminal 12, the semiconductor chip 20, the passive component chip 25, and the terminal 13, and the two integrated components 16a and 16b are arranged in the Y direction. There can be one integrated component 16a and one integrated component 16b, or three or more integrated components.

[0064] The semiconductor chip 20 and the passive element chip 25 are mounted on the base 11. The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. The substrate 21 is, for example, a semiconductor substrate. The electrodes 22 and 23 are provided on the upper surface of the substrate 21. The electrode 24 is provided on the lower surface of the substrate 21. The passive element chip 25 includes a substrate 26, an electrode 27, and an electrode 28. The substrate 26 is, for example, a dielectric substrate. The electrode 27 is provided on the upper surface of the substrate 26, and the electrode 28 is provided on the lower surface of the substrate 26. The conductive bonding layer 36 bonds the base 11 with the electrodes 24 and 28. The electrodes 24 and 28 are electrically connected to the base 11 and short-circuited. The bonding wire 31 electrically connects the terminal 12 with the electrode 23. The bonding wire 32 electrically connects the electrode 22 with the electrode 27. The bonding wire 33 electrically connects the electrode 27 with the terminal 13.

[0065] The base 11 is provided with bonding wires 41 to 44. The bonding wire 41 is provided adjacent to the bonding wires 31 to 33 between the bonding wires 31 to 33 of the integrated part 16a and the side of the base 11 located in the positive (+) direction in the Y direction. The bonding wire 42 is provided adjacent to the bonding wires 31 to 33 of the integrated part 16a between the bonding wires 31 to 33 of the integrated part 16a and the integrated part 16b. The bonding wire 43 is provided adjacent to the bonding wires 31 to 33 of the integrated part 16b between the bonding wires 31 to 33 of the integrated part 16b and the integrated part 16a. The bonding wire 44 is provided adjacent to the bonding wires 31 to 33 between the bonding wires 31 to 33 of the integrated part 16b and the side of the base 11 located in the negative (-) direction in the Y direction.

[0066] Figure 4 FIG. 1 is a circuit diagram of an integrated circuit of the semiconductor device of Embodiment 1. Figure 4 As shown, the integrated component 16a and the integrated component 16b include a terminal 12, a terminal 13, a transistor Q, inductors L1 to L3, and a capacitor C1. The transistor Q is, for example, a FET (Field Effect Transistor), and has a source S, a gate G, and a drain D. The inductor L3 and the inductor L2 are connected in series between the terminal 13 and the gate G. The capacitor C1 is connected in shunt to a node between the inductor L3 and the inductor L2. The source S is grounded. The inductor L1 is connected between the drain D and the terminal 12. The inductor L3, the inductor L2, and the capacitor C1 are an LCL type circuit, forming a matching circuit 18. The matching circuit 18 matches the impedance when the matching circuit 18 is viewed from the terminal 13 with the impedance when the transistor Q is viewed from the matching circuit 18.

[0067] The transistor Q is provided in the semiconductor chip 20. The source S, the gate G and the drain D correspond to the electrode 24, the electrode 22 and the electrode 23, respectively. The electrode 22 is an input electrode for inputting a high-frequency signal, and the electrode 23 is an output electrode for outputting a high-frequency signal. The capacitor C1 is provided in the passive element chip 25, and corresponds to the substrate 26 and the electrode 27 and the electrode 28 across the substrate 26. The inductor L1, the inductor L2 and the inductor L3 correspond to the bonding wire 31, the bonding wire 32 and the bonding wire 33, respectively.

[0068] The high-frequency signal input to the terminal 13 is input to the gate G through the matching circuit 18. The high-frequency signal amplified by the transistor Q is output from the drain D through the inductor L1 to the terminal 12. The inductor L1 may also form a part of the matching circuit. When the semiconductor device 100 is used for an amplifier circuit for a base station of mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz to 10 GHz. The frequency of the high-frequency signal may also be above 10 GHz.

[0069] The transistor Q is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or a LDMOS (Laterally Diffused Metal Oxide Semiconductor). When the transistor Q has a GaN HEMT, the substrate 21 is, for example, a silicon carbide substrate or a gallium nitride substrate. The electrodes 22 to 24 are, for example, metal layers such as a gold layer.

[0070] When the passive element chip 25 has the capacitor C1, the substrate 26 is, for example, a dielectric substrate, such as an alumina substrate, a high dielectric ceramic substrate having a relative dielectric constant greater than that of the alumina substrate, a silicon substrate, or a gallium arsenide substrate. The electrodes 27 and 28 are, for example, metal layers such as gold layers.

[0071] Figure 5 FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device according to Embodiment 1. Figure 5 As shown, a plurality of lead frames 10 connected by connecting bars are prepared (step S10). In step S10, a semiconductor chip 20 and a passive component chip 25 are mounted on a base 11, bonding wires 31 to 33 are bonded to the semiconductor chip 20 or the passive component chip 25, and bonding wires 41 to 44 are bonded to the base 11.

[0072] Next, the frame is sealed with resin (step S12). In step S12, the frame is placed in a mold, and a resin to be the resin layer 14 is injected into the mold using a transfer molding method. Next, the resin layer 14 and the frame are cut (step S14). Figures 1 to 3 The semiconductor device 100 is completed.

[0073] Next, the semiconductor device 100 is electrically inspected (step S16). In step S16, for example, a DC measuring device is used to inspect the electrical short circuit between the terminal 12 and the base 11 and the electrical short circuit between the terminal 13 and the base 11. Next, the pass or fail of the semiconductor device 100 is determined based on the inspection result of step S16 (step S18). In step S18, for example, if the terminal 12 and the base 11 are electrically short-circuited or the terminal 13 and the base 11 are electrically short-circuited, it is determined to be failed, and if the terminal 12 and the base 11 are not electrically short-circuited and the terminal 13 and the base 11 are not electrically short-circuited, it is determined to be passed.

[0074] Next, the semiconductor device 100 determined to be acceptable in step S18 is regarded as an acceptable product (step S20 ). When regarded as an acceptable product in step S20 , for example, a seal is stamped on the semiconductor device 100 .

[0075] [Comparative Example 1]

[0076] Figure 6 is a cross-sectional view of a semiconductor device according to Comparative Example 1. Figure 7 yes Figure 6 A-A section view. Figure 6 and Figure 7 As shown, in the semiconductor device 110 of Comparative Example 1, the bonding wires 41 to 44 are not provided. The resin layer 14 is formed by, for example, transfer molding. In step S12, there are a plurality of lead frames. Figure 6 and Figure 7 The lead frame 10 is a lead frame into which the resin is injected from the negative (-) direction in the Y direction as shown by the arrow 50. In the lead frame 10, the bonding wires 31 to 33 are inclined due to the flow of the resin. In addition to the transfer molding method, when the resin layer 14 is provided by a potting method, for example, the bonding wires 31 to 33 may also be inclined when the resin flows.

[0077] exist Figure 7 In FIG. 1 , the bonding wire 32a represents before the resin is injected, and the bonding wire 32 represents after the resin is injected. The bonding wire 32 is tilted at an angle θ1. When the bonding wire 32 is tilted, the high-frequency characteristics of the bonding wire 32 change. In addition, when the angle θ1 is too large, there is a possibility of short circuit with other components. Therefore, when it is desired to inspect the tilt of the bonding wire 32, an expensive device such as an X-ray transmission inspection device is used.

[0078] [Description of Example 1]

[0079] Figure 8 is a cross-sectional view of the semiconductor device of Example 1. Figure 8 As shown in FIG. 1 , when the bonding wire 32 is tilted, the bonding wire 32 contacts the bonding wire 41 and the bonding wire 43. Thus, the terminal 13 and the base 11 are electrically short-circuited. Figure 5 In step S16, the electrical short circuit between the terminal 13 and the base 11 is checked. In step S18, if the electrical short circuit between the terminal 13 and the base 11 is found, the product is judged as defective. In this way, the inclination of the bonding wire 32 can be checked.

[0080] According to Example 1, Figures 1 to 3 In this way, the terminal 12 (first terminal) is DC-connected to the bonding wire 31 (first bonding wire), and the terminal 13 (first terminal) is DC-connected to the bonding wires 32 and 33 (first bonding wires). The base 11 (second terminal) is DC-connected to the bonding wires 41 to 44 (second bonding wires). The base 11 is not DC-connected to the terminals 12 and 13. Thus, by detecting the DC short circuit between the terminals 12 and 13 and the base 11 in step S16, the inclination of the bonding wires 31 to 33 can be detected as in step S18.

[0081] Fig. 9 This is a side view of the bonding wire in Example 1 when viewed from the Y direction. Fig.10 This is a side view of the bonding wire in Example 1 when viewed from the X direction. Fig.11 is a top view of the bonding wire in Example 1. Figures 9 to 11 , the bonding line 30 corresponds to the bonding lines 31 to 33, and the bonding line 40 corresponds to the bonding lines 41 to 44. The vertices of the bonding line 30 and the bonding line 40 are P3 and P4, respectively. The heights of the bonding line 30 and the bonding line 40 are H3 and H4, respectively. The vertex P3 and the vertex P4 of the bonding line 30 and the bonding line 40 are the points farthest from the base 11 in the bonding line 30 and the bonding line 40 as the object. The height of the bonding line 30 and the bonding line 40 is the height in the Z direction between the lower side (the side closer to the base 11) of the two ends of the bonding line 30 or the bonding line 40 as the object and the vertex P3 and the vertex P4.

[0082] like Fig.10 In this way, the bonding wire 30 does not contact the bonding wire 40, but when the bonding wire 30 is tilted toward the bonding wire 40, the bonding wire 30 can contact the bonding wire 40. Thus, by detecting the electrical contact between the bonding wire 30 and the bonding wire 40, the tilt of the bonding wire 30 can be detected.

[0083] When the bonding wire 30 is tilted from the Z direction to the bonding wire 40 at an angle θ1, the bonding wire 30 can contact the bonding wire 40. The angle θ1 can be set to, for example, 45° or less, 30° or less, or 15° or less. When the angle θ1 increases, the high-frequency characteristics of the bonding wire 30 will change significantly. Therefore, the change in the high-frequency characteristics of the bonding wire 30 can be detected with high precision by reducing the angle θ1. When the angle θ1 is too small, even if the inclination of the bonding wire 30 is to the extent of manufacturing error, the bonding wire 30 will contact the bonding wire 40. From this point of view, the angle θ1 can be set to 5° or more.

[0084] The shortest distance between the bonding wire 30 and the bonding wire 40 is defined as distance D1. Figures 9 to 11 In the figure, the distance between the vertex P3 and the vertex P4 is assumed to be the shortest distance D1. By making the distance D1 smaller than the height H3, when the bonding wire 30 is inclined, the bonding wire 30 and the bonding wire 40 are easily in contact. The distance D1 can be set to be less than one times the height H3, less than 3 / 4 of the height H3, or less than 1 / 2 of the height H3.

[0085] In order to make the joining line 30 contact the joining line 40 when tilted, the joining line 40 is set to be asymmetric. When the length of the joining line 40 when viewed from the Z direction is set to D2, the position 1 / 3×D2 away from the end of the joining line 40 closer to the joining line 30 when viewed from the Z direction is set to Q3, the position 1 / 4×D2 away from the end is set to Q4, and the position 1 / 5×D2 away from the end is set to Q5. When viewed from the Z direction, the vertex P4 is located at a position closer to the joining line 30 than the position Q3. That is, when the joining line 40 is divided into three parts when viewed from the Z direction, the vertex P4 is located at the part closest to the joining line 30 among the divided parts. The vertex P4 can also be located at a position closer to the joining line 30 than the position Q4, and can also be located at a position closer to the joining line 30 than the position Q5. In this way, by setting the joining line 40 asymmetric, the shortest distance D1 can be reduced.

[0086] When the height H4 is too low, even if the bonding wire 30 is inclined, the bonding wire 30 does not contact the bonding wire 40. From this viewpoint, the height H4 can be set to be 0.5 times or more of the height H3, and can be set to be 0.8 times or more of the height H3.

[0087] Fig.12 : This is a top view of the bonding wire in Example 1. The angle formed by the extension direction of the bonding wire 30 and the extension direction of the bonding wire 40 when viewed from the Z direction is set to θ2. The angle θ2 may not be 90°. The extension direction of the bonding wire 30 and the extension direction of the bonding wire 40 may intersect. From the viewpoint of reducing the influence of the bonding wire 40 on the high-frequency characteristics of the bonding wire 30, the angle θ2 may be set to 45° or more, 60° or more, or 80° or more.

[0088] like Figure 8 Thus, at least two bonding wires 41 and 42 are provided with bonding wire 32 disposed therebetween. Thus, the inclination of bonding wire 32 can be detected regardless of whether bonding wire 32 is inclined in the positive (+) direction or the negative (-) direction in the Y direction.

[0089] Both ends of the bonding wires 41 to 44 are bonded to the base 11. Thus, the bonding wires 41 to 44 can be set to a reference potential. Thus, by detecting an electrical short circuit between the base 11 and the terminal 12 or the terminal 13, the inclination of the bonding wires 31 to 33 can be detected.

[0090] When the bonding wires 31 to 33 transmit high-frequency signals, the high-frequency characteristics of the bonding wires 31 to 33 change when the bonding wires 31 to 33 are tilted. Therefore, by providing the bonding wires 41 to 44 adjacent to the bonding wires 31 to 33, the change in the high-frequency characteristics of the bonding wires 31 to 33 can be detected.

[0091] When the high frequency characteristics of the bonding wire 32 electrically connecting the semiconductor chip 20 and the passive element chip 25 change, the characteristics of the matching circuit 18 cannot be adjusted from the outside of the semiconductor device 100. Therefore, it is important to detect the inclination of the bonding wire 32. Therefore, the bonding wire 41 and the bonding wire 42 adjacent to the bonding wire 32 are provided.

[0092] [Example 2]

[0093] Fig.13 It is a top view of the semiconductor device of Example 2. Fig.14 yes Fig.13 A-A section view. Fig.13 and Fig.14 As shown, in the semiconductor device 102 of the second embodiment, an electrode 27a and an electrode 27b are provided on the upper surface of the passive element chip 25. The bonding wire 34 electrically connects the electrode 27a and the electrode 27b. The bonding wire 32 electrically connects the electrode 22 and the electrode 27a. The bonding wire 33 electrically connects the electrode 27b and the terminal 13. The electrode 29 is provided on the substrate 26 in such a manner that the bonding wire 34 is arranged therebetween in the Y direction. The bonding wire 45 is bonded to the electrode 29. The via 29a penetrates the substrate 26, and electrically connects the electrode 28 and the electrode 29 to short-circuit them. Thus, the bonding wire 45 and the base 11 are at the same potential.

[0094] Fig.15 FIG. 1 is a circuit diagram of an integrated circuit of a semiconductor device of Embodiment 2. Fig.15As shown, the inductor L4 is connected in series between the inductor L2 and the inductor L3. The capacitor C1 is connected in shunt between the inductor L2 and the inductor L4. The capacitor C2 is connected in shunt between the inductor L4 and the inductor L3. The inductors L2 to L4, the capacitor C1 and the capacitor C2 form a matching circuit 18. The capacitor C1 and the capacitor C2 are provided in the passive element chip 25. The inductor L4 corresponds to the bonding wire 34 that electrically connects the electrode 27a and the electrode 27b. The capacitor C1 corresponds to the substrate 26 and the electrode 27a and the electrode 28 across the substrate 26. The capacitor C2 corresponds to the substrate 26 and the electrode 27b and the electrode 28 across the substrate 26. The other configurations are the same as those in the first embodiment, and the description thereof is omitted.

[0095] When both ends of the bonding wire 34 are bonded to one passive element chip 25 as in Example 2, it is difficult to provide a bonding wire adjacent to the bonding wire 34 on the base 11. Therefore, the first end of the bonding wire 45, which is closer to the bonding wire 34, is bonded to the passive element chip 25. Thus, the inclination of the bonding wire 34 can be detected.

[0096] [Example 3]

[0097] Fig.16 FIG. 1 is a top view of the semiconductor device of Example 3. Fig.16 As shown, in the semiconductor device 104 of the third embodiment, the semiconductor chip 20 and the passive element chip 25 are mounted on the base 11. The conductive layer 48 is provided on the base 11 in such a manner that an insulating layer is arranged therebetween. The terminal 12 and the terminal 13 are provided on the conductive layer 48 in such a manner that they are in electrical contact. The bonding wires 31 to 33 are connected in the same manner as in the first embodiment. The passive element chip 25a is provided on the base 11. The passive element chip 25a has a substrate 26 and an electrode 27. The electrode 27 and the conductive layer 48 are electrically connected by the bonding wire 35. The bonding wire 46 is provided on the base 11 in such a manner that the bonding wire 35 is arranged therebetween in the Y direction.

[0098] The bonding wire 35 and the passive component chip 25a form a VBW (Video Band Width) circuit 19. The VBW circuit 19 allows the signal with a frequency lower than the operating frequency band among the high-frequency signals flowing through the terminal 12 to pass to the ground and does not allow the signal of the operating frequency band to pass to the ground. Therefore, the passive component chip 25a has a large capacitance to allow the low-frequency signal to pass. The bonding wire 35 has a large inductance to prevent the high-frequency signal of the operating frequency band from passing. Therefore, the bonding wire 35 becomes longer and is easy to tilt when the resin is injected. Therefore, by setting the bonding wire 46 in a manner that the bonding wire 35 is arranged between them in the Y direction, the tilt of the bonding wire 35 can be detected. The other structures are the same as those in Example 1 and the description is omitted.

[0099] In Example 3, the bonding wire 35 is the longest among the bonding wires 31 to 33 that transmit signals and the bonding wire 35. In this case, a bonding wire 46 is provided adjacent to the bonding wire 35. Thus, the inclination of the bonding wire 35 can be detected.

[0100] The shortest bonding wire 31 among the bonding wires 31 to 33 and the bonding wires 35 for transmitting signals is not easily tilted. Thus, it is also possible not to provide a bonding wire adjacent to the bonding wire 31. In this way, the adjacent bonding wires 41 to 44 are not provided for at least one of the bonding wires 31 to 33 for transmitting signals other than the longest bonding wire 35. Thus, the miniaturization of the semiconductor device can be achieved.

[0101] In the first to third embodiments, an example of transmitting a high-frequency signal to the bonding wires 31 to 35 is described, but the bonding wires 31 to 35 may also transmit signals other than high-frequency signals, and may also be supplied with a reference potential. In the case where the bonding wires 31 to 35 transmit high-frequency signals, when the bonding wires 31 to 35 are inclined, the high-frequency signals of the bonding wires 31 to 35 are likely to change. Therefore, the bonding wires 41 to 46 are provided adjacent to the bonding wires 31 to 35 through which the high-frequency signals flow.

[0102] The embodiments disclosed herein are illustrative and non-restrictive in all aspects. The scope of the present disclosure is indicated by the claims rather than the above meanings, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: Pedestal; one or more chips, including a semiconductor chip disposed on the base; a first bonding wire connected to at least one chip among the one or more chips; a second bonding line extending in a direction intersecting with an extending direction of the first bonding line when viewed from the thickness direction of the base; as well as a resin layer, disposed on the base, for sealing the one or more chips, the first bonding wire and the second bonding wire; The first bonding line does not contact the second bonding line, and when the first bonding line is inclined toward the second bonding line, the first bonding line can contact the second bonding line.

2. The semiconductor device according to claim 1, comprising: a first terminal connected to the first bonding wire in a direct current manner; and a second terminal, connected to the second bonding wire in a direct current manner; The base is not DC-connected to the first terminal and the second terminal.

3. The semiconductor device according to claim 1 or 2, wherein: When the first bonding line is inclined by 45° or more from the thickness direction of the base toward the second bonding line, the first bonding line can contact the second bonding line.

4. The semiconductor device according to claim 1 or 2, wherein: When the second joining line is divided into three parts when viewed in the thickness direction of the base, the point on the second joining line farthest from the base is located in a portion closest to the first joining line among the divided parts.

5. The semiconductor device according to claim 1 or 2, wherein: When viewed in the thickness direction of the base, an angle formed by an extending direction of the first bonding wire and an extending direction of the second bonding wire is greater than or equal to 45°.

6. The semiconductor device according to claim 1 or 2, wherein: having a plurality of second bonding wires, At least two of the plurality of second bonding wires are provided so that the first bonding wire is arranged therebetween.

7. The semiconductor device according to claim 1 or 2, wherein: Two ends of the second bonding wire are bonded to the base.

8. The semiconductor device according to claim 1 or 2, wherein: Two ends of the first bonding wire are bonded to one of the one or more chips, A first end of the second bonding wire, which is close to the first bonding wire, is bonded to the one chip.

9. The semiconductor device according to claim 1 or 2, wherein: The first bonding wire is the longest among bonding wires that transmit signals in the semiconductor device.

10. The semiconductor device according to claim 1 or 2, wherein: The first bonding wire transmits a high frequency signal.

11. The semiconductor device according to claim 10, wherein The one or more chips include the semiconductor chip and the passive component chip, The first bonding wire electrically connects the semiconductor chip and the passive element chip.

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