Semiconductor structure and preparation method thereof
By setting the first chip, a sheet-shaped electrical connector and a second chip in the IMS module package structure, the effective packaging and functional output of a high-current and high-voltage power chip are achieved, and the problem that it is difficult for traditional packaging structures to lay out large chips in a limited space is solved.
Patent Information
- Application Number
- CN202311120337.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-31
- Publication Date
- 2025-02-28
AI Technical Summary
It is difficult for traditional IMS module packaging structure to arrange large current and high voltage power chips and devices in a limited package space, affecting the power and functional output of the product.
By providing a first chip, a sheet-shaped electrical connection and a second chip on the substrate, an electrical connection between the first chip and the substrate is realized, and the second chip is laminated on the first chip through the sheet-shaped electrical connection, and the packaging structure is optimized to adapt to the layout of a larger chip size.
The effective packaging of high-current and high-voltage power chips is realized in a limited package space, and it is easy to enclose more chips and devices, thereby improving functional output.
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Figure CN119542331A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] In the traditional IMS (aluminum substrate) module packaging structure, the field effect tube and the control chip are generally packaged together. The field effect tube and the control chip are arranged on the IMS in the same layer spacing. The field effect tube has three poles, namely the gate, source, and drain. The drain is connected to the IMS (aluminum substrate) through an adhesive, and the gate and source are connected to the corresponding pins of the IMS (aluminum substrate) by metal wires; the control chip is connected to the gate, and the signal end is connected to the IMS (aluminum substrate) by wire bonding, so as to achieve line conduction.
[0003] This type of packaging structure has a fixed product size. Therefore, high-current and high-voltage power chips and devices cannot be arranged within the limited packaging structure size (high-current and high-voltage power chips have a large area), which affects the power and functional output of the product. Summary of the invention
[0004] An embodiment of the present application provides a semiconductor structure, which includes:
[0005] The substrate has a first surface and a second surface which are opposite to each other, wherein the first surface is provided with a circuit and a chip welding area and a plurality of electrode welding areas connected to the circuit;
[0006] A first chip has a front side and a back side, wherein a first electrode and a second electrode are arranged on the front side of the first chip, a third electrode is arranged on the back side of the first chip, the back side of the first chip faces the substrate, and the third electrode is welded on a chip welding area;
[0007] At least two sheet-shaped electrical connectors, used to respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate;
[0008] The second chip has a front side and a back side. The front side of the second chip is provided with a plurality of electrodes, and the back side of the second chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors.
[0009] In some embodiments, the semiconductor structure further comprises:
[0010] The third chip has a front side and a back side, wherein a plurality of electrodes are arranged on the front side of the third chip, and the back side of the third chip faces the sheet-like electrical connector and is arranged on one of the sheet-like electrical connectors; wherein the third chip and the second chip are arranged on different sheet-like electrical connectors.
[0011] In some embodiments, the semiconductor structure also includes a plurality of leads, a portion of the plurality of leads being used to connect the electrodes on the front side of the second chip with the circuit on the first surface of the substrate, and another portion of the plurality of leads being used to connect the electrodes on the front side of the third chip with the circuit on the first surface of the substrate.
[0012] In some embodiments, the first surface is provided with a plurality of pin welding areas located on at least one side of the chip welding area, and the plurality of pin welding areas are connected to the circuit; the semiconductor structure also includes a plurality of outgoing pins; and the plurality of outgoing pins are respectively welded to the plurality of pin welding areas.
[0013] In some embodiments, the chip welding area, the plurality of electrode welding areas, the plurality of pin welding areas, and the first and second electrodes of the first chip are all provided with conductive solder, the first chip is soldered to the chip welding area by the conductive solder, the plurality of outgoing pins are respectively soldered to the plurality of pin welding areas by the conductive solder, at least one sheet-like electrical connector is soldered to the first electrode and the corresponding electrode welding area by the conductive solder, and at least one sheet-like electrical connector is soldered to the second electrode and the corresponding electrode welding area by the conductive solder;
[0014] The sheet-like electrical connector includes a first connecting portion extending laterally and used to connect the first pole or the third pole of the first chip, and a second connecting portion located on the side of the first chip and extending longitudinally; in the sheet-like electrical connector on which the second chip and the third chip are provided, an adhesive is provided on the first connecting portion of the sheet-like electrical connector, and the second chip and the third chip are respectively fixed on the sheet-like electrical connector by the adhesive; the adhesive is an insulating adhesive or a conductive adhesive.
[0015] In some embodiments, the semiconductor structure includes a plastic package, the plastic package covers the first chip, the second chip, the third chip, the at least two sheet-like electrical connectors and the exposed portion of the first surface of the substrate; and / or
[0016] The first chip is a MOS chip, the second chip is an IC chip, and the third chip is an MCU chip.
[0017] The present application also provides a method for preparing a semiconductor structure, which includes:
[0018] The first chip is arranged on the substrate; the substrate has a first surface and a second surface which are opposite to each other, the first surface is provided with a circuit and a chip welding area and a plurality of electrode welding areas connected to the circuit; the first chip has a front side and a back side, the front side of the first chip is provided with a first electrode and a second electrode, the back side of the first chip is provided with a third electrode, the back side of the first chip faces the substrate, and the third electrode is welded on the chip welding area;
[0019] At least two sheet-shaped electrical connectors are provided; the at least two sheet-shaped electrical connectors respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate;
[0020] A second chip is provided; the second chip has a front side and a back side, a plurality of electrodes are provided on the front side of the second chip, and the back side of the second chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors.
[0021] In some embodiments, the method for preparing the semiconductor structure further includes:
[0022] A third chip is provided; the third chip has a front side and a back side, a plurality of electrodes are provided on the front side of the third chip, and the back side of the third chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors; wherein the third chip and the second chip are provided on different sheet-like electrical connectors.
[0023] In some embodiments, before providing the second chip, the method includes:
[0024] A plurality of outgoing pins are provided; the first surface is provided with a plurality of pin welding areas located at least on one side of the chip welding area, and the plurality of pin welding areas are connected to the circuit; the plurality of outgoing pins are respectively welded to the plurality of pin welding areas;
[0025] Before placing the first chip on the substrate, the method includes: placing conductive solder on the chip welding area, a plurality of electrode welding areas and a plurality of pin welding areas;
[0026] After setting a plurality of outgoing pins, the method includes:
[0027] The conductive solder is reflow-cured.
[0028] In some embodiments, after providing at least two sheet-shaped electrical connectors, the method includes:
[0029] An adhesive is arranged on the first connection part of the sheet-shaped electrical connection member on which the second chip and the third chip are arranged; the sheet-shaped electrical connection member comprises a first connection part extending transversely and used to connect the first pole or the third pole of the first chip, and a second connection part located at the side of the first chip and extending longitudinally; the adhesive is an insulating adhesive or a conductive adhesive;
[0030] After the second chip and the third chip are provided, the method includes:
[0031] The adhesive is cured, and the second chip and the third chip are fixed on the sheet-like electrical connector respectively through the adhesive.
[0032] In some embodiments, after providing the second chip and the third chip, the method includes:
[0033] A plurality of leads are provided, a portion of the leads are used to connect the electrodes on the front side of the second chip with the circuit on the first surface of the substrate, and another portion of the leads are used to connect the electrodes on the front side of the third chip with the circuit on the first surface of the substrate.
[0034] In some embodiments, after providing the plurality of leads, the method includes:
[0035] A plastic package is formed; the plastic package covers the first chip, the second chip, the third chip, the at least two sheet-like electrical connectors and the exposed portion of the first surface of the substrate.
[0036] The main technical effects achieved by the embodiments of the present application are:
[0037] The semiconductor structure and manufacturing method provided in the embodiment of the present application, by placing the second chip on a sheet-like electrical connector used for electrical lead-out of the first chip so as to be stacked with the first chip, can arrange a larger chip size within a limited packaging space, thereby achieving effective packaging of high-current and high-voltage power chips; at the same time, due to the optimization of the packaging structure, it is convenient to encapsulate more chips and devices within a limited packaging space, thereby achieving more functional outputs. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;
[0039] Figure 2 is a cross-sectional view of another semiconductor structure provided by an exemplary embodiment of the present application;
[0040] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided by an exemplary embodiment of the present application;
[0041] Figures 4 to 10 It is a preparation process diagram of a method for preparing a semiconductor structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0042] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0043] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0044] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0045] The present application provides a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, a first chip, at least two sheet-like electrical connectors and a second chip. The substrate has a first surface and a second surface facing away from each other, the first surface is provided with a circuit and a chip welding area and a plurality of electrode welding areas connected to the circuit; the first chip has a front and a back, the front of the first chip is provided with a first pole and a second pole, the back of the first chip is provided with a third pole, the back of the first chip faces the substrate, and the third pole is welded on the chip welding area; at least two sheet-like electrical connectors are used to respectively connect the first pole and the second pole on the front of the first chip to different electrode welding areas on the substrate; the second chip has a front and a back, the front of the second chip is provided with a plurality of electrodes, and the back of the second chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors. The semiconductor structure, by arranging the second chip on the sheet-like electrical connector for electrical lead-out of the first chip, so as to be stacked with the first chip, can arrange a larger chip size in a limited packaging space, thereby realizing effective packaging of a high-current and high-voltage power chip; at the same time, due to the optimization of the packaging structure, it is convenient to enclose more chips and devices in a limited packaging space, thereby realizing more functional outputs.
[0046] The following is combined with Figures 1 to 10 , some embodiments of the present application are described in detail. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0047] Please refer to Figure 1 , and when necessary, combine Figure 2 As shown, the semiconductor structure 1000 includes a substrate 10 , a first chip 30 , at least two sheet-shaped electrical connectors 40 and a second chip 60 .
[0048] The substrate 10 has a first surface 101 and a second surface 102 which are opposite to each other. The first surface 101 is provided with a circuit and a chip bonding area 103 and a plurality of electrode bonding areas 104 connected to the circuit.
[0049] The first chip 30 has a front side 301 and a back side facing away from each other. The front side 301 of the first chip 30 is provided with a first pole and a second pole, the back side of the first chip 30 is provided with a third pole, the back side of the first chip 30 faces the substrate 10, and the third pole is welded on the chip welding area 103.
[0050] At least two sheet-shaped electrical connectors 40 are used to respectively connect the first electrode and the second electrode on the front side of the first chip 30 to different electrode welding areas 104 on the substrate 10 .
[0051] The second chip 60 has a front side 601 and a back side facing away from each other. The front side 601 of the second chip 60 is provided with a plurality of electrodes. The back side of the second chip 60 faces the sheet-like electrical connector 40 and is provided on one of the sheet-like electrical connectors 40 .
[0052] The substrate mentioned here may be a metal plate (IMS, Insulated Metal Substrate), such as an aluminum substrate.
[0053] The first chip 30 mentioned here can be a MOS chip, that is, a driving MOS transistor, and the second chip 60 can be an IC chip, that is, a driving chip. It can be understood that the size of the second chip 60 here is smaller than that of the first chip 30.
[0054] The first electrode mentioned here is a gate electrode, the second electrode mentioned here can be a source electrode, and the third electrode is a drain electrode, or vice versa.
[0055] It is understandable that passive components such as resistors, capacitors, inductors, etc. may also be disposed on the substrate 10 .
[0056] The sheet-like electrical connector 40 mentioned here can be a copper sheet. Figure 1 As shown, the sheet-like electrical connector 40 may include a first connecting portion 41 extending laterally and used to connect the first pole or the third pole of the first chip 30, and a second connecting portion 42 located at the side of the first chip 30 and extending longitudinally. The sheet-like electrical connector can lead the first pole and the second pole of the front side 301 of the first chip 30 to the circuit on the connection substrate 10.
[0057] The orthographic projection of the second chip 60 in the thickness direction T of the semiconductor structure 1000 is located within the orthographic projection range of the first connecting portion 41 in the thickness direction T. Here, the size of the second chip 60 is smaller than the size of the first connecting portion 41 in the sheet-like electrical connector 40. Figure 1 As shown, the distance D between the edge of the second chip 60 and the edge of the first connection portion 41 can be controlled to be greater than 0.1 mm to ensure that the sheet-like electrical connector 40 can support the second chip 60 .
[0058] Please continue to refer to Figure 1 As shown, the semiconductor structure 1000 further includes a third chip 70 .
[0059] The third chip 70 can be an MCU chip, that is, a control chip. The semiconductor structure 1000 stacks the second chip on the first chip and introduces the third chip. Compared with the implementation method in which the MCU chip is separately external and the IC chip and the MOS chip are integrated in a semiconductor structure with the same layer interval, the semiconductor structure 1000 introduces other chips or devices such as the MCU chip, which is conducive to realizing more functions while realizing the high current and high voltage power of the semiconductor structure. The third chip 70 is an MCU chip. The introduction of the third chip 70 in the semiconductor structure 1000 is conducive to further increasing the control function of the semiconductor structure, facilitating the optimization and design of the product structure, and facilitating the control of the product size.
[0060] The third chip 70 has a front side 701 and a back side, wherein a plurality of electrodes are arranged on the front side of the third chip 70, and the back side of the third chip 70 faces the sheet-like electrical connector 40 and is arranged on one of the sheet-like electrical connectors 40; wherein the third chip 70 and the second chip 60 are arranged on different sheet-like electrical connectors 40.
[0061] Similarly, the orthographic projection of the third chip 70 in the thickness direction T of the semiconductor structure 1000 is located within the orthographic projection range of the first connecting portion 41 in the thickness direction T. Here, the size of the third chip 70 is smaller than the size of the first connecting portion 41 in the sheet-like electrical connector 40. Figure 1 As shown, the distance between the edge of the third chip 70 and the edge of the first connecting portion 41 can also be controlled to be greater than 0.1 mm to ensure that the sheet-like electrical connector 40 can support the third chip 70 .
[0062] Of course, in some other embodiments, if the first connecting portion is relatively large, the second chip and the third chip may also be arranged on the same sheet-shaped electrical connecting member.
[0063] Please continue to refer to Figure 1 As shown, the semiconductor structure 1000 also includes a plurality of leads 90, a portion of the plurality of leads 90 is used to connect the electrode on the front side of the second chip 60 with the circuit on the first surface 101 of the substrate 10, and another portion of the plurality of leads 90 is used to connect the electrode on the front side of the third chip 70 with the circuit on the first surface 101 of the substrate 10.
[0064] In some embodiments, a portion of the lead 90 may be used to connect the electrode on the front side of the second chip 60 and the electrode on the front side of the third chip 70 .
[0065] The lead wire 90 can be a conductive wire such as an aluminum wire or a copper wire.
[0066] Please continue to refer to Figure 1As shown, the first surface 101 is provided with a plurality of pin welding areas 105 located at least on one side of the chip welding area 103, and the plurality of pin welding areas 105 are connected to the circuit. The semiconductor structure 1000 also includes a plurality of external pins 50. The plurality of external pins 50 are respectively welded to the plurality of pin welding areas 105.
[0067] Please continue to refer to Figure 1 As shown, conductive solder 20 is provided on the chip welding area 103, multiple electrode welding areas 104, multiple pin welding areas 105, and the first pole and the second pole of the first chip 30, the first chip 30 is soldered to the chip welding area 103 through the conductive solder 20, the multiple outgoing pins 50 are respectively soldered to the multiple pin welding areas 105 through the conductive solder 20, at least one sheet electrical connector 40 is soldered to the first pole and the corresponding electrode welding area 104 through the conductive solder 20, and at least one sheet electrical connector 40 is soldered to the second pole and the corresponding electrode welding area 104 through the conductive solder 20.
[0068] The conductive solder may be solder paste, or other solders, such as silver.
[0069] Please continue to refer to Figure 1 As shown, in the sheet-like electrical connector 40 provided with the second chip 60 and the third chip 70, an adhesive 80 is provided on the first connection portion 41 of the sheet-like electrical connector 40, and the second chip 60 and the third chip 70 are respectively fixed on the sheet-like electrical connector 40 by the adhesive 80. The adhesive 80 is an insulating adhesive or a conductive adhesive.
[0070] The adhesive 80 is preferably insulating adhesive, such as insulating adhesive EN-4900GCN3.
[0071] Please continue to refer to Figure 1 As shown, the semiconductor structure 1000 includes a plastic package 110, which covers the first chip 30, the second chip 60, the third chip 70, the at least two sheet-like electrical connectors 40 and the exposed portion of the first surface 101 of the substrate 10.
[0072] It is understandable that the plastic package 110 also covers the lead 90 and the portion of the external pin 50. The external end of the external pin 50 can be exposed from the plastic package 110 to be electrically connected to an external structure.
[0073] It should be noted that the third chip 70 is an MCU chip, the second chip 60 is an IC chip, and the first chip 30 is a MOS chip. When the semiconductor structure 1000 is working, the MCU chip will provide a control signal to the IC chip, and the IC chip will drive the MOS chip to perform corresponding work after receiving the control signal.
[0074] It should be noted that in some other embodiments, the semiconductor structure may not include a third chip, that is, an MCU chip. Figure 2 As shown, the semiconductor structure 2000 does not include a third chip, that is, does not include an MCU chip. Accordingly, when the semiconductor structure 2000 is working, it can cooperate with the MCU structure that is separately externally placed outside the semiconductor structure 2000. That is, the second chip 60 is an IC chip, and the first chip 30 is a MOS chip. When the semiconductor structure 2000 is working, the MCU structure that is separately externally placed outside the semiconductor structure 2000 will provide a control signal to the IC chip, and the IC chip will drive the MOS chip to perform corresponding work after receiving the control signal.
[0075] It should be noted that the external pins 50 of the semiconductor structure 1000 and the semiconductor structure 2000 may be further bent, for example, bent toward the lower surface in the figure, so as to facilitate subsequent connection with other structures.
[0076] In addition, it should be noted that the semiconductor structure 1000 or 2000 can be a power device, which can be applied to a drive switch as a module structure of a drive switch. For example, it can be applied to air conditioners, washing machines or other electrical structures. Taking the application in air conditioners as an example, it can be applied to control or drive at least one of the functions of air conditioners such as cooling, heating, and frequency conversion. The difference is that the semiconductor structure 1000 is integrated with an MCU chip (that is, a control chip), while the semiconductor structure 2000 is not integrated with an MCU chip, and needs to work with a separate MCU chip or MCU structure.
[0077] The present application further provides a semiconductor intermediate structure, which may include a plurality of semiconductor structures 1000 or 2000 or similar semiconductor structures as described above. The plurality of semiconductor structures may be arranged in an array.
[0078] Please refer to Figure 3 As shown, the present application further provides a method for preparing a semiconductor structure, which includes the following steps S101 to S105:
[0079] In step S101, a first chip is arranged on a substrate; the substrate has a first surface and a second surface facing away from each other, the first surface is provided with a circuit and a chip welding area connected to the circuit and a plurality of electrode welding areas; the first chip has a front side and a back side, the front side of the first chip is provided with a first pole and a second pole, the back side of the first chip is provided with a third pole, the back side of the first chip faces the substrate, and the third pole is welded on the chip welding area.
[0080] In step S103, at least two sheet-shaped electrical connectors are provided; the at least two sheet-shaped electrical connectors respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate.
[0081] In step S105, a second chip is provided; the second chip has a front side and a back side, a plurality of electrodes are provided on the front side of the second chip, and the back side of the second chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors.
[0082] Combine the following Figures 4 to 10 As shown, taking the preparation of the semiconductor structure 1000 as an example, the preparation method of the semiconductor structure is described in detail.
[0083] Please combine Figure 4 As shown, in the method for preparing the semiconductor structure, first, a substrate 10 is provided. The substrate 10 has a first surface 101 and a second surface 102 which are separated from each other, and the first surface 101 is provided with a circuit and a chip welding area 103 and a plurality of electrode welding areas 104 connected to the circuit.
[0084] The substrate mentioned here may be a metal plate (IMS, Insulated Metal Substrate), such as an aluminum substrate.
[0085] Please combine Figure 4 As shown, before the first chip 30 is placed on the substrate 10 in step S101, the method includes the following step S102:
[0086] In step S102 , conductive solder 20 is provided on the chip pad 103 , the plurality of electrode pads 104 , and the plurality of lead pads 105 .
[0087] The conductive solder 20 can be solder paste, silver, etc. Figure 5 As shown, in step S101, a first chip 30 is disposed on a substrate 10. The first chip 30 has a front side and a back side, a first electrode and a second electrode are disposed on the front side of the first chip 30, a third electrode is disposed on the back side of the first chip 30, the back side of the first chip 30 faces the substrate 10, and the third electrode is welded on the chip welding area 103.
[0088] The first chip 30 mentioned here may be a MOS chip. It is understandable that passive components such as resistors, capacitors, inductors, etc. may also be arranged on the substrate 10.
[0089] The first electrode mentioned here is a gate electrode, the second electrode mentioned here can be a source electrode, and the third electrode is a drain electrode, or vice versa.
[0090] Please combine Figure 6 As shown, in step S103, at least two sheet-shaped electrical connectors 40 are provided. The at least two sheet-shaped electrical connectors 40 respectively connect the first electrode and the second electrode on the front side of the first chip 30 to different electrode welding areas 104 on the substrate 10.
[0091] The sheet-like electrical connector 40 mentioned here can be a copper sheet. Figure 1 As shown, the sheet-like electrical connector 40 may include a first connecting portion 41 extending laterally and used to connect the first pole or the third pole of the first chip 30, and a second connecting portion 42 located at the side of the first chip 30 and extending longitudinally. The sheet-like electrical connector can lead the first pole and the second pole of the front side 301 of the first chip 30 to the circuit on the connection substrate 10.
[0092] Please combine Figure 7 As shown, before setting the second chip 60 in step S105, the method further includes the following step S104:
[0093] In step S104 , a plurality of outgoing pins 50 are provided; the first surface 101 is provided with a plurality of pin welding areas 105 located at least on one side of the chip welding area 103 , and the plurality of pin welding areas 105 are connected to the circuit; and the plurality of outgoing pins 50 are respectively welded to the plurality of pin welding areas 105 .
[0094] The output pin 50 is provided to facilitate electrical extraction and electrical signal input within the semiconductor structure 1000 .
[0095] It should be noted that after setting a plurality of outgoing pins 50 in step S104, the method includes the following step S106:
[0096] In step S106 , the conductive solder 20 is reflow-cured.
[0097] Taking the conductive solder as solder paste as an example, the solder paste can be solidified by reflow heating to achieve a fixed connection of the corresponding structure.
[0098] Please combine Figure 8As shown, in step S105 , a second chip 60 is provided. The second chip 60 has a front side and a back side. The front side of the second chip 60 is provided with a plurality of electrodes. The back side of the second chip 60 faces the sheet-like electrical connector 40 and is provided on one of the sheet-like electrical connectors 40 .
[0099] The second chip 60 may be an IC chip.
[0100] Please continue to combine Figure 8 As shown, the method for preparing the semiconductor structure 1000 further includes the following step S107:
[0101] In step S107, a third chip 70 is set; the third chip 70 has a front side and a back side, the front side of the third chip 70 is provided with a plurality of electrodes, and the back side of the third chip 70 faces the sheet-like electrical connector 40 and is arranged on one of the sheet-like electrical connectors 40; wherein the third chip 70 and the second chip 60 are arranged on different sheet-like electrical connectors 40.
[0102] The order of step S107 and step S105 is not limited.
[0103] It should be noted that after at least two sheet-shaped electrical connectors 40 are provided in step S103 and before the second chip and the third chip are provided in step S105, the method further includes the following step S108:
[0104] In step S108, an adhesive 80 is provided on the first connection portion 41 of the sheet-like electrical connector 40 on which the second chip 60 and the third chip 70 are provided; the sheet-like electrical connector 40 includes a first connection portion 41 extending laterally and used to connect the first pole or the third pole of the first chip 30, and a second connection portion 42 located on the side of the first chip 30 and extending longitudinally; the adhesive 80 is an insulating adhesive or a conductive adhesive.
[0105] The adhesive 80 is preferably insulating adhesive, such as insulating adhesive EN-4900GCN3.
[0106] Accordingly, after the second chip 60 is set in step S105 and the third chip 70 is set in step S107, the method includes the following step S109:
[0107] In step S109 , the adhesive 80 is cured, and the second chip 60 and the third chip 70 are fixed on the sheet-shaped electrical connector 40 respectively by the adhesive 80 .
[0108] The adhesive 80 may be cured by heating.
[0109] Please combine Fig. 9As shown, after the second chip 60 and the third chip 70 are set in step S105 and step S107, the method includes the following step S110:
[0110] In step S110, a plurality of leads 90 are provided, a portion of the plurality of leads 90 is used to connect the electrode on the front side of the second chip 60 with the circuit on the first surface 101 of the substrate 10, and another portion of the plurality of leads 90 is used to connect the electrode on the front side of the third chip 70 with the circuit on the first surface 101 of the substrate 10.
[0111] It is understandable that, in some embodiments, part of the leads 90 may be used to connect the electrodes on the front side of the second chip 60 and the electrodes on the front side of the third chip 70 .
[0112] Please combine Fig.10 As shown, after setting a plurality of leads 90 in step S110, the method includes the following step S111:
[0113] In step S111 , a plastic package 110 is formed; the plastic package 110 covers the first chip 30 , the second chip 60 , the third chip 70 , the at least two sheet-like electrical connectors 40 and the exposed portion of the first surface 101 of the substrate 10 .
[0114] Furthermore, after the plastic package 110 is formed, a semiconductor intermediate structure may be formed, wherein the semiconductor intermediate structure includes a plurality of semiconductor structural units. The plurality of semiconductor structural units may be similar to Fig.10 In the structure shown, the substrates 10 of different semiconductor structure units can be connected into a continuous structure.
[0115] Accordingly, after forming the semiconductor intermediate structure, the method includes the following step S112:
[0116] In step S112, the semiconductor intermediate structure is cut into pieces to form semiconductor structures.
[0117] Please refer to Fig.10 As shown, when the semiconductor intermediate structure is cut, the following Fig.10 A semiconductor structure 1000 is shown.
[0118] It should be noted that in the formation of Fig.10 After the semiconductor structure 1000 is shown, the method may further include bending the external pin 50, such as bending it toward the lower surface side in the figure, so as to facilitate subsequent connection with other structures.
[0119] The semiconductor structure 2000 may be manufactured by referring to the above corresponding manufacturing method steps.
[0120] The embodiment of the method for manufacturing a semiconductor structure provided in the embodiment of the present application and the embodiment of the semiconductor structure belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, which will not be repeated here.
[0121] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.
[0122] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0123] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A semiconductor structure, characterized in that: include: The substrate has a first surface and a second surface which are opposite to each other, wherein the first surface is provided with a circuit and a chip welding area and a plurality of electrode welding areas connected to the circuit; A first chip has a front side and a back side, wherein a first electrode and a second electrode are arranged on the front side of the first chip, a third electrode is arranged on the back side of the first chip, the back side of the first chip faces the substrate, and the third electrode is welded on a chip welding area; At least two sheet-shaped electrical connectors, used to respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate; The second chip has a front side and a back side. The front side of the second chip is provided with a plurality of electrodes, and the back side of the second chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors.
2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: The third chip has a front side and a back side, wherein a plurality of electrodes are arranged on the front side of the third chip, and the back side of the third chip faces the sheet-like electrical connector and is arranged on one of the sheet-like electrical connectors; wherein the third chip and the second chip are arranged on different sheet-like electrical connectors.
3. The semiconductor structure according to claim 2, wherein: The semiconductor structure also includes a plurality of leads, a portion of the leads being used to connect the electrodes on the front side of the second chip with the circuit on the first surface of the substrate, and another portion of the leads being used to connect the electrodes on the front side of the third chip with the circuit on the first surface of the substrate.
4. The semiconductor structure according to claim 2, characterized in that The first surface is provided with a plurality of pin welding areas located at least on one side of the chip welding area, and the plurality of pin welding areas are connected to the circuit; the semiconductor structure also includes a plurality of outgoing pins; the plurality of outgoing pins are respectively welded to the plurality of pin welding areas.
5. The semiconductor structure according to claim 4, characterized in that Conductive solder is disposed on the chip welding area, the plurality of electrode welding areas, the plurality of pin welding areas, and the first and second poles of the first chip, the first chip is soldered to the chip welding area by the conductive solder, the plurality of outgoing pins are respectively soldered to the plurality of pin welding areas by the conductive solder, at least one sheet-shaped electrical connector is soldered to the first pole and the corresponding electrode welding area by the conductive solder, and at least one sheet-shaped electrical connector is soldered to the second pole and the corresponding electrode welding area by the conductive solder; The sheet-like electrical connector includes a first connecting portion extending laterally and used to connect the first pole or the third pole of the first chip, and a second connecting portion located on the side of the first chip and extending longitudinally; in the sheet-like electrical connector on which the second chip and the third chip are provided, an adhesive is provided on the first connecting portion of the sheet-like electrical connector, and the second chip and the third chip are respectively fixed on the sheet-like electrical connector by the adhesive; the adhesive is an insulating adhesive or a conductive adhesive.
6. The semiconductor structure according to any one of claims 2 to 5, characterized in that: The semiconductor structure includes a plastic package, which covers the first chip, the second chip, the third chip, the at least two sheet-shaped electrical connectors and the exposed portion of the first surface of the substrate; and / or The first chip is a MOS chip, the second chip is an IC chip, and the third chip is an MCU chip.
7. A method for preparing a semiconductor structure, characterized in that: include: The first chip is arranged on the substrate; the substrate has a first surface and a second surface which are opposite to each other, the first surface is provided with a circuit and a chip welding area and a plurality of electrode welding areas connected to the circuit; the first chip has a front side and a back side, the front side of the first chip is provided with a first electrode and a second electrode, the back side of the first chip is provided with a third electrode, the back side of the first chip faces the substrate, and the third electrode is welded on the chip welding area; At least two sheet-shaped electrical connectors are provided; the at least two sheet-shaped electrical connectors respectively connect the first electrode and the second electrode on the front side of the first chip to different electrode welding areas on the substrate; A second chip is provided; the second chip has a front side and a back side, a plurality of electrodes are provided on the front side of the second chip, and the back side of the second chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The method for preparing the semiconductor structure further comprises: A third chip is provided; the third chip has a front side and a back side, a plurality of electrodes are provided on the front side of the third chip, and the back side of the third chip faces the sheet-like electrical connector and is provided on one of the sheet-like electrical connectors; wherein the third chip and the second chip are provided on different sheet-like electrical connectors.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that: Before providing the second chip, the method includes: A plurality of outgoing pins are provided; the first surface is provided with a plurality of pin welding areas located at least on one side of the chip welding area, and the plurality of pin welding areas are connected to the circuit; the plurality of outgoing pins are respectively welded to the plurality of pin welding areas; Before placing the first chip on the substrate, the method includes: placing conductive solder on the chip welding area, a plurality of electrode welding areas and a plurality of pin welding areas; After setting a plurality of outgoing pins, the method includes: The conductive solder is reflow-cured.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that: After providing at least two sheet-shaped electrical connectors, the method comprises: An adhesive is arranged on the first connection part of the sheet-shaped electrical connection member on which the second chip and the third chip are arranged; the sheet-shaped electrical connection member comprises a first connection part extending transversely and used to connect the first pole or the third pole of the first chip, and a second connection part located at the side of the first chip and extending longitudinally; the adhesive is an insulating adhesive or a conductive adhesive; After the second chip and the third chip are provided, the method includes: The adhesive is cured, and the second chip and the third chip are fixed on the sheet-like electrical connector respectively through the adhesive.
11. The method for preparing a semiconductor structure according to claim 10, characterized in that: After the second chip and the third chip are provided, the method includes: A plurality of leads are provided, a portion of the leads are used to connect the electrodes on the front side of the second chip with the circuit on the first surface of the substrate, and another portion of the leads are used to connect the electrodes on the front side of the third chip with the circuit on the first surface of the substrate.
12. The method for preparing a semiconductor structure as claimed in claim 11, characterized in that: After providing a plurality of leads, the method includes: A plastic package is formed; the plastic package covers the first chip, the second chip, the third chip, the at least two sheet-like electrical connectors and the exposed portion of the first surface of the substrate.