Voltage resonance peak suppression circuit and method for high-frequency link single-phase isolation inverter

Abstract

The invention belongs to the technical field of inverters, and particularly relates to a high-frequency link single-phase isolation inverter voltage resonance peak suppression circuit, and the core function of a full-bridge active clamping circuit is to effectively eliminate the voltage resonance peak at the secondary side output end of a transformer and ensure the safety and reliability of the commutation process of a cycloconverter; because the potential at the two ends of the clamping capacitor is the same as the potential at the output end of the secondary side of the isolation transformer, the clamping switch tube can realize zero-voltage switching; a safe and reliable commutation path is provided for filtering inductive current by adopting a unipolar frequency doubling phase shift modulation strategy; the power switch tube of the cycloconverter is switched on and switched off in the time period when the voltage of the output end of the secondary side of the transformer is zero, so that the power switch tube of the cycloconverter can be switched on and switched off under the condition of no voltage stress, namely, zero-voltage switching is realized, the energy loss of the power switch tube in the switching process is remarkably reduced, and the service life of the cycloconverter is prolonged. And the overall operation efficiency and performance of the high-frequency link single-phase isolation inverter are improved.

Description

Technical Field

[0001] The present application belongs to the technical field of inverters, and in particular relates to a voltage resonance spike suppression circuit and method for a high-frequency link single-phase isolated inverter. Background Art

[0002] With the rapid development of DC-AC inverters, the requirements for power density, size and weight are becoming more and more stringent, which has promoted the progress of high-frequency isolation inverters. Compared with traditional DC-HFAC-DC-AC inverters, DC-HFAC-AC inverters have fewer conversion stages, so they are more efficient and smaller in size. However, there are obvious resonant voltage spikes at the output end of the secondary side of the transformer of the DC-HFAC-AC inverter, which greatly increases the risk of switch breakdown. In addition, how to achieve safe commutation of the cycloconverter and its peripheral circuits is also a key technical issue that hinders the development of high-frequency isolation inverters. Summary of the invention

[0003] Based on the current technical problems, the present invention provides a method for suppressing voltage resonance spikes of a high-frequency link single-phase isolated inverter, which can significantly suppress the output voltage resonance spikes of the transformer secondary side and realize safe commutation of the cycloconverter and its peripheral circuits. The technical solution is as follows:

[0004] A high-frequency link single-phase isolated inverter voltage resonance spike suppression circuit, comprising a single-phase full-bridge inverter, a full-wave cycloconverter, a full-bridge active clamping circuit, an LC filter circuit and a load resistor;

[0005] The single-phase full-bridge inverter includes a DC power supply V DC , DC bus capacitor C DC , transistors Q1, Q2, Q3, Q4, and their anti-parallel diodes D1, D2, D3, D4 and output capacitors C1, C2, C3, C4;

[0006] The full-wave cycloconverter comprises transistors Q5, Q6, Q7, Q8 and anti-parallel diodes D5, D6, D7, D8; the series branch of transistors Q5 and Q6 is connected in parallel with the series branch of transistors Q7 and Q8;

[0007] The full-bridge active clamp circuit includes a transistor Q n1 , Q n2 , Q n3 , Q n4 , anti-parallel diode D n1 , D n2 , D n3 , D n4 , output capacitor C n1 , C n2 , C n3 , Cn4 And the clamping capacitor C n5 ; Transistor Q n1 , Q n2 The series branch and Q n3 , Q n4 The series branches are connected in parallel;

[0008] The LC filter circuit includes a filter inductor L F And filter capacitor C F ;

[0009] The collector of transistor Q5 is respectively connected to Q n1 The emitter, Q n2 The collector of transistor Q7 is connected to Q n3 The emitter, Q n4 The collector of the transistor Q6 is connected to the collector of Q8 and the L of the filter circuit F connect;

[0010] The transistor Q n1 The collector and Q n3 The collector connection of transistor Q n1 The emitter and Q n2 The collector connection of transistor Q n2 The emitter and Q n4 The emitter connection of transistor Q n3 The emitter and Q n4 The collector connection of transistor Q n1 and Q n3 The collector and clamp capacitor C n5 The positive input terminal of transistor Q n2 and Q n4 The emitter and clamping capacitor C n5 The negative input terminal is connected;

[0011] The primary leakage inductance of the transformer is L K1 , the transformer secondary leakage inductance is L K2 The C end of the secondary winding N2 is connected to the collector of transistor Q5, Q n1 The emitter and Q n2 The collector of the isolation transformer's secondary winding N3 is connected to the collector of transistor Q7, Q n3 The emitter, Q n4 The collector of the common terminal D is connected to the filter capacitor C F and load resistance R L .

[0012] Preferably, when the output terminal of the secondary side of the isolation transformer is in a positive or negative level state, the full-bridge clamp circuit passes Cn5 The voltage resonance spike at the secondary output end of the isolation transformer is eliminated. Since the potential at both ends of the clamping capacitor is the same as the potential at the secondary output end of the isolation transformer, the clamping switch tube can achieve zero voltage switching; when the cycloconverter is commutating, a commutation path is provided for the filter inductor current; the cycloconverter includes transistors Q5, Q6, Q7, and Q8, and the turn-on and turn-off of the transistors Q5, Q6, Q7, and Q8 all occur during the period when the voltage at the secondary output end of the transformer is zero, so Q5, Q6, Q7, and Q8 can be turned on and off without voltage stress, that is, zero voltage switching is achieved.

[0013] A method for suppressing voltage resonance spikes in a high-frequency link single-phase isolated inverter adopts a unipolar frequency-doubling phase-shift modulation strategy. A complete switching cycle includes two carrier cycles. When the modulation wave u g When >0, the working mode of the previous carrier cycle is as follows, with a total of eight modes:

[0014] The capacitance of the power switch output capacitors C1 to C4 is C oss ,i A (t0) is the initial value of the primary current, L K1 is the primary leakage inductance of the transformer, L K2 is the secondary leakage inductance of the transformer, U AB is the voltage difference between the emitter of primary transistor Q1 and the collector of Q4, U EF is the voltage difference between the collector of transistor Q7 and the collector of Q8, U C2 is the voltage across the parasitic capacitor C2 of the transistor Q2, the transformation ratio of the transformer is N=N2 / N1=N3 / N1, where N1 represents the number of turns of the primary winding of the transformer, N2 represents the number of turns of one of the windings on the secondary side of the transformer, and N3 represents the number of turns of the other winding on the secondary side of the transformer.

[0015] Mode 1, t0~t1: For the primary side of the transformer, due to U Q3 Before t0, it is 0, so Q3 is turned off at zero voltage at t0. During this period, C3 is charged, C4 is discharged, and U AB =U Q3 ,i A <0; For the secondary side of the transformer, the output terminals C and E pass through the clamping circuit Q n4 -D n2 Connect, U Qn2 =0; Q5-D6 and Q n4 -D n2 These two paths provide paths for leakage inductor current and filter inductor current;

[0016] Mode 2, t1~t2: For the primary side of the transformer, at t1, C3 and C4 complete charging and discharging respectively, and D4 is naturally turned on; during this period, the primary side current iA Energy is fed back to the DC power supply through the anti-parallel diode D1-D4 path, i A <0, and decays rapidly; at t2, i A =0, Q4 can achieve zero voltage conduction; for the secondary side of the transformer, Q n2 It needs to be turned off before Q4 is turned on to avoid short circuit caused by sudden voltage on the secondary winding of the transformer;

[0017] Mode 3, t2~t3; for the primary side of the transformer, Q1 and Q4 are turned on, i A The direction of the change, i A >0; at t3, i A (t3) = Ni LF ; For the secondary side of the transformer, before t3, due to the primary current i A Less than the current Ni converted from the secondary filter inductor current to the primary side LF , i.e. i A <Ni LF , winding N3 passes through Q n4 -D n2 for i LF Provide a path for electric current;

[0018] Mode 4, t3-t4: At time t3, i C =i LF =i A / N,U CD =NU AB =NV DC During this period, Q n1 conduction; due to Q n1 The potential at both ends is 2NV DC , so Q n1 Zero voltage conduction; clamping capacitor C n5 By Q n1 and Q n4 Clamp the secondary voltage to 2NV DC ; Due to U Cn1 =0,Q n1 It can be turned off at zero voltage before time t4;

[0019] Mode 5, t4~t5: Due to U C1 =0, Q1 can be turned off at zero voltage at t4; during this period, C1 is charged, C2 is discharged, and U AB Gradually decrease, U AB =U EF =U C2 , L F , L K1 and L K2 Still equivalent series connection, iA =Ni LF ;

[0020] Mode 6, t5-t6: For the primary side of the transformer, at t5, C1 completes charging, C2 completes discharging, and U AB =U CE =U C2 =0,U C1 =V DC , D2 is naturally turned on; during this period, Q2 can achieve zero voltage conduction, i A Gradually decrease, i A >0; For the secondary side of the transformer, since winding N2 cannot support i LF , winding N3 passes through Q n4 -D n2 Provides a commutation path for leakage inductance current and filter inductance current; during this period, U Cn2 =0,Q n2 Can achieve zero voltage conduction;

[0021] Mode 7, t6~t7: For the primary side of the transformer, i A Continues to decrease, and i A >0; For the secondary side of the transformer, Q7 and Q8 are turned on at t6; due to U CE =0, Q7 and Q8 can achieve zero voltage conduction; during this period, Q5-D6, Q7-D8 and Q n4 -D n2 -Q5-D6 is i LF Providing a commutation path;

[0022] Mode 8, t7-t8: Due to U CE =0, Q5 and Q6 can achieve zero voltage shutdown at t7, Q n4 Zero voltage shutdown can be achieved before t8; winding N2 passes Q n2 -D n4 Continue for i LF A commutation path is provided; during this period, since there is no sudden current change in winding N2, voltage overshoot caused by commutation of the cycloconverter is avoided.

[0023] Preferably, in the modulation wave u g >0, in the next carrier cycle, the full-bridge active clamp circuit passes Q n3 The clamping capacitor C n5 Connect to the C and E terminals of the secondary side of the transformer to eliminate the voltage resonance spike. In this process, due to Q n3 The potentials at both ends are the same, so Q n3 Zero voltage switching can be achieved.

[0024] Preferably, in mode 2, the dead time T of Q3 and Q4 dead2 The conditions are:

[0025]

[0026] V DC is the power supply voltage.

[0027] Preferably, Q n2 Zero voltage turn-off time T delay1 The conditions are:

[0028]

[0029] Preferably, in mode 4, Q n1 The zero voltage on-time condition is:

[0030]

[0031] Preferably, in mode 6, the dead time of Q1 and Q2 satisfies the following condition:

[0032]

[0033] Preferably, Q n2 The zero voltage on-time condition is:

[0034]

[0035] Preferably, transistors Q5 and Q6, Q7 and Q8 are driven by the same PWM signal respectively. n1 , Q n2 With Q n3 , Q n4 Has the same conduction logic; when the modulation wave u g >0, the power switch tubes Q1 and Q2 located in the leading bridge arm are easier to achieve zero voltage switching, while the power switch tubes Q3 and Q4 located in the trailing bridge arm are more difficult to achieve zero voltage switching.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] Compared with the high-frequency isolation inverter without active clamping circuit, the present invention adds a full-bridge active clamping circuit on the secondary side of the transformer, which effectively eliminates the voltage resonance peak at the output end of the secondary side of the transformer. Since the potential across the clamping capacitor is the same as the potential at the output end of the secondary side of the isolation transformer, the clamping switch tube can achieve zero voltage switching, while ensuring the safety and reliability of the commutation process of the cyclotron converter; a unipolar frequency-doubling phase-shift modulation strategy is adopted to provide a safe and reliable commutation path for the filter inductor current; the power switch tube of the cyclotron converter is turned on and off during the period when the voltage at the output end of the secondary side of the transformer is zero, so that the power switch tube of the cyclotron converter can be turned on and off without voltage stress, that is, zero voltage switching is achieved, thereby significantly reducing the energy loss of the power switch tube during the switching process, and improving the overall operating efficiency and performance of the high-frequency link single-phase isolation inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The circuit diagram of the high-frequency link single-phase isolated full-wave inverter containing a full-bridge active clamping circuit of the present invention;

[0039] Figure 2 It is a unipolar frequency-doubled SPWM modulation signal diagram;

[0040] Figure 3 for u g >0: the action state of the clamp circuit in the previous carrier cycle;

[0041] Figure 4 for u g >0: the clamp circuit is in the action state after one carrier cycle;

[0042] Figure 5(a) shows the voltage u at the output terminal of the transformer secondary side when no clamping circuit is added CE and current i C ;

[0043] FIG5(b) is a diagram showing the voltage u of the secondary output terminal of the transformer after adding the full-bridge active clamping circuit of the present invention. CE and current i C ;

[0044] Figure 6 The output voltage THD analysis after adding the full-bridge active clamping circuit of the present invention;

[0045] Figure 7(a) shows the gate-source voltage u of Q1 after adding the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned on;

[0046] Figure 7(b) shows the gate-source voltage u of Q1 after adding the full-bridge active clamp circuit. GS and the drain-source voltage uDS The waveform when the switch is turned off;

[0047] Figure 8(a) shows the gate-source voltage u of Q3 after adding the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned on;

[0048] Figure 8(b) shows the gate-source voltage u of Q3 after adding the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned off;

[0049] Figure 9(a) shows the Q after adding the full-bridge active clamp circuit. n1 The gate-source voltage u GS and the drain-source voltage u DS The waveform when the switch is turned on;

[0050] Figure 9(b) shows the Q after adding the full-bridge active clamp circuit. n1 The gate-source voltage u GS and the drain-source voltage u DS The waveform when the switch is turned off;

[0051] Figure 10(a) shows the gate-source voltage u of Q5 after adding the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned on;

[0052] Figure 10(b) shows the gate-source voltage u of Q5 added to the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned off;

[0053] Figure 11(a) shows the gate-source voltage u of Q7 after adding the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned on;

[0054] Figure 11(b) shows the gate-source voltage u of Q7 added to the full-bridge active clamp circuit. GS and the drain-source voltage u DS The waveform when the switch is turned off. DETAILED DESCRIPTION

[0055] The detailed description of the following embodiments is supplemented by the drawings selected from the experimental process of the present invention, which is intended to provide a more in-depth explanation of the core concept of the present invention. Those skilled in the art should be able to understand all technical and scientific terms involved in the text without obstacles. It should be emphasized that the terms used herein are purely for the purpose of illustrating specific examples and are by no means intended to limit the broad scope of the exemplary embodiments of the present invention.

[0056] The detailed description of the following embodiments is supplemented by the drawings selected from the experimental process of the present invention, which is intended to provide a more in-depth explanation of the core concept of the present invention. Those skilled in the art should be able to understand all technical and scientific terms involved in the text without obstacles. It should be emphasized that the terms used herein are purely for the purpose of illustrating specific examples and are by no means intended to limit the broad scope of the exemplary embodiments of the present invention.

[0057] The present invention provides a method for suppressing the resonant voltage of a high-frequency link single-phase isolated inverter, wherein the circuit is composed of a single-phase full-bridge (H-bridge) inverter, a cycloconverter, a full-bridge active clamping circuit, a filter circuit and a resistive load. Figure 1 shown. Figure 2 The circuit parameters in are: L F =1.2mH, C F =14.1uF, R L =25Ω, L K1 =3.5uH, transformer turns ratio N = 3, Q1-Q8, Q n1 , Q n2 , Q n3 , Q n4 Insulated gate bipolar transistor (MOSFET), D1-D8, D n1 , D n2 , D n3 , D n4 For the anti-parallel diode of the power switch tube, C1~C4, C n1 ~C n4 is the output capacitance of the power switch tube.

[0058] The full-bridge active clamp circuit consists of four insulated gate bipolar transistors (MOSFET) Q n1 ~Q n4 , anti-parallel diode D n1 ~D n4 , output capacitor C n1 ~C n4 And the clamping capacitor C n5 When the output terminal of the secondary side of the isolation transformer is in a positive or negative level state, the full-bridge clamp circuit passes through C n5Eliminate the voltage resonance spike at the secondary output end of the isolation transformer. Since the potential across the clamping capacitor is the same as the potential at the secondary output end of the isolation transformer, the clamping switch tube can achieve zero voltage switching; when the cycloconverter is commutating, it provides a safe and reliable commutation path for the filter inductor current.

[0059] The cycloconverter consists of four insulated gate bipolar transistors (MOSFET) Q5~Q8 and their anti-parallel diodes D5~D8. The conduction and shutdown of Q5~Q8 occur in the period when the voltage at the output end of the secondary side of the transformer is zero. Therefore, Q5~Q8 can be turned on and off without voltage stress, that is, zero voltage switching is achieved, thereby significantly reducing the energy loss of the power switch tube during the switching process and improving the overall operating efficiency and performance of the high-frequency link single-phase isolation inverter.

[0060] Based on the above circuit structure, the present invention provides a method for suppressing the resonant voltage of a high-frequency link single-phase isolated inverter, which adopts a unipolar frequency-doubling phase-shift modulation strategy. The modulation strategy is as follows: Figure 2 As shown. Ignoring the conduction voltage drop of the transistor's anti-parallel diode, the conduction loss of the transistor and the switching loss, in the modulation wave u g >0, a complete switching cycle includes two carrier cycles, where the working mode of the previous carrier cycle is as follows, there are eight modes in total, among which i A (t0) is the initial value of the primary current.

[0061] Mode 1 (t0~t1): For the primary side of the transformer, due to U Q3 It is 0 before t0, so Q3 is turned off at zero voltage at t0. During this period, C3 is charged, C4 is discharged, and U AB =U Q3 ,i A <0. For the secondary side of the transformer, the output terminals C and E are connected through the clamping circuit Q n4 -D n2 Connect, U Qn2 = 0. Q5-D6 and Q n4 -D n2 These two paths provide paths for leakage inductor current and filter inductor current.

[0062] Mode 2 (t1~t2): For the primary side of the transformer, at t1, C3 and C4 complete charging and discharging respectively, and D4 is naturally turned on. During this period, the primary side current i A Energy is fed back to the DC power supply through the anti-parallel diode D1-D4 path, i A <0, and decays rapidly. At t2, i A =0, Q4 can achieve zero voltage conduction. For the secondary side of the transformer, Q n2It needs to be turned off before Q4 is turned on to avoid short circuit caused by sudden voltage on the secondary winding of the transformer. The dead time of Q3 and Q4 meets the conditions:

[0063]

[0064] Q n2 The zero voltage turn-off time meets the conditions:

[0065]

[0066] Mode 3 (t2~t3); for the primary side of the transformer, Q1 and Q4 are turned on, i A The direction of the change, i A >0. At t3, i A (t3) = Ni LF For the transformer secondary side, before t3, due to i A <Ni LF , winding N3 passes through Q n4 -D n2 for i LF Provides a current path.

[0067] Mode 4 (t3~t4): At time t3, i C =i LF =i A / N,U CD =NU AB =NV DC During this period, Q n1 Since Q n1 The potential at both ends is 2NV DC , so Q n1 It is zero voltage turn-on. Clamping capacitor C n5 By Q n1 and Q n4 Clamp the secondary voltage to 2NV DC . Cn1 =0,Q n1 It can be turned off at zero voltage before t4, Q n1 The zero voltage on-time condition is:

[0068]

[0069] Mode 5 (t4~t5): Due to U C1 =0, Q1 can be turned off at zero voltage at t4. During this period, C1 is charged, C2 is discharged, and U AB Gradually decrease, U AB =U EF =U C2 , L F , LK1 and L K2 Still equivalent series connection, i A =Ni LF .

[0070] Mode 6 (t5-t6): For the primary side of the transformer, at t5, C1 completes charging, C2 completes discharging, and U AB =U CE =U C2 =0,U C1 =V DC , D2 is naturally turned on. During this period, Q2 can achieve zero voltage conduction, i A Gradually decrease, i A >0. For the secondary side of the transformer, since winding N2 cannot support i LF , winding N3 passes through Q n4 -D n2 It provides a commutation path for the leakage inductor current and the filter inductor current. Cn2 =0,Q n2 Zero voltage turn-on can be achieved, and the dead time of Q1 and Q2 meets the conditions:

[0071]

[0072] Q n2 The zero voltage on-time condition is:

[0073]

[0074] Mode 7 (t6~t7): For the primary side of the transformer, during this period i A Continue to decrease, i A >0. For the secondary side of the transformer, Q7 and Q8 are turned on at t6. CE =0, Q7 and Q8 can achieve zero voltage conduction. During this period, Q5-D6, Q7-D8 and Q n4 -D n2 -Q5-D6 is i LF Providing a commutation path;

[0075] Mode 8 (t7~t8): Due to U CE =0, Q5 and Q6 can achieve zero voltage shutdown at t7, Q n4 Zero voltage shutdown can be achieved before t8. Winding N2 is connected to the n2 -D n4 Continue for i LF A commutation path is provided. During this period, since there is no sudden current change in winding N2, voltage overshoot caused by commutation of the cycloconverter is avoided.

[0076] In addition, in the modulation wave ug >0, the modes 9 to 16 in the next carrier cycle are similar to the modes 1 to 8 in the previous carrier cycle. The modes of the clamping circuit action in the previous carrier cycle are as follows: Figure 3 In the next carrier cycle, the full-bridge active clamp circuit uses Q n3 The zero voltage turn-on and turn-off makes the clamp capacitor C n5 Connect to the secondary side of the transformer to eliminate the voltage resonance spike. The clamping circuit action mode is as follows Figure 4 shown.

[0077] Before adding the clamping circuit, the output voltage and current waveforms of the transformer secondary side are shown in FIG5(a), and there is a very obvious voltage resonance peak in the transformer secondary side voltage. After adding the clamping circuit provided by the present invention, the output voltage and current waveforms of the transformer secondary side are shown in FIG5(b), and the transformer secondary side output voltage resonance peak is significantly eliminated.

[0078] After entering the full-bridge active clamping circuit, the harmonic content in the output voltage of the high-frequency link single-phase isolated inverter is analyzed, such as Figure 6 As shown, except for the fundamental frequency, the content of other harmonics accounts for a very small proportion.

[0079] When the modulation wave u g When >0, the power switch tubes Q1 and Q2 located in the leading bridge arm can easily achieve zero voltage switching, as shown in Figure 7(a) and Figure 7(b), while the power switch tubes Q3 and Q4 located in the trailing bridge arm are more difficult to achieve zero voltage switching, as shown in Figure 8(a) and Figure 8(b).

[0080] The zero voltage switching of the power switch tube of the full-bridge active clamping circuit of the present invention is analyzed. n1 , Q n2 With Q n3 , Q n4 They have the same conduction logic, so only Q needs to be verified n1 It can be a zero voltage switch, as shown in Figure 9(a) and Figure 9(b), Q n1 , Q n2 , Q n3 and Q n4 Both can achieve soft switching.

[0081] For the zero voltage switching analysis of the power switch tube of the cycloconverter of the present invention, the switch tubes Q5 and Q6, Q7 and Q8 are driven by the same PWM signal respectively, so it is only necessary to verify that Q5 and Q7 are zero voltage switches, as shown in Figures 10(a), 10(b), 11(a), and 11(b).

[0082] The above contents describe only embodiments of the present invention, and the present invention is not limited to the above embodiments. Various changes and improvements may be made within the spirit and scope of the present invention, and these changes and improvements shall fall within the scope of the present invention to be protected.

[0083] The above-described embodiment is only one of the specific forms of expression of the present invention and should not be regarded as limiting the scope of the present invention. Under the premise of following the core ideas and basic principles of the present invention, any form of changes and improvements are within the scope of protection of the present invention, and these changes and improvements are regarded as effective expansion and deepening of the present invention.

Claims

1. A high-frequency link single-phase isolated inverter voltage resonance spike suppression circuit, characterized in that: It includes a single-phase full-bridge inverter, a full-wave cycloconverter, a full-bridge active clamping circuit, an LC filter circuit and a load resistor; The single-phase full-bridge inverter includes a DC power supply V DC , DC bus capacitor C DC , transistors Q1, Q2, Q3, Q4, and their anti-parallel diodes D1, D2, D3, D4 and output capacitors C1, C2, C3, C4; The full-wave cycloconverter comprises transistors Q5, Q6, Q7, Q8 and anti-parallel diodes D5, D6, D7, D8; the series branch of transistors Q5 and Q6 is connected in parallel with the series branch of transistors Q7 and Q8; The full-bridge active clamp circuit includes a transistor Q n1 , Q n2 , Q n3 , Q n4 , anti-parallel diode D n1 , D n2 , D n3 , D n4 , output capacitor C n1 , C n2 , C n3 , C n4 And the clamping capacitor C n5 ; Transistor Q n1 , Q n2 The series branch and Q n3 , Q n4 The series branches are connected in parallel; The LC filter circuit includes a filter inductor L F And filter capacitor C F ; The collector of transistor Q5 is respectively connected to Q n1 The emitter, Q n2 The collector of transistor Q7 is connected to Q n3 The emitter, Q n4 The collector of the transistor Q6 is connected to the collector of Q8 and the L of the filter circuit F connect; The transistor Q n1 The collector and Q n3 The collector connection of transistor Q n1 The emitter and Q n2 The collector connection of transistor Q n2 The emitter and Q n4 The emitter connection of transistor Q n3 The emitter and Q n4 The collector connection of transistor Q n1 and Q n3 The collector and clamp capacitor C n5 The positive input terminal of transistor Q n2 and Q n4 The emitter and clamping capacitor C n5 The negative input terminal is connected; The primary leakage inductance of the transformer is L K1 , the transformer secondary leakage inductance is L K2 The C end of the secondary winding N2 is connected to the collector of transistor Q5, Q n1 The emitter and Q n2 The collector of the isolation transformer's secondary winding N3 is connected to the collector of transistor Q7, Q n3 The emitter, Q n4 The collector of the common terminal D is connected to the filter capacitor C F and load resistance R L .

2. The high-frequency link single-phase isolated inverter voltage resonance spike suppression circuit according to claim 1 is characterized in that: When the output terminal of the secondary side of the isolation transformer is in a positive or negative level state, the full-bridge clamp circuit passes C n5 The voltage resonance spike at the secondary output end of the isolation transformer is eliminated. Since the potential at both ends of the clamping capacitor is the same as the potential at the secondary output end of the isolation transformer, the clamping switch tube can achieve zero voltage switching; when the cycloconverter is commutating, a commutation path is provided for the filter inductor current; the cycloconverter includes transistors Q5, Q6, Q7, and Q8, and the turn-on and turn-off of the transistors Q5, Q6, Q7, and Q8 all occur during the period when the voltage at the secondary output end of the transformer is zero, so Q5, Q6, Q7, and Q8 can be turned on and off without voltage stress, that is, zero voltage switching is achieved.

3. A method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter, used in the voltage resonance peak suppression circuit of a high-frequency link single-phase isolated inverter according to any one of claims 1-2, characterized in that: Using a unipolar frequency-doubling phase-shift modulation strategy, a complete switching cycle includes two carrier cycles. g When >0, the working mode of the previous carrier cycle is as follows, with a total of eight modes: The capacitance of the power switch output capacitors C1 to C4 is C oss ,i A (t0) is the initial value of the primary current, L K1 is the primary leakage inductance of the transformer, L K2 is the secondary leakage inductance of the transformer, U AB is the voltage difference between the emitter of primary transistor Q1 and the collector of Q4, U EF is the voltage difference between the collector of transistor Q7 and the collector of Q8, U C2 is the voltage across the parasitic capacitor C2 of the transistor Q2, the transformation ratio of the transformer is N=N2 / N1=N3 / N1, where N1 represents the number of turns of the primary winding of the transformer, N2 represents the number of turns of one of the windings on the secondary side of the transformer, and N3 represents the number of turns of the other winding on the secondary side of the transformer. Mode 1, t0~t1: For the primary side of the transformer, due to U Q3 Before t0, it is 0, so Q3 is turned off at zero voltage at t0. During this period, C3 is charged, C4 is discharged, and U AB =U Q3 ,i A <0; For the secondary side of the transformer, the output terminals C and E pass through the clamping circuit Q n4 -D n2 Connect, U Qn2 =0; Q5-D6 and Q n4 -D n2 These two paths provide paths for leakage inductor current and filter inductor current; Mode 2, t1~t2: For the primary side of the transformer, at t1, C3 and C4 complete charging and discharging respectively, and D4 is naturally turned on; during this period, the primary side current i A Energy is fed back to the DC power supply through the anti-parallel diode D1-D4 path, i A <0, and decays rapidly; at t2, i A =0, Q4 can achieve zero voltage conduction; for the secondary side of the transformer, Q n2 It needs to be turned off before Q4 is turned on; Mode 3, t2~t3; for the primary side of the transformer, Q1 and Q4 are turned on, i A The direction of the change, i A >0; at t3, i A (t3) = Ni LF ; For the secondary side of the transformer, before t3, due to the primary current i A Less than the current Ni converted from the secondary filter inductor current to the primary side LF , i.e. i A <Ni LF , winding N3 passes through Q n4 -D n2 for i LF Provide a path for electric current; Mode 4, t3-t4: At time t3, i C =i LF =i A / N,U CD =NU AB =NV DC During this period, Q n1 conduction; due to Q n1 The potential at both ends is 2NV DC , so Q n1 Zero voltage conduction; clamping capacitor C n5 By Q n1 and Q n4 Clamp the secondary voltage to 2NV DC ; Due to U Cn1 =0,Q n1 It can be turned off at zero voltage before time t4; Mode 5, t4~t5: Due to U C1 =0, Q1 can be turned off at zero voltage at t4; during this period, C1 is charged, C2 is discharged, and U AB Gradually decrease, U AB =U EF =U C2 , L F , L K1 and L K2 Still equivalent series connection, i A =Ni LF ; Mode 6, t5-t6: For the primary side of the transformer, at t5, C1 completes charging, C2 completes discharging, and U AB =U CE =U C2 =0,U C1 =V DC , D2 is naturally turned on; during this period, Q2 can achieve zero voltage conduction, i A Gradually decrease, i A >0; For the secondary side of the transformer, since winding N2 cannot support i LF , winding N3 passes through Q n4 -D n2 Provides a commutation path for leakage inductance current and filter inductance current; during this period, U Cn2 =0,Q n2 Achieve zero voltage conduction; Mode 7, t6~t7: For the primary side of the transformer, i A Continues to decrease, and i A >0; For the secondary side of the transformer, Q7 and Q8 are turned on at t6; due to U CE =0, Q7 and Q8 are turned on at zero voltage; during this period, Q5-D6, Q7-D8 and Q n4 -D n2 -Q5-D6 is i LF Providing a commutation path; Mode 8, t7-t8: Due to U CE =0, Q5 and Q6 can achieve zero voltage shutdown at t7, Q n4 Zero voltage shutdown can be achieved before t8; winding N2 passes Q n2 -D n4 Continue for i LF Provides a commutation path.

4. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3 is characterized in that: In the modulation wave u g >0, in the next carrier cycle, the full-bridge active clamp circuit passes Q n3 The clamping capacitor C n5 Connect to the C and E terminals of the secondary side of the transformer to eliminate the voltage resonance spike. In this process, due to Q n3 The potentials at both ends are the same, so Q n3 Zero voltage switching can be achieved.

5. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3 is characterized in that: In mode 2, the dead time T of Q3 and Q4 dead2 The conditions are: V DC is the power supply voltage.

6. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3 is characterized in that: Q n2 Zero voltage turn-off time T delay1 The conditions are:

7. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3 is characterized in that: In mode 4, Q n1 The zero voltage on-time condition is:

8. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3 is characterized in that: In mode 6, the dead time of Q1 and Q2 meets the following conditions:

9. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3 is characterized in that: In mode 6, Q n2 The zero voltage on-time condition is:

10. The method for suppressing voltage resonance peak of a high-frequency link single-phase isolated inverter according to claim 3, characterized in that: Transistors Q5 and Q6, Q7 and Q8 are driven by the same PWM signal. n1 , Q n2 With Q n3 , Q n4 Has the same conduction logic; when the modulation wave u g >0, the power switch tubes Q1 and Q2 located in the leading bridge arm are easier to achieve zero voltage switching, while the power switch tubes Q3 and Q4 located in the trailing bridge arm are more difficult to achieve zero voltage switching.

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