Synchronous Rectification Control System and Power Supply System

Abstract

An embodiment of the present invention discloses a control system for synchronous rectification and a power supply system, which are applied to the technical field of electronic information processing. A control system for synchronous rectification includes a control module, a first-side timing control module, and a second-side timing control module, which can perform timing control on the switching tubes in the synchronous rectification system applied to a bidirectional switching power supply. Moreover, when one of the timing control modules in the synchronous rectification mode can generate a timing control signal according to the midpoint voltage signals of the two bridge arms in the synchronous rectification system to drive the corresponding full-bridge switching tubes, so that the signal transformation for driving the full-bridge switching tubes is consistent with the transformation of the midpoint voltage signals. In this way, the situation where the phase difference between the input voltage and the current phase of the resonant inductor after passing through the resonant network increases as the frequency of the input voltage on the active working mode side changes will not occur, achieving an optimal turn-on time for synchronous rectification, thereby maximizing the efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic information processing, and particularly to a control system and a power supply system for synchronous rectification. Background Art

[0002] Synchronous rectification is a technology that uses a dedicated power metal oxide semiconductor field effect transistor (MOSFET) with an extremely low on-resistance to replace the rectifier diode to reduce rectification losses. It can greatly improve the efficiency of the DC / DC converter and there is no dead zone voltage caused by the Schottky barrier voltage.

[0003] Synchronous rectification technology can significantly improve the conversion efficiency of the switching power supply under the condition of large current output and is widely used in unidirectional switching power supplies, where the current in the synchronous rectification switch tube flows unidirectionally. In recent years, the rise of the energy storage industry has led to an increasing demand for bidirectional power supplies. Since the current in the switch tube flows bidirectionally, the traditional synchronous rectification technology cannot meet the bidirectional requirements. Summary of the Invention

[0004] Embodiments of the present invention provide a control system and a power supply system for synchronous rectification, which achieve the optimal synchronous rectification turn-on time.

[0005] On the one hand, an embodiment of the present invention provides a control system for synchronous rectification, which is used for performing timing control on a synchronous rectification system. The synchronous rectification system includes: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit. Both the first-side full-bridge circuit and the second-side full-bridge circuit include two bridge arms. The control system for synchronous rectification includes:

[0006] A control module, which is used to generate a first control signal, a first enable signal, a second control signal, and a second enable signal. The first enable signal is used to control the first-side timing control module to be in the active working mode, and the second enable signal controls the second-side timing control module to be in the synchronous rectification mode;

[0007] A first-side timing control module, which is used to drive the first full-bridge switch tubes in the two first bridge arms according to the first control signal;

[0008] The second-side timing control module is used to respectively detect the second midpoint voltage signals corresponding to the two second bridge arms in the second-side full-bridge circuit, and drive the second full-bridge switching tubes in the two second bridge arms according to the second midpoint voltage signals and the second control signal, so that the phase-shift time of synchronous rectification of the second full-bridge switching tubes is the first phase-shift time, and the first phase-shift time is the voltage conversion arrival time of the second midpoint voltage signal.

[0009] Another aspect of the embodiments of the present invention further provides a power supply system, including: a synchronous rectification system and the control system of the synchronous rectification, wherein:

[0010] The synchronous rectification system includes: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit, and both the first-side full-bridge circuit and the second-side full-bridge circuit include two bridge arms;

[0011] The control system of the synchronous rectification is the control system of the synchronous rectification as described in one aspect of the embodiments of the present invention.

[0012] It can be seen that the control system of the synchronous rectification in the embodiments of the present invention includes a control module, a first-side timing control module, and a second-side timing control module, and can perform timing control on the switching tubes in the synchronous rectification system applied to the bidirectional switching power supply. Moreover, when one side timing control module in the synchronous rectification mode can generate a timing control signal according to the midpoint voltage signals of the two bridge arms in the synchronous rectification system to drive the corresponding full-bridge switching tubes, so that the signal conversion for driving the full-bridge switching tubes is consistent with the conversion of the midpoint voltage signals. In this way, the situation where the phase difference between the input voltage and the current phase of the resonant inductor after passing through the resonant network increases with the frequency change of the input voltage on the actively working mode side will not occur, achieving an optimal turn-on time for synchronous rectification, thereby maximizing the efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0014] Figure 1 is a schematic structural diagram of the synchronous rectification system in the embodiments of the present invention;

[0015] Figure 2a is a schematic structural diagram of a control system of a synchronous rectification provided by the embodiments of the present invention;

[0016] Figure 2bIt is a schematic structural diagram of another control system for synchronous rectification provided by an embodiment of the present invention;

[0017] Figure 3a It is a schematic structural diagram of the first-side timing control module provided by an embodiment of the present invention;

[0018] Figure 3b It is a schematic structural diagram of the second-side timing control module provided by an embodiment of the present invention;

[0019] Figure 4 It is a schematic structural diagram of the synchronous rectification system in a specific embodiment of the present invention;

[0020] Figure 5 It is a schematic structural diagram of the control module in the control system for synchronous rectification in a specific embodiment of the present invention. Specific Embodiments

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0022] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0023] An embodiment of the present invention provides a control system for synchronous rectification, mainly used for timing control of the synchronous rectification system. As Figure 1 shown, the synchronous rectification system may include: a first-side full-bridge circuit 10, a resonant network 11, an isolation transformer 12, and a second-side full-bridge circuit 13. Specifically:

[0024] The first-side full-bridge circuit 10 includes two first bridge arms, and each first bridge arm can include two first full-bridge switching tubes 110; the second-side full-bridge circuit 13 includes two second bridge arms, and each second bridge arm can include two second full-bridge switching tubes 113. Each full-bridge switching tube can specifically be a synchronous rectifier tube, such as a MOSFET. And for one of the two full-bridge circuits on both sides, a high-voltage power supply can be input, while for the other full-bridge circuit, a low-voltage power supply is input, which is a two-way switched-current system.

[0025] The resonant network 11 can specifically include two inductors and one capacitor, which is a DC-DC resonant network and can form an LLC resonant circuit or an LC resonant circuit.

[0026] The above-mentioned resonant network 11 and isolation transformer 12 are connected between the first-side full-bridge circuit 10 and the second-side full-bridge circuit 13.

[0027] If the first-side full-bridge circuit 10 is the high-voltage-side full-bridge circuit and the second-side full-bridge circuit 13 is the low-voltage-side full-bridge circuit, then such a synchronous rectification system can include two operating modes, namely the buck mode and the boost mode. Specifically:

[0028] In the buck mode, the two inductors and one capacitor in the resonant network 11 form an LLC resonant circuit. The switching frequency of the full-bridge switching tubes in the first-side full-bridge circuit 10 is changed to input the high-voltage power supply, and it is converted into a low-voltage output through the isolation transformer 12. At this time, the full-bridge switching tubes in the second-side full-bridge circuit 13 are synchronous rectifier tubes.

[0029] In the boost mode, one inductor and one capacitor in the resonant network 11 form an LC resonant circuit, and the other inductor does not participate in the resonance. The switching frequency of the full-bridge switching tubes in the second-side full-bridge circuit 13 is changed to input the low-voltage power supply, and it is converted into a high-voltage output through the isolation transformer 12. At this time, the full-bridge switching tubes in the first-side full-bridge circuit 10 are synchronous rectifier tubes.

[0030] The control system for synchronous rectification in this embodiment includes: a control module 20, a first-side timing control module 21, and a second-side timing control module 22, specifically as Figure 2a shown:

[0031] The control module 20 is used to generate a first control signal, a first enable signal, a second control signal, and a second enable signal. The first enable signal is used to control the first-side timing control module 21 to be in the active operating mode, and the second enable signal controls the second-side timing control module 22 to be in the synchronous rectification mode.

[0032] The first-side timing control module 21 is used to drive the first full-bridge switching tubes 110 in the two first bridge arms according to the first control signal.

[0033] The second-side timing control module 22 is used to respectively detect the second midpoint voltage signals corresponding to the two second bridge arms in the second-side full-bridge circuit 13, and drive the second full-bridge switching transistors 113 in the two second bridge arms according to the second midpoint voltage signals and the second control signal, so that the phase-shift time of the synchronous rectification of the second full-bridge switching transistors is the first phase-shift time, and the first phase-shift time is the voltage conversion arrival time of the second midpoint voltage signal. Here, the second midpoint voltage signal is the voltage signal between the two second full-bridge switching transistors 113 in any second bridge arm, and the voltage conversion arrival of the second midpoint voltage signal means that one of the two second midpoint voltage signals is at a low level and the other second midpoint voltage signal is at a high level.

[0034] Specifically, the second-side timing control module 22 combines the two second midpoint voltage signals to obtain a second comparison signal, then the control module 20 determines the first phase-shift time according to the second comparison signal, and generates the above-mentioned second control signal according to the first phase-shift time and outputs it to the second-side timing control module 22, and then the second-side timing control module 22 drives the second full-bridge switching transistors 113 to follow the above-mentioned second control signal. The determination of the first phase-shift time can be the time difference between the start time and the rising edge time of the second comparison signal, so that the change of the generated second control signal can be consistent with the change of the second midpoint voltage signal. In this way, after driving the first full-bridge switching transistors 110 and the second full-bridge switching transistors 113 by the first control signal and the second control signal respectively, the phase-shift time between the second full-bridge switching transistors 113 and the first full-bridge switching transistors 110 can be the first phase-shift time.

[0035] Here, the second comparison signal can be a signal indicating the difference between the two second midpoint voltage signals. For example, the second comparison signal can be a signal obtained by performing an exclusive OR operation on the two second midpoint voltage signals. When both of the two second midpoint voltage signals are at a high level or a low level, the obtained second comparison signal is at a low level, and vice versa, the obtained second comparison signal is at a high level.

[0036] In practical applications, in order to ensure that the change of the above-generated second control signal is consistent with the change of the above second midpoint voltage signal, the second control signal can be corrected. Specifically, when driving the second full-bridge switching transistors 113, the second-side timing control module 22 can correct the second control signal according to the second midpoint voltage signal to obtain a second corrected signal, so that the change of the second corrected signal is consistent with the change of the second midpoint voltage signal, and then drive the second full-bridge switching transistors 113 to follow the second corrected signal.

[0037] It can be understood that if the first-side full-bridge circuit 10 inputs a high-voltage power supply and the second-side full-bridge circuit 13 inputs a low-voltage power supply, the above-mentioned first-side timing control module 21 and second-side timing control module 22 mainly perform timing control when the synchronous rectification system is in the buck mode. In other embodiments, the first-side timing control module 21 and the second-side timing control module 22 can also perform timing control when the synchronous rectification system is in the boost mode, specifically as Figure 2b shown:

[0038] The first enable signal generated by the control module 20 is also used to control the first-side timing control module 21 to be in the synchronous rectification mode, and the second enable signal is also used to control the second-side timing control module 22 to be in the active working mode.

[0039] The first-side timing control module 21 is further configured to respectively detect the first midpoint voltage signals corresponding to the two first bridge arms in the first-side full-bridge circuit 10, and drive the first full-bridge switch tubes 110 in the two first bridge arms according to the first midpoint voltage signals and the first control signal, so that the phase-shift time of the first full-bridge switch tubes 110 for synchronous rectification is the second phase-shift time, and the second phase-shift time is the voltage transformation in-place time of the first midpoint voltage signals. Wherein, the voltage transformation in-place of the first midpoint voltage signals means that one of the two first midpoint voltage signals is at a low level and the other first midpoint voltage signal is at a high level.

[0040] Specifically, the first-side timing control module 21 combines the two first midpoint voltage signals to obtain a first comparison signal, then the control module 20 determines the second phase-shift time according to the first comparison signal, and generates the above-mentioned first control signal according to the second phase-shift time and outputs it to the first-side timing control module 21, and then the first-side timing control module 21 drives the first full-bridge switch tubes 110 to follow the above-mentioned first control signal. The determination of the second phase-shift time can be the time difference between the start time and the rising edge time of the first comparison signal, so that the transformation of the generated first control signal can be consistent with the transformation of the first midpoint voltage signals. In this way, after driving the first full-bridge switch tubes 110 and the second full-bridge switch tubes 113 with the first control signal and the second control signal respectively, the phase-shift time between the first full-bridge switch tubes 110 and the second full-bridge switch tubes 113 can be the second phase-shift time.

[0041] Here, the first comparison signal can be a signal indicating the difference between the two first midpoint voltage signals. For example, the first comparison signal can be a signal obtained by performing an exclusive OR operation on the two first midpoint voltage signals. When the two first midpoint voltage signals are both at a high level or a low level, the obtained first comparison signal is at a low level, and vice versa, the obtained first comparison signal is at a high level.

[0042] In practical applications, in order to ensure that the transformation of the first control signal generated above is consistent with the transformation of the first midpoint voltage signal, the first control signal can be corrected. Specifically, when the first-side timing control module 21 drives the first full-bridge switch 110, it can correct the first control signal according to the first midpoint voltage signal to obtain a first corrected signal, so that the transformation of the first corrected signal is consistent with the transformation of the first midpoint voltage signal, and then drive the first full-bridge switch 110 to follow the first corrected signal.

[0043] The second-side timing control module 22 is further configured to drive the second full-bridge switches 113 in the two second bridge arms according to the second control signal.

[0044] In a specific embodiment, the structures of the first-side timing control module 21 and the second-side timing control module 22 in the synchronous rectification control system may be the same. Among them, the first-side timing control module 21 may be as Figure 3a shown, including: a driving generation circuit 211 composed of an exclusive-OR gate U1, two first AND gates U2 and U2', two OR gates U3 and U3', and two second AND gates U4 and U4'. And it may further include a first midpoint sampling and conversion circuit 221 and a first output driving circuit 231. Specifically:

[0045] The first midpoint voltage signals HV_VS1 and HV_VS2 are connected to the inputs of the exclusive-OR gate U1 and are respectively connected to the inputs of each of the first AND gates U2 and U2'. The output of the exclusive-OR gate U1 is respectively connected to the inputs of each of the first AND gates U2 and U2'. The outputs of the two first AND gates U2 and U2' are respectively connected to the inputs of the two OR gates U3 and U3'. The first enable signal HV_SYN_EN is respectively connected to each of the OR gates U3 and U3'. The outputs of the two OR gates U3 and U3' are respectively connected to the two second AND gates U4 and U4'. The two first control sub-signals PWM1 and PWM2 in the first control signal are respectively connected to the two second AND gates U4 and U4'. The outputs of the two second AND gates U4 and U4' are respectively connected to the driving ends of the first full-bridge switches 110. Among them, the output of the exclusive-OR gate U1 will be connected to the control module 20.

[0046] In the specific implementation process, when connecting the first midpoint voltage signal to the driving generation circuit 211, a first midpoint sampling and conversion circuit 221 can be used. The first midpoint sampling and conversion circuit 221 is configured to convert the first midpoint voltage signals HV_VS1 and HV_VS2 and connect the converted first midpoint voltage signals VS1 and VS2 to the inputs of the exclusive-OR gate U1.

[0047] When driving the first full-bridge switch 110, a driving signal can be directly output to the first full-bridge switch 110 through the first output driving circuit 231 (denoted as U5 and U5'). The first output driving circuit 231 is used to convert the signals output by the two second AND gates U4 and U4' into driving signals HV_G1A, HV_G2B, HV_G2A, and HV_G1B, and connect the driving signals to the driving ends of the first full-bridge switch 110.

[0048] Specifically, through the exclusive-OR gate U1, exclusive-OR calculations can be performed on the signals VS1 and VS2 obtained by level conversion of the first midpoint voltage signals HV_VS1 and HV_VS2 to obtain the first comparison signal In0, which can ensure that when the potentials of the two converted first midpoint voltage signals VS1 and VS2 change in place, it can be reflected by the first comparison signal In0. For example, when the converted first midpoint voltage signals VS1 and VS2 are both high level or low level, the first comparison signal In0 is low level, and when the converted first midpoint voltage signals VS1 and VS2 are at different levels, the first comparison signal In0 is high level.

[0049] Further, both of the two first AND gates U2 and U2' combine with the first comparison signal In0 to respectively output synchronous rectification signals In1 and In1', which respectively reflect the changes of the converted first midpoint voltage signals VS1 and VS2, and at the same time can reflect the changes of the first midpoint voltage signals HV_VS1 and HV_VS2. Then, through the two OR gates U3 and U3' respectively combined with the first enable signal, the first enable signal can cause the synchronous rectification process signal to be ignored when the first-side timing control module 21 is in the active working mode, and when the first-side timing control module 21 is in the synchronous rectification mode, synchronous rectification process signals In2 and In2' are respectively output. Finally, in the synchronous rectification mode, the two second AND gates U4 and U4' can respectively correct the two first control sub-signals PWM1 and PWM2, that is, correct them respectively through the synchronous rectification process signals In2 and In2'. The correction time is the first phase shift time, so that the change of the obtained first corrected signal is consistent with the change of the first midpoint voltage signal.

[0050] Further, the second-side timing control module 22 can be as Figure 3b shown, including: a driving generation circuit 212 composed of an exclusive-OR gate U6, two first AND gates U7 and U7', two OR gates U8 and U8', and two second AND gates U9 and U9', and can also include a second midpoint sampling and conversion circuit 222 and a second output driving circuit 232. Specifically:

[0051] The second midpoint voltage signals LV_VS1 and LV_VS2 are connected to the inputs of the exclusive-OR gate U6, and are respectively connected to the inputs of each of the first AND gates U7 and U7'. The output of the exclusive-OR gate U6 is respectively connected to the inputs of each of the first AND gates U7 and U7'. The outputs of the two first AND gates U7 and U7' are respectively connected to the inputs of two OR gates U8 and U8'. The second enable signal LV_SYN_EN is respectively connected to each of the OR gates U8 and U8'. The outputs of the two OR gates U8 and U8' are respectively connected to two second AND gates U9 and U9'. The two second control sub-signals PWM3 and PWM4 in the second control signal are respectively connected to the two second AND gates U9 and U9'. The outputs of the two second AND gates U9 and U9' are respectively connected to the driving ends of the second full-bridge switch tubes 130. Among them, the output of the exclusive-OR gate U6 is connected to the control module 20.

[0052] In the specific implementation process, when connecting the second midpoint voltage signal to the driving generation circuit 212, a second midpoint sampling and conversion circuit 222 can be used. The second midpoint sampling and conversion circuit 222 is used to convert the second midpoint voltage signals LV_VS1 and LV_VS2, and connect the converted second midpoint voltage signals VS3 and VS4 to the inputs of the exclusive-OR gate U6.

[0053] When driving the second full-bridge switch tube 113, the second output driving circuit 232 (denoted as U10 and U10') can be used to directly output driving signals to the second full-bridge switch tube 113. The second output driving circuit 232 is used to convert the signals output by the two second AND gates U9 and U9' into driving signals LV_G3A, LV_G4B, LV_G4A, and LV_G3B, and connect the driving signals to the driving ends of the second full-bridge switch tubes 130.

[0054] Specifically, the exclusive-OR gate U6 can perform an exclusive-OR calculation on the signals VS3 and VS4 obtained by level conversion of the second midpoint voltage signals LV_VS1 and LV_VS2 to obtain the second comparison signal In0'. It can ensure that when the potentials of the two converted second midpoint voltage signals VS3 and VS4 change in place, it can be reflected by the second comparison signal In0'. For example, when the converted second midpoint voltage signals VS3 and VS4 are both high level or low level, the second comparison signal In0' is low level. When the converted second midpoint voltage signals VS3 and VS4 are at different levels, the second comparison signal In0' is high level.

[0055] Further, both of the two first AND gates U7 and U7' are combined with the second comparison signal In0', and respectively output synchronous rectification signals In3 and In3', which respectively reflect the transformation of the converted second midpoint voltage signals VS3 and VS4, and at the same time can reflect the transformation of the second midpoint voltage signals LV_VS1 and LV_VS2. Then, after passing through two OR gates U8 and U8' respectively combined with the second enable signal, the second enable signal can cause the synchronous rectification process signal to be ignored when the second-side timing control module 22 is in the active working mode, and when the second-side timing control module 22 is in the synchronous rectification mode, the synchronous rectification process signals In4 and In4' are respectively output. Finally, in the synchronous rectification mode, the two second AND gates U9 and U9' can respectively correct the two second control sub-signals PWM3 and PWM4, that is, respectively correct them through the synchronous rectification process signals In4 and In4', and the correction time is the second phase shift time, so that the transformation of the obtained second corrected signal is consistent with the transformation of the second midpoint voltage signal.

[0056] It can be seen that the synchronous rectification control system in this embodiment includes a control module 20, a first-side timing control module 21, and a second-side timing control module 22, which can perform timing control on the switching tubes in the synchronous rectification system applied to the bidirectional switching power supply. And when one of the timing control modules in the synchronous rectification mode can generate a timing control signal according to the midpoint voltage signals of the two bridge arms in the synchronous rectification system to drive the corresponding full-bridge switching tube, so that the signal transformation for driving the full-bridge switching tube is consistent with the transformation of the midpoint voltage signal. In this way, the situation where the phase difference between the input voltage and the current phase of the resonant inductor after passing through the resonant network increases with the frequency change of the input voltage on the active working mode side will not occur, achieving an optimal synchronous rectification turn-on time, thereby maximizing the efficiency.

[0057] A specific embodiment of the present invention provides a synchronous rectification control system, which mainly performs timing control on the synchronous rectification system. In this embodiment, the synchronous rectification system can be as Figure 4 shown, where:

[0058] The first-side full-bridge circuit 10 is specifically a high-voltage-side full-bridge circuit, which inputs a high-voltage power supply HVDC. The first full-bridge switching transistors included in the high-voltage-side full-bridge circuit are Q1A, Q2A, Q1B, and Q2B, and the signals for driving these full-bridge switching transistors are HV_G1A, HV_G2A, HV_G1B, and HV_G2B respectively. The first midpoint voltage signals of the two first bridge arms are HV_VS1 and HV_VS2 respectively; the second-side full-bridge circuit 13 is specifically a low-voltage-side full-bridge circuit, which inputs a low-voltage power supply LVDC. The second full-bridge switching transistors included in the low-voltage-side full-bridge circuit are Q3A, Q4A, Q3B, and Q4B, and the signals for driving these full-bridge switching transistors are LV_G3A, LV_G4A, LV_G3B, and LV_G4B respectively. The second midpoint voltage signals of the two second bridge arms are LV_VS1 and LV_VS2 respectively.

[0059] The resonant network 11 is specifically a DC-DC resonant network, including an inductor Lr, an inductor Lm, and a capacitor Cr. The isolation transformer 12 is T1.

[0060] In the synchronous rectification control system of this embodiment, the first-side timing control module 21 and the second-side timing control module 22 can be specifically as described above Figure 3a and Figure 3b shown, and the control module 20 in the control system is specifically a controller U0 as shown in Figure 5 shown, which can generate a first enable signal HV_SYN_EN, a second enable signal LV_SYN_EN, two first control sub-signals PWM1 and PWM2 in the first control signal, and two second control sub-signals PWM3 and PWM4 in the second control signal.

[0061] In this way, in this embodiment, the synchronous rectification control system can perform timing control on the synchronous rectification system in the following two modes of the synchronous rectification system:

[0062] I. When the synchronous rectification system is in the buck mode

[0063] When the synchronous rectification system is in the buck mode, Lr, Cr, and Lm in the resonant network 11 form an LLC resonant circuit. By changing the switching frequencies of the first full-bridge switching transistors Q1A, Q1B, Q2A, and Q2B in the high-voltage-side full-bridge circuit, the high-voltage input voltage HVDC is converted into a low-voltage output voltage LVDC through the isolation transformer T1. The second full-bridge switching transistors Q3A, Q3B, Q4A, and Q4B in the low-voltage-side full-bridge circuit are synchronous rectification transistors. In this case, in the synchronous rectification control system:

[0064] When the synchronous rectification system is in buck mode, the first enable signal HV_SYN_EN generated by the controller U0 is low, controlling the first-side timing control module 21 to be in the active working mode; and two first control sub-signals PWM1 and PWM2 are generated. These two first control sub-signals have a certain dead zone, a duty cycle of approximately 50% and are high-low complementary, and are variable-frequency square waves.

[0065] The first midpoint sampling and conversion circuit 221 in the first-side timing control module 21 collects the first midpoint voltage signals HV_VS1 and HV_VS2 of the two bridge arms of the high-voltage side full-bridge circuit in the synchronous rectification system. The obtained converted signals VS1 and VS2 are respectively output to two first AND gates U2 and U2', and are also respectively connected to the inputs of the exclusive-OR gate U1. In this way, the exclusive-OR gate U1 outputs a signal In0 according to the two converted signals VS1 and VS2.

[0066] The first AND gate U2 outputs a signal In1 according to the converted signal VS1 and the signal In0. The first AND gate U2' outputs a signal In1' according to the converted signal VS2 and the signal In0. The OR gate U3 outputs a signal In2 according to the signal In1 and the first enable signal HV_SYN_EN. The OR gate U3' outputs a signal In2' according to the signal In1' and the first enable signal HV_SYN_EN. The signals In2 and In2' are high. The second AND gate U4 outputs a PWM signal following the first control sub-signal PWM1 according to the signal In2 and a first control sub-signal PWM1. The second AND gate U4' outputs a PWM signal following the first control sub-signal PWM2 according to the signal In2' and another first control sub-signal PWM2.

[0067] The outputs of the second AND gates U4 and U4' are respectively connected to two first output driving circuits 231 (denoted as U5 and U5') to output driving signals, respectively driving the first full-bridge switching transistors Q1A and Q2B and Q2A and Q1B.

[0068] The second midpoint sampling and conversion circuit 222 in the second-side timing control module 22 collects the second midpoint voltage signals LV_VS1 and LV_VS2 of the two bridge arms of the low-voltage side full-bridge circuit in the synchronous rectification system. The obtained converted signals VS3 and VS4 are respectively output to two first AND gates U7 and U7', and are also respectively connected to the inputs of the exclusive-OR gate U6. In this way, the exclusive-OR gate U6 outputs a signal In0' according to the two converted signals VS3 and VS4.

[0069] The first AND gate U7 outputs signal In3 according to the converted signal VS3 and signal In0'. The first AND gate U7' outputs signal In3' according to the converted signal VS4 and signal In0'. The OR gate U8 outputs signal In4 according to signal In3 and the second enable signal LV_SYN_EN. The OR gate U8' outputs signal In4' according to signal In3' and the second enable signal LV_SYN_EN. The second enable signal LV_SYN_EN is constantly at a low level, so signals In4 and In4' respectively follow signals In3 and In3'. The second AND gate U9 outputs a signal to the second output driving circuit 232 (denoted as U10) according to signal In4 and a second control sub-signal PWM3. The second AND gate U9' outputs a signal to the second output driving circuit 232 (denoted as U10') according to signal In4' and another second control sub-signal PWM4.

[0070] The second output driving circuit 232 outputs driving signals to drive the second full-bridge switching transistors Q3A and Q4B and Q4A and Q3B respectively.

[0071] In this process, the controller U0 can calculate the first phase shift time of synchronous rectification (relative to the rising edge signal of In0) based on the rising edge signal of signal In0', and set the starting points of the high-level signals of the two second control sub-signals PWM3 and PWM4 based on the first phase shift time. The falling edges of the two second control sub-signals PWM3 and PWM4 are shifted backward by the first phase shift time based on the falling edges of the above two first control sub-signals PWM1 and PWM2 to set the ending points of the high-level signals of the two second control sub-signals PWM3 and PWM4.

[0072] Among them, since signal In0' is output according to two second midpoint voltage signals, the first phase shift time is determined based on the second midpoint voltage signal.

[0073] Also, since the signals driving the first full-bridge switching transistors 110 follow the first control sub-signals PWM1 and PWM2, and the signals driving the second full-bridge switching transistors 113 follow the second control sub-signals PWM3 and PWM4, the phase shift between the second full-bridge switching transistors 113 and the first full-bridge switching transistors 110 is the first phase shift time.

[0074] (4) When the synchronous rectification system is in the buck mode, the XOR gate U6 in the second-side timing control module 22 is an interlock circuit. When the converted signals VS3 and VS4 pass through high or low levels, the output signal In0' is at a low level, thereby making the synchronous rectification signals In4 and In4' at a low level and turning off the synchronous rectification drive.

[0075] The functions of the two first AND gates U7 and U7' are to insert the signal In0' into the synchronous rectification signals of the converted signals VS3 and VS4, so as to obtain the output synchronous rectification signals In4 and In4'. The functions of the two OR gates U8 and U8' are to output the synchronous rectification signals In4 and In4' under the condition of buck mode. The functions of the two second AND gates U9 and U9' are to respectively increase the synchronous rectification signals In4 and In4' with the second control sub-signals PWM3 and PWM4, improving the reliability.

[0076] II. When the synchronous rectification system is in boost mode

[0077] When the synchronous rectification system is in boost mode, Lr and Cr in the resonant network 11 form an LC resonant circuit, changing the switching frequencies of the second full-bridge switching transistors Q3A, Q3B, Q4A, and Q4B in the low-voltage side full-bridge circuit to convert the low-voltage input voltage LVDC into a high-voltage output voltage HVDC through the isolation transformer T1. The first full-bridge switching transistors Q1A, Q1B, Q2A, and Q2B in the high-voltage side full-bridge circuit are synchronous rectification transistors. In this case, in the control system of synchronous rectification:

[0078] (1) When the synchronous rectification system is in boost mode, the second enable signal LV_SYN_EN generated by the controller U0 is low, controlling the second-side timing control module 22 to be in the active working mode; and two second control sub-signals PWM3 and PWM4 are generated. These two second control sub-signals have a certain dead zone, a duty cycle of about 50% and are high-low complementary, and are variable-frequency square waves.

[0079] (2) The second midpoint sampling and conversion circuit 222 in the second-side timing control module 22 will collect the second midpoint voltage signals LV_VS1 and LV_VS2 of the two arms of the low-voltage side full-bridge circuit in the synchronous rectification system. The obtained converted signals VS3 and VS4 are respectively output to the two first AND gates U7 and U7', and are also respectively connected to the inputs of the exclusive-OR gate U6. In this way, the exclusive-OR gate U6 outputs the signal In0' according to the two converted signals VS3 and VS4.

[0080] The first AND gate U7 outputs a signal In3 according to the converted signal VS3 and the signal In0'. The first AND gate U7' outputs a signal In3' according to the converted signal VS4 and the signal In0'. The OR gate U8 outputs a signal In4 according to the signal In4 and the second enable signal LV_SYN_EN. The OR gate U8' outputs a signal In4' according to the signal In3' and the second enable signal LV_SYN_EN. The signals In4 and In4' are high. The second AND gate U9 outputs a PWM signal following the second control sub-signal PWM3 according to the signal In4 and a second control sub-signal PWM3. The second AND gate U9' outputs a PWM signal following the second control sub-signal PWM4 according to the signal In4' and another second control sub-signal PWM4.

[0081] The outputs of the second AND gates U9 and U9' are respectively connected to two second output driving circuits 232 (denoted as U10 and U10') to output driving signals, which respectively drive the second full-bridge switching transistors Q3A and Q4B and Q4A and Q3B to follow the second control sub-signal.

[0082] (3)The first midpoint sampling conversion circuit 221 in the first-side timing control module 21 collects the first midpoint voltage signals HV_VS1 and HV_VS2 of two arms of the high-voltage side full-bridge circuit in the synchronous rectification system. The obtained converted signals VS1 and VS2 are respectively output to two first AND gates U2 and U2', and are also respectively connected to the inputs of the XOR gate U1. In this way, the XOR gate U1 outputs a signal In0 according to the two converted signals VS1 and VS2.

[0083] The first AND gate U2 outputs a signal In1 according to the converted signal VS1 and the signal In0. The first AND gate U2' outputs a signal In1' according to the converted signal VS2 and the signal In0. The OR gate U3 outputs a signal In2 according to the signal In1 and the first enable signal HV_SYN_EN. The OR gate U3' outputs a signal In2' according to the signal In1' and the first enable signal HV_SYN_EN. The first enable signal HV_SYN_EN is constantly at a low level, so the signals In2 and In2' respectively follow the signals In1 and In1'. The second AND gate U4 outputs a signal to the first output driving circuit 231 (denoted as U5) according to the signal In2 and a first control sub-signal PWM1. The second AND gate U4' outputs a signal to the first output driving circuit 231 (denoted as U5') according to the signal In2' and another first control sub-signal PWM2.

[0084] The first output driving circuit 231 outputs driving signals to respectively drive the first full-bridge switching transistors Q1A and Q2B and Q2A and Q1B.

[0085] During this process, the controller U0 can calculate the second phase shift time of synchronous rectification (relative to the rising edge signal of In0’) based on the rising edge signal of the signal In0, and set the starting points of the high-level signals of the two first control sub-signals PWM1 and PWM2 based on the second phase shift time. The falling edges of the two first control sub-signals PWM1 and PWM2 are shifted backward by the second phase shift time based on the falling edges of the two second control sub-signals PWM3 and PWM4 to set the ending points of the high-level signals of the two first control sub-signals PWM1 and PWM2.

[0086] Since the signal In0 is output according to the two first midpoint voltage signals, the second phase shift time is determined based on the first midpoint voltage signals when determining the second phase shift time.

[0087] Also, since the signal driving the second full-bridge switch 113 follows the second control sub-signals PWM3 and PWM4, and the signal driving the first full-bridge switch 110 follows the first control sub-signals PWM1 and PWM2, the phase shift between the first full-bridge switch 110 and the second full-bridge switch 113 is the second phase shift time.

[0088] (4) When the synchronous rectification system is in the boost mode, the exclusive-OR gate U1 in the first-side timing control module 21 is an interlock circuit. When the converted signals VS1 and VS2 pass through high or low levels, the output signal In0 is at a low level, thereby making the synchronous rectification signals In2 and In2’ low and turning off the synchronous rectification drive.

[0089] The functions of the two first AND gates U2 and U2’ are to insert the signal In0 into the synchronous rectification signals of the converted signals VS1 and VS2, thereby generating the output synchronous rectification signals In2 and In2’. The functions of the two OR gates U3 and U3’ are to output the synchronous rectification signals In2 and In2’ under the conditions of the boost mode. The functions of the two second AND gates U4 and U4’ are to respectively increase the synchronous rectification signals In2 and In2’ with the first control sub-signals PWM1 and PWM2 to improve the reliability.

[0090] The embodiment of the present invention further provides a power supply system, which is a bidirectional switching power supply and mainly applies the above synchronous rectification system. The synchronous rectification system may include: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit. The first-side full-bridge circuit and the second-side full-bridge circuit each include two bridge arms. The control system of synchronous rectification is the control system of synchronous rectification as described in the above embodiment, which will not be elaborated here.

[0091] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. The storage medium may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disc, etc.

[0092] The above has introduced in detail a synchronous rectification control system and a power supply system provided by an embodiment of the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A control system for synchronous rectification, characterized in that, For timing control of a synchronous rectification system, the synchronous rectification system includes: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit. The first-side full-bridge circuit and the second-side full-bridge circuit each include two bridge arms. The control system of the synchronous rectification includes: A control module for generating a first control signal, a first enable signal, a second control signal, and a second enable signal. The first enable signal is used to control the first-side timing control module to be in an active working mode, and the second enable signal controls the second-side timing control module to be in a synchronous rectification mode; A first-side timing control module for driving a first full-bridge switch tube in two first bridge arms according to the first control signal; A second-side timing control module for respectively detecting second midpoint voltage signals corresponding to two second bridge arms in the second-side full-bridge circuit, and driving second full-bridge switch tubes in the two second bridge arms according to the second midpoint voltage signals and the second control signal, so that the phase shift time of synchronous rectification of the second full-bridge switch tubes is a first phase shift time. The first phase shift time is the voltage transformation in-place time of the second midpoint voltage signal; wherein the voltage transformation in-place of the second midpoint voltage signal means that one of the two second midpoint voltage signals is at a low level and the other second midpoint voltage signal is at a high level; The second-side timing control module is specifically configured to obtain a second comparison signal according to the second midpoint voltage signal. The control module determines the first phase shift time according to the second comparison signal, and generates the second control signal according to the first phase shift time. The second-side timing control module drives the second full-bridge switch tubes to follow the second control signal; wherein the second comparison signal is a signal obtained by performing an exclusive OR operation on the two second midpoint voltage signals; The first phase shift time is the time difference between the start time and the rising edge time of the second comparison signal.

2. The system according to claim 1, wherein The second-side timing control module driving the second full-bridge switch tubes to follow the second control signal specifically includes: The second-side timing control module corrects the second control signal according to the second midpoint voltage signal to obtain a second corrected signal, and drives the second full-bridge switch tubes to follow the second corrected signal.

3. The system according to claim 1, wherein The first enable signal generated by the control module is further used to control the first-side timing control module to be in a synchronous rectification mode, and the second enable signal is further used to control the second-side timing control module to be in an active working mode; The first-side timing control module is used to respectively detect the first midpoint voltage signals corresponding to two first bridge arms in the first-side full-bridge circuit, and drive the first full-bridge switching tubes in the two first bridge arms according to the first midpoint voltage signals and the first control signal, so that the phase-shift time of synchronous rectification of the first full-bridge switching tubes is the second phase-shift time, and the second phase-shift time is the voltage transformation in-place time of the first midpoint voltage signal; wherein the voltage transformation in-place of the first midpoint voltage signal means that one of the two first midpoint voltage signals is at a low level and the other first midpoint voltage signal is at a high level. The second-side timing control module is further used to drive the second full-bridge switching tubes in the two second bridge arms according to the second control signal.

4. The system according to claim 3, wherein The first-side timing control module is specifically used to obtain a first comparison signal according to the two first midpoint voltage signals, the control module determines the second phase-shift time according to the first comparison signal, and generates the first control signal according to the second phase-shift time. The first-side timing control module drives the first full-bridge switching tubes to follow the first control signal; the second phase-shift time is the time difference between the start time and the rising edge time of the first comparison signal, and the first comparison signal is a signal obtained by performing an exclusive OR operation on the two first midpoint voltage signals.

5. The system according to claim 3 or 4, characterized in that, The first-side timing control module includes: an exclusive OR gate, two first AND gates, two OR gates, and two second AND gates; The first midpoint voltage signal is connected to the input of the exclusive OR gate and respectively connected to the first input of each of the first AND gates, and the output of the exclusive OR gate is respectively connected to the second input of each of the first AND gates; The outputs of the two first AND gates are respectively connected to the first inputs of the two OR gates, and the first enable signal is respectively connected to the second input of each of the OR gates; The outputs of the two OR gates are respectively connected to the first inputs of the two second AND gates, two first control sub-signals in the first control signal are respectively connected to the second inputs of the two second AND gates, and the outputs of the two second AND gates are respectively connected to the drive ends of the first full-bridge switching tubes.

6. The system according to claim 5, wherein The first-side timing control module further includes: a first midpoint sampling and conversion circuit and a first output driving circuit, wherein: The first midpoint sampling and conversion circuit is used to convert the first midpoint voltage signal and connect the converted first midpoint voltage signal to the input of the exclusive OR gate; The first output driving circuit is used to convert the signals output by the two second AND gates into driving signals and connect the driving signals to the drive ends of the first full-bridge switching tubes.

7. The system according to any one of claims 1 to 4, characterized in that, The second-side timing control module includes: an exclusive OR gate, two first AND gates, two OR gates, and two second AND gates; The second midpoint voltage signal is connected to the input of the exclusive OR gate and respectively connected to the first input of each of the first AND gates, and the output of the exclusive OR gate is respectively connected to the second input of each of the first AND gates; The outputs of the two first AND gates are respectively connected to the first inputs of the two OR gates, and the second enable signals are respectively connected to the second inputs of each of the OR gates; The outputs of the two OR gates are respectively connected to the first inputs of the two second AND gates, two second control sub-signals in the second control signal are respectively connected to the second inputs of the two second AND gates, and the outputs of the two second AND gates are respectively connected to the driving ends of the second full-bridge switching tubes.

8. The system according to claim 7, wherein The second-side timing control module further includes: a second midpoint sampling and conversion circuit and a second output driving circuit, wherein: The second midpoint sampling and conversion circuit is configured to convert the second midpoint voltage signal, and connect the converted second midpoint voltage signal to the input of the exclusive-OR gate in the second-side timing control module; The second output driving circuit is configured to convert the signals output by the second AND gates in the two second-side timing control modules into driving signals, and connect the driving signals to the driving ends of the second full-bridge switching tubes.

9. A power supply system, characterized in that, Comprising: A synchronous rectification system and a control system for the synchronous rectification, wherein: The synchronous rectification system includes: a first-side full-bridge circuit, a resonant network, an isolation transformer, and a second-side full-bridge circuit, and both the first-side full-bridge circuit and the second-side full-bridge circuit include two bridge arms; The control system for the synchronous rectification is the control system for the synchronous rectification according to any one of claims 1 to 8.

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