RC oscillator circuit

Abstract

The invention relates to the technical field of circuits, in particular to an RC oscillator circuit, which comprises a reference current module for providing a reference current and a reference voltage; the input end of the buffer module is connected with the reference current module; and the clock generation module is connected with the reference current module and the buffer module and outputs a clock signal under the action of the group of switch sequence signals. According to the low-temperature-drift RC oscillator circuit provided by the invention, current and reference voltage which do not change along with the temperature are generated through the reference current module, and the voltage drift generated by circuit matching can be offset by switching the working state of the clock generation module under the action of a switch sequence signal.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an RC oscillator circuit. Background Art

[0002] An RC oscillator is a sinusoidal oscillator that generates a sinusoidal wave as an output with the help of linear electronic components. The oscillation frequency of the oscillation circuit varies with temperature. Therefore, for a high-precision oscillator, the oscillation frequency needs to be adjusted to prevent it from being affected by temperature. The RC oscillator in the prior art has the disadvantages of large output variations with temperature and voltage, high power consumption, and inaccurate RC output frequency. Summary of the invention

[0003] In view of the above problems, the object of the present invention is to provide an RC oscillator circuit;

[0004] An RC oscillator circuit, comprising:

[0005] A reference current module provides a reference current and a reference voltage;

[0006] A buffer module, an input end of which is connected to the reference current module;

[0007] The clock generating module is connected to the reference current module and the buffer module, and outputs a clock signal under the action of a set of switch timing signals.

[0008] The RC oscillator circuit of the present invention, the reference current module comprises:

[0009] A first PMOS tube is connected between a power supply voltage and a first reference node, and a gate electrode and a drain electrode of the first PMOS tube are connected;

[0010] A first switch tube, controllably connected to the first reference node and a second reference node under the control of a constant temperature voltage, wherein the second reference node outputs the reference voltage;

[0011] The variable resistor is connected between the second reference node and the ground terminal.

[0012] In the RC oscillator circuit of the present invention, the buffer module includes a buffer, and the buffer includes:

[0013] A non-inverting input terminal connected to the reference voltage;

[0014] The inverting input terminal is connected to the output terminal of the buffer.

[0015] The RC oscillator circuit of the present invention, the clock generation module comprises:

[0016] a second PMOS transistor, wherein a gate of the second PMOS transistor is connected to the first reference node, and a source of the second PMOS transistor is connected to a power supply voltage;

[0017] a third PMOS transistor, controllably connected between the drain of the second PMOS transistor and a third reference node under the action of a first control signal;

[0018] a fourth PMOS transistor, controllably connected between the drain of the second PMOS transistor and a fourth reference node under the action of a second control signal;

[0019] A second switch tube, controllably connected between the third reference node and a first input terminal of a comparator under the action of a second control signal;

[0020] A third switch tube, controllably connected between the fourth reference node and the second input terminal of the comparator under the action of the first control signal;

[0021] The output terminal of the comparator outputs the clock signal.

[0022] In the RC oscillator circuit of the present invention, the switch timing signal is generated by a switch timing generation module, and the switch timing generation module includes:

[0023] A first inverter, connected to the output end of the clock generating module, the first inverter outputs the first control signal;

[0024] A second inverter, connected to an output end of the first inverter, the second inverter outputting the second control signal;

[0025] The third inverter is connected to the output end of the second inverter.

[0026] The RC oscillator circuit of the present invention, the clock generation module comprises:

[0027] a fourth switch tube, controllably connected between the third reference node and the ground terminal under the action of a third control signal;

[0028] A first capacitor connected in parallel with the fourth switch tube;

[0029] a fifth switch tube, controllably connected between the fourth reference node and the ground terminal under the action of a fourth control signal;

[0030] The second capacitor is connected in parallel with the fifth switch tube.

[0031] The RC oscillator circuit of the present invention, the switch timing generation module further includes:

[0032] A delayer connected to the output end of the first inverter, the delayer outputting the third control signal;

[0033] A fourth inverter is connected to the output end of the delayer, and the output end of the fourth inverter outputs the fourth control signal.

[0034] The RC oscillator circuit of the present invention, the clock generation module further includes:

[0035] a sixth switch tube, controllably connected between the output end of the buffer module and the second input end under the action of the second control signal;

[0036] a seventh switch tube, controllably connected between the output end of the buffer module and the first input end under the action of the first control signal;

[0037] A third capacitor connected between the first input terminal and the ground terminal;

[0038] The fourth capacitor is connected between the second input terminal and the ground terminal.

[0039] In the RC oscillator circuit described in the present invention, in a first state, the second control signal and the fourth control signal are set high, and the first control signal and the third control signal are set low; in a second state, the second control signal and the fourth control signal are set low, and the first control signal and the third control signal are set high.

[0040] In the RC oscillator circuit of the present invention, in a first state, the charge of the fourth capacitor is transferred to the second capacitor; in a second state, the charge of the third capacitor is transferred to the first capacitor.

[0041] Beneficial effects: The present invention provides a low-temperature drift RC oscillator circuit, which generates a current and a reference voltage that do not change with temperature through a reference current module. The working state of the clock generation module is switched under the action of a switching timing signal to offset the voltage drift generated by circuit matching. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a circuit schematic diagram of an RC oscillator circuit according to an embodiment of the present invention;

[0043] Figure 2 It is a circuit operation waveform diagram of the RC oscillator circuit of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0046] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0047] Reference Figure 1 The present invention provides an RC oscillator circuit, comprising:

[0048] A reference current module 1 provides a reference current I1 and a reference voltage Vref;

[0049] A buffer module 2, wherein an input end of the buffer module 2 is connected to the reference current module 1;

[0050] The clock generating module 3 is connected to the reference current module 1 and the buffer module 2, and outputs a clock signal CLK under the action of a set of switch timing signals.

[0051] The present invention provides a low-temperature drift RC oscillator circuit, which generates a reference current and a reference voltage that do not change with temperature through a reference current module, and switches the working state under the action of a switch timing signal to offset the voltage drift generated by circuit matching.

[0052] In a preferred embodiment of the present invention, the reference current module 1 comprises:

[0053] A first PMOS transistor PM2 is connected between a power supply voltage VDD and a first reference node X1, and a gate electrode and a drain electrode of the first PMOS transistor PM2 are connected;

[0054] The first switch tube M1 is controllably connected to the first reference node X1 and the second reference node X2 under the control of a constant temperature voltage VBG, and the second reference node K2 outputs a reference voltage Vref;

[0055] The variable resistor R is connected between the second reference node X2 and the ground terminal.

[0056] The present invention generates a constant temperature reference current I1 by using a first switch tube M1 and a variable resistor R through an externally provided constant temperature voltage VBG. The reference current I1 and the constant temperature voltage VBG have the following relationship:

[0057] Among them, Vref=I1*R, Vref is the reference voltage, which is generated by the constant temperature variable resistor R and the constant temperature current I1, so Vref is also a constant temperature voltage. The variable resistor R is a programmable resistor, so the frequency consistency problem can be calibrated by changing the resistor, and the reference voltage Vref can be adjusted by the variable resistor to solve the oscillator consistency problem caused by process deviation.

[0058] In a preferred embodiment of the present invention, the buffer module 2 includes a buffer AMPBUF, and the buffer AMPBUF includes:

[0059] Positive input terminal, connected to reference voltage Vref;

[0060] The inverting input terminal is connected to the output terminal of the buffer AMPBUF.

[0061] In a preferred embodiment of the present invention, the clock generation module 3 includes:

[0062] A second PMOS transistor PM3, wherein a gate of the second PMOS transistor PM3 is connected to the first reference node X1, a Vbias voltage is provided for the second PMOS transistor PM3, and a source of the second PMOS transistor PM3 is connected to a power supply voltage VDD;

[0063] The third PMOS transistor PM0 is controllably connected between the drain of the second PMOS transistor PM3 and the third reference node X3 under the action of a first control signal φ9;

[0064] The fourth PMOS transistor PM1 is controllably connected between the drain of the second PMOS transistor PM3 and the fourth reference node X4 under the action of a second control signal φ8;

[0065] The second switch tube M4 is controllably connected between the third reference node X3 and a first input terminal Vin of a comparator CMP under the action of a second control signal φ8;

[0066] The third switch tube M5 is controllably connected between the fourth reference node X4 and the second input terminal Vip of the comparator CMP under the action of the first control signal φ9.

[0067] The present invention realizes that the starting frequency meets the wide voltage application through the current mirroring of the first PMOS tube PM2 and the second PMOS tube PM3, and the relationship between the mirror current and the reference voltage. The current I0 generated on the second PMOS tube PM3 and the reference current I1 have the following relationship: I0=N*I1.

[0068] In a preferred embodiment of the present invention, the switch timing signal is generated by a switch timing generation module 4, and the switch timing generation module 4 includes:

[0069] A first inverter is connected to the output terminal Vout of the clock generating module 3, and the first inverter outputs a first control signal φ9;

[0070] A second inverter is connected to the output end of the first inverter, and the second inverter outputs a second control signal φ8;

[0071] The third inverter is connected to the output end of the second inverter, and the third inverter outputs a clock signal CLK.

[0072] In a preferred embodiment of the present invention, the clock generation module 3 includes:

[0073] The fourth switch tube M2 is controllably connected between the third reference node X3 and the ground terminal under the action of a third control signal φ3;

[0074] A first capacitor C10 is connected in parallel with the fourth switch tube M2;

[0075] The fifth switch tube M3 is controllably connected between the fourth reference node X4 and the ground terminal under the action of a fourth control signal φ2;

[0076] The second capacitor C11 is connected in parallel with the fifth switch tube M3.

[0077] In a preferred embodiment of the present invention, the switch timing generation module 4 further includes:

[0078] The delay device Td1 is connected to the output end of the first inverter, and the delay device Td1 outputs a third control signal φ3;

[0079] The fourth inverter is connected to the output end of the delayer Td1 , and the output end of the fourth inverter outputs a fourth control signal φ2 .

[0080] In a preferred embodiment of the present invention, the clock generation module 3 further includes:

[0081] The sixth switch tube M6 is controllably connected between the output terminal of the buffer AMPBUF and the second input terminal Vip under the action of the second control signal φ8;

[0082] The seventh switch tube M7 is controllably connected between the output terminal of the buffer AMPBUF and the first input terminal Vin under the action of the first control signal φ9;

[0083] A third capacitor C0 is connected between the first input terminal Vin and the ground terminal;

[0084] The fourth capacitor C1 is connected between the second input terminal Vip and the ground terminal.

[0085] The present invention provides a reference voltage to the comparator CMP in a time-sharing manner through the buffer AMPBUF, which can solve the problem that the voltage drift caused by the process deviation affects the oscillator frequency. In order to obtain a rectangular wave with a duty cycle of 50%, the third capacitor C0 / fourth capacitor C1 and the current connected to the two ends of the comparator CMP input need to be the same and strictly symmetrical.

[0086] Combination Figure 2 , the working process of the present invention is:

[0087] The first state: the second control signal φ8 and the fourth control signal φ2 are set high, the first control signal φ9 and the third control signal φ3 are set low, at this time, the fifth switch tube M3, the second switch tube M4, the sixth switch tube M6, and the third PMOS tube PM0 are closed, and the fourth PMOS tube PM1, the fourth switch tube M2, the seventh switch tube M7, and the third switch tube M5 are disconnected, the fourth capacitor C1 and the first capacitor C10 are charged, the second capacitor C11 is discharged, and the charge of the third capacitor C0 is transferred to the first capacitor C10. The charges of the fourth capacitor C1 and the first capacitor C10 have the following relationship: Qc1=Vref*C1, Qc10=I0*T / 2+Qc0; the first input terminal Vin and the second input terminal Vip of the comparator CMP have the following relationship: Vin=Vref,

[0088]

[0089] The second state: the second control signal φ8 and the fourth control signal φ2 are set low, the first control signal φ9 and the third control signal φ3 are set high, at this time, the fifth switch tube M3, the second switch tube M4, the sixth switch tube M6, and the third PMOS tube PM0 are disconnected, and the fourth PMOS tube PM1, the fourth switch tube M2, the seventh switch tube M7, and the third switch tube M5 are closed, the third capacitor C0 and the second capacitor C11 are charged, the first capacitor C10 is discharged, and the charge of the fourth capacitor C1 is transferred to the second capacitor C11. The charges of the fourth capacitor C1 and the first capacitor C10 have the following relationship: Qc1=Vref*C0, Qc11=I0*T / 2+Qc1; the first input terminal Vin and the second input terminal Vip of the comparator CMP have the following relationship: Vip=Vref,

[0090] Because it is positive feedback, the fifth switch tube M3, the second switch tube M4, the sixth switch tube M6, the third PMOS tube PM0, the fourth PMOS tube PM1, the fourth switch tube M2, the seventh switch tube M7, and the third switch tube M5 are continuously opened and closed to complete the oscillation. Qc1 and Qc2 use pre-charging technology to store the reference voltage in the capacitors at both ends of the second input terminal Vip\the first input terminal Vin during the oscillation process. Therefore, there are two states in the oscillation process: in the first state, the charge of the fourth capacitor C1 is transferred to the second capacitor C11; in the second state, the charge of the third capacitor C0 is transferred to the first capacitor C10; these two states can store the voltage drift generated by the circuit matching on the third capacitor C0\the fourth capacitor C1, and then transfer the charge to the first capacitor C10\the second capacitor C11, which can offset the voltage drift, the current I0=N*I1, and the reference voltage Vref=I1*R. In the first state, when Vin>Vip, the state machine will be adjusted to the second state until Vin<Vip, and then it will be adjusted to the first state, and the oscillation will be realized in a reciprocating manner, and the frequency is:

[0091] When the voltage across the third capacitor C0 reaches the reference voltage Vref, a delay Td must pass before the comparator responds and the output level changes. Td is the transmission delay of the comparator.

[0092] The present invention provides a low-temperature drift RC oscillator circuit, which generates a reference current and a reference voltage that do not change with temperature through a reference current module, and switches the working state under the action of a switch timing signal to offset the voltage drift generated by circuit matching, thereby solving the problems of the prior art RC oscillator circuit that the output changes greatly with temperature and voltage, the power consumption is high, and the output frequency is inaccurate.

[0093] Through the description and drawings, typical embodiments of the specific structures of the specific implementation methods are given, and other transformations can be made based on the spirit of the present invention. Although the above invention proposes the existing preferred embodiments, these contents are not intended to be limiting.

[0094] For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention.

Claims

1. An RC oscillator circuit, characterized in that: include: A reference current module provides a reference current and a reference voltage; A buffer module, an input end of which is connected to the reference current module; The clock generating module is connected to the reference current module and the buffer module, and outputs a clock signal under the action of a set of switch timing signals.

2. The RC oscillator circuit according to claim 1, characterized in that: The reference current module comprises: A first PMOS tube is connected between a power supply voltage and a first reference node, and a gate electrode and a drain electrode of the first PMOS tube are connected; A first switch tube, controllably connected to the first reference node and a second reference node under the control of a constant temperature voltage, wherein the second reference node outputs the reference voltage; The variable resistor is connected between the second reference node and the ground terminal.

3. The RC oscillator circuit according to claim 1, characterized in that: The buffer module includes a buffer, and the buffer includes: A non-inverting input terminal connected to the reference voltage; The inverting input terminal is connected to the output terminal of the buffer.

4. The RC oscillator circuit according to claim 2, characterized in that: The clock generation module comprises: a second PMOS transistor, wherein a gate of the second PMOS transistor is connected to the first reference node, and a source of the second PMOS transistor is connected to the power supply voltage; a third PMOS transistor, controllably connected between the drain of the second PMOS transistor and a third reference node under the action of a first control signal; a fourth PMOS transistor, controllably connected between the drain of the second PMOS transistor and a fourth reference node under the action of a second control signal; A second switch tube, controllably connected between the third reference node and a first input terminal of a comparator under the action of a second control signal; The third switch tube is controllably connected between the fourth reference node and the second input terminal of the comparator under the action of the first control signal.

5. The RC oscillator circuit according to claim 4, characterized in that: The switch timing signal is generated by a switch timing generation module, and the switch timing generation module includes: A first inverter, connected to the output end of the clock generating module, the first inverter outputs the first control signal; A second inverter, connected to an output end of the first inverter, the second inverter outputting the second control signal; The third inverter is connected to the output end of the second inverter.

6. The RC oscillator circuit according to claim 4, characterized in that: The clock generation module comprises: a fourth switch tube, controllably connected between the third reference node and the ground terminal under the action of a third control signal; A first capacitor connected in parallel with the fourth switch tube; a fifth switch tube, controllably connected between the fourth reference node and the ground terminal under the action of a fourth control signal; The second capacitor is connected in parallel with the fifth switch tube.

7. The RC oscillator circuit according to claim 6, characterized in that: The switch timing generation module also includes: A delayer connected to the output end of the first inverter, the delayer outputting the third control signal; A fourth inverter is connected to the output end of the delayer, and the output end of the fourth inverter outputs the fourth control signal.

8. The RC oscillator circuit according to claim 6, characterized in that: The clock generation module also includes: a sixth switch tube, controllably connected between the output end of the buffer module and the second input end under the action of the second control signal; a seventh switch tube, controllably connected between the output end of the buffer module and the first input end under the action of the first control signal; A third capacitor connected between the first input terminal and the ground terminal; The fourth capacitor is connected between the second input terminal and the ground terminal.

9. The RC oscillator circuit according to claim 6, characterized in that: In the first state, the second control signal and the fourth control signal are set high, and the first control signal and the third control signal are set low. In the second state, the second control signal and the fourth control signal are set low, and the first control signal and the third control signal are set high.

10. The RC oscillator circuit according to claim 8, characterized in that: In the first state, the charge of the fourth capacitor is transferred to the second capacitor; in the second state, the charge of the third capacitor is transferred to the first capacitor.

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