A power-on reset circuit with hysteresis effect

Abstract

The present invention discloses a power-on reset circuit with a hysteresis effect. The power-on reset circuit with a hysteresis effect can set the conduction voltages of the NMOS transistors in the pre-stage circuit, the comparison inverter circuit, and the control circuit, and through the control circuit, during the power-on process, as the power supply voltage gradually increases and the PMOS transistor of the first inverter conducts, the output power supply of the first inverter gradually increases until the output voltage of the first inverter is greater than the conduction voltage of the NMOS transistor of the second inverter, completing the power-on; and during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases until the output voltage of the first inverter is less than the conduction voltage of the NMOS transistor of the second inverter, completing the power-off.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular, to a power-on reset circuit with a hysteresis effect. Background Art

[0002] The power-on reset circuit generally plays a role of low-effective global reset in integrated circuits and systems. This circuit generates a low-effective logic signal affected by the power supply voltage (VDD) of the circuit system, that is, the reset signal (RSTN), and controls other modules in the circuit system to perform global reset.

[0003] The power-on reset circuit can set its upper and lower threshold points, so that other modules of the circuit system always work within the normal range of the power supply voltage, avoiding the problem that the circuit system does not work properly due to too low power supply voltage.

[0004] Therefore, how to design and use the power-on reset circuit has become an important research direction for those skilled in the art in the field of electronic technology. Summary of the Invention

[0005] The present invention provides a power-on reset circuit with a hysteresis effect. Specifically, the present invention provides the following technical solutions:

[0006] A power-on reset circuit with a hysteresis effect includes: a pre-circuit, a comparison inverter circuit, and a control circuit;

[0007] The input end of the pre-circuit is connected to the power supply, and the output end of the pre-circuit is connected to the comparison inverter circuit, for providing an output voltage to the comparison inverter circuit;

[0008] The comparison inverter circuit includes a first inverter and a second inverter. The first input end of the first inverter is connected to the output end of the pre-circuit; the second input end of the first inverter is connected to the power supply; the output end of the first inverter is connected to the first input end of the second inverter; the second input end of the second inverter is connected to the power supply; the comparison inverter circuit is used for outputting a first reset signal based on the voltage output by the pre-circuit and the power supply voltage;

[0009] The first input end of the control circuit is connected to the output end of the pre-circuit; the second input end of the control circuit is connected to the output end of the first inverter; the third input end of the control circuit is connected to the output end of the second inverter;

[0010] The control circuit is configured to, during the power-on process, as the power supply voltage gradually increases and the PMOS transistor of the first inverter conducts, cause the output power supply of the first inverter to gradually increase until the output voltage of the first inverter is greater than the turn-on voltage of the NMOS transistor of the second inverter, completing the power-on; and during the power-off process, as the power supply voltage gradually decreases, cause the output voltage of the second inverter to gradually increase and the output voltage of the first inverter to gradually decrease until the output voltage of the first inverter is less than the turn-on voltage of the NMOS transistor of the second inverter, completing the power-off.

[0011] In an alternative embodiment of the present application, the pre-stage circuit includes: a first NMOS transistor and a first resistor;

[0012] The drain of the first NMOS transistor is connected to one end of the first resistor and the gate of the first NMOS transistor respectively; the other end of the first resistor is connected to the power supply; the source of the first NMOS transistor is grounded; wherein, the drain of the first NMOS transistor serves as an output terminal to provide an output voltage to the comparison inverter circuit.

[0013] In an alternative embodiment of the present application, the first inverter includes a first PMOS transistor and a second NMOS transistor;

[0014] The gate of the first PMOS transistor and the gate of the second NMOS transistor are connected and serve as the first input terminal of the first inverter to be connected to the output terminal of the pre-stage circuit;

[0015] The source of the first PMOS transistor serves as the second input terminal of the first PMOS transistor to be connected to the power supply;

[0016] The drain of the first PMOS transistor and the drain of the second NMOS transistor are connected and serve as the output terminal of the first inverter to be connected to the input terminal of the second inverter; the source of the second NMOS transistor is grounded.

[0017] In an alternative embodiment of the present application, the second inverter includes: a second PMOS transistor and a fifth NMOS transistor;

[0018] The gate of the second PMOS transistor and the gate of the fifth NMOS transistor are connected and serve as the first input terminal of the second inverter to be connected to the output terminal of the first inverter;

[0019] The source of the second PMOS transistor serves as the second input terminal of the second PMOS transistor to be connected to the power supply;

[0020] The drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor and serves as the output terminal of the second inverter; the source of the fifth NMOS transistor is grounded.

[0021] In an alternative embodiment of the present application, the control circuit includes: a third NMOS transistor and a fourth NMOS transistor;

[0022] The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the gate of the third NMOS transistor is connected to the first input terminal of the first inverter and the output terminal of the pre-stage circuit respectively; the drain of the third NMOS transistor is connected to the output terminal of the first inverter and the first input terminal of the second inverter respectively;

[0023] The gate of the fourth NMOS transistor is connected to the output terminal of the second inverter; the source of the fourth NMOS transistor is grounded.

[0024] In an alternative embodiment of the present application, the pre-stage circuit includes a first NMOS transistor;

[0025] The relationship between the conduction voltages of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor is:

[0026] V TH4 <V TH3 <V TH1 <V TH2 <<V TH5 ;

[0027] Wherein, V TH4 represents the conduction voltage of the fourth NMOS transistor; V TH3 represents the conduction voltage of the third NMOS transistor; V TH1 represents the conduction voltage of the first NMOS transistor; V TH2 represents the conduction voltage of the second NMOS transistor; V TH5 represents the conduction voltage of the fifth NMOS transistor.

[0028] In an alternative embodiment of the present application, it further includes:

[0029] an output filtering circuit;

[0030] The input terminal of the output filtering circuit is connected to the output terminal of the comparison inverter circuit for receiving the first reset signal and performing hysteresis output on the first reset signal.

[0031] In an alternative embodiment of the present application, the output filtering circuit includes:

[0032] The third inverter, the fourth inverter, the fifth inverter, the first capacitor, and the AND operation module;

[0033] The input terminal of the third inverter serves as the input terminal of the output filtering circuit and is connected to the output terminal of the second inverter; the output terminal of the third inverter is respectively connected to the first input terminal of the AND operation module and the input terminal of the fourth inverter;

[0034] The output terminal of the fourth inverter is respectively connected to the input terminal of the fifth inverter and one end of the first capacitor; the other end of the first capacitor is grounded;

[0035] The output terminal of the fifth inverter is connected to the second input terminal of the AND operation module.

[0036] Compared with the prior art, the power-on reset circuit with hysteresis effect provided by the present invention can set the conduction voltages of the NMOS transistors in the pre-stage circuit, the comparison inverter circuit, and the control circuit, and through the control circuit, during the power-on process, as the power supply voltage gradually increases and the PMOS transistor of the first inverter conducts, the output power supply of the first inverter gradually increases until the output voltage of the first inverter is greater than the conduction voltage of the NMOS transistor of the second inverter, completing the power-on; and during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases until the output voltage of the first inverter is less than the conduction voltage of the NMOS transistor of the second inverter, completing the power-off. The power-on reset circuit with hysteresis effect can realize the hysteresis effect of the power-on reset circuit during the power-on process and the power-off process, and can provide a new research idea for the power-on reset circuit in the field of electronic technology. Description of the Drawings

[0037] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0038] Figure 1 is the power-on reset circuit structure with hysteresis effect provided by the embodiment of the present application Figure 1 ;

[0039] Figure 2 is the power-on reset circuit structure with hysteresis effect provided by the embodiment of the present application Figure 2 ;

[0040] Figure 3 is the schematic diagram of the behavior of the reset signal during the power-on and power-off processes provided by the embodiment of the present application. Detailed Embodiments

[0041] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0042] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0043] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is two or more, unless otherwise specifically defined. The meaning of "several" is one or more, unless otherwise specifically defined.

[0044] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0045] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0046] The power-on reset circuit generally plays a role of low-effective global reset in integrated circuits and systems. The circuit generates a low-effective logic signal affected by the power supply voltage (VDD) of the circuit system, that is, the reset signal (RSTN), and controls other modules in the circuit system to perform global reset.

[0047] The power-on reset circuit can set the upper and lower threshold points, enabling other modules of the circuit system to always operate within the normal range of the power supply voltage, thus avoiding the problem of abnormal operation of the circuit system caused by too low power supply voltage.

[0048] Therefore, how to design and use the power-on reset circuit has become an important research direction for those skilled in the art in the field of electronic technology.

[0049] To solve the above technical problems, this application provides a power-on reset circuit with a hysteresis effect. Please refer to Figure 1 , Figure 1 which is the structure of the power-on reset circuit with a hysteresis effect provided by the embodiments of this application. Figure 1 .

[0050] As Figure 1 shown, the power-on reset circuit with a hysteresis effect includes: a pre-stage circuit 101, a comparison and inverter circuit 102, a control circuit 103, and an output filtering circuit 104;

[0051] The input end of the pre-stage circuit 101 is connected to the power supply, and the output end is connected to the comparison and inverter circuit 102, for providing an output voltage to the comparison and inverter circuit 102.

[0052] The comparison and inverter circuit 102 includes: a first inverter 1021 and a second inverter 1022.

[0053] Among them, the first input end of the first inverter 1021 is connected to the output end of the pre-stage circuit 101; the second input end of the first inverter 1021 is connected to the power supply; the output end of the first inverter 1021 is connected to the first input end of the second inverter 1022; the second input end of the second inverter 1022 is connected to the power supply; the output end of the second inverter 1022 is connected to the output filtering circuit; the comparison and inverter circuit is used to output a first reset signal based on the voltage output by the pre-stage circuit and the power supply voltage;

[0054] The first input end of the control circuit 103 is connected to the output end of the pre-stage circuit 101; the second input end of the control circuit 103 is connected to the output end of the first inverter 1021; the third input end of the control circuit 103 is connected to the output end of the second inverter 1022.

[0055] The control circuit 103 is used to gradually increase the output power supply of the first inverter 1021 as the power supply voltage gradually increases and the PMOS transistor of the first inverter 1021 conducts during the power-on process, until the output voltage of the first inverter 1021 is greater than the conduction voltage of the NMOS transistor of the second inverter 1022, completing the power-on; and during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter 1022 gradually increases and the output voltage of the first inverter 1021 gradually decreases, until the output voltage of the first inverter 1021 is less than the conduction voltage of the NMOS transistor of the second inverter 1022, completing the power-off.

[0056] The input end of the output filtering circuit 104 is connected to the output end of the comparison inverter circuit 102, and is used to receive the first reset signal and filter and output the first reset signal.

[0057] Specifically, please refer to Figure 2 , Figure 2 the power-on reset circuit structure with hysteresis effect provided by the embodiments of the present application Figure 2 .

[0058] As Figure 2 shown, the pre-stage circuit 101 includes: a first NMOS transistor (hereinafter referred to as NMOS1) and a first resistor R1.

[0059] Among them, the drain of NMOS1 is respectively connected to one end of the first resistor R1 and the gate of NMOS1; the other end of the first resistor R1 is connected to the power supply VDD; the source of NMOS1 is grounded; the drain of NMOS1 serves as the output end to provide the output voltage to the comparison inverter circuit.

[0060] The first inverter 1021 includes a first PMOS transistor (hereinafter referred to as PMOS1) and a second NMOS transistor (hereinafter referred to as NMOS2).

[0061] Among them, the gates of PMOS1 and NMOS2 are connected and serve as the first input end of the first inverter 1021 and are connected to the output end of the pre-stage circuit;

[0062] The source of PMOS1 serves as the second input end of PMOS1 and is connected to the power supply (VDD).

[0063] The drains of PMOS1 and NMOS2 are connected and serve as the output end of the first inverter 1021 and are connected to the input end of the second inverter 1022; the source of NMOS2 is grounded.

[0064] Similar to the first inverter 1021, the second inverter includes: a second PMOS transistor (hereinafter referred to as PMOS2) and a fifth NMOS transistor (hereinafter referred to as NMOS5).

[0065] The gate of PMOS2 is connected to the gate of NMOS5 and is connected to the output terminal of the first inverter 1021 as the first input terminal of the second inverter;

[0066] The source of PMOS2 is connected to the power supply (VDD) as the second input terminal of PMOS2;

[0067] The drain of PMOS2 is connected to the drain of NMOS5 and is connected to the input terminal of the output filtering circuit as the output terminal of the second inverter 1022; the source of NMOS5 is grounded.

[0068] Furthermore, the control circuit includes: a third NMOS transistor (hereinafter referred to as NMOS3) and a fourth NMOS transistor (hereinafter referred to as NMOS4).

[0069] Among them, the source of NMOS3 is connected to the drain of NMOS4; the gate of NMOS3 is respectively connected to the first input terminal of the first inverter 1021 and the output terminal of the pre-stage circuit; the drain of NMOS3 is respectively connected to the output terminal of the first inverter 1021 and the input terminal of the first inverter 1021.

[0070] The gate of NMOS4 is respectively connected to the output terminal of the second inverter 1022 (i.e., the drain of PMOS2 and the drain of NMOS2) and the input terminal of the output filtering circuit 104; the source of NMOS4 is grounded.

[0071] Output filtering circuit 104: includes a third inverter (such as Figure 2 the shown INV1), a fourth inverter (such as Figure 2 the shown INV2), a fifth inverter (such as Figure 2 the shown INV3), a first capacitor C1, and an AND operation model (such as Figure 2 the shown AND).

[0072] Among them, the input terminal of the third inverter is connected to the output terminal of the second inverter (i.e., the drain of PMOS2 and the drain of NMOS2) as the input terminal of the output filtering circuit; the output terminal of the third inverter is respectively connected to the input terminal of the fourth inverter and the first input terminal of the AND operation module.

[0073] The output terminal of the fourth inverter is respectively connected to the input terminal of the fifth inverter and one end of the first capacitor C1; the other end of the first capacitor C1 is grounded.

[0074] The output terminal of the fifth inverter is connected to the second input terminal of the AND operation module.

[0075] Furthermore, the turn-on voltages of NMOS1, NMOS2, NMOS3, NMOS4, and NMOS5 are as follows:

[0076] V TH4 <V TH3 <V TH1 <V TH2 <<V TH5 ;

[0077] Among them, V TH4 represents the turn-on voltage of the fourth NMOS transistor; V TH3 represents the turn-on voltage of the third NMOS transistor; V TH1 represents the turn-on voltage of the first NMOS transistor; V TH2 represents the turn-on voltage of the second NMOS transistor; V TH5 represents the turn-on voltage of the fifth NMOS transistor.

[0078] First, for the convenience of understanding the working principle of the power-on reset circuit with hysteresis effect provided by the embodiments of the present application, first, the power-on process and the power-off process of the power-on reset circuit will be described in detail.

[0079] Please refer to Figure 3 , Figure 3 , which is a schematic diagram of the behavior of the reset signal during the power-on and power-off processes provided by the embodiments of the present application.

[0080] As Figure 3 shown, for the power-on reset circuit, as time (Time) goes by, during the process of the power supply voltage VDD rising from 0 to the normal operating voltage of the circuit system, only when the power supply voltage VDD is higher than the power-on threshold V PORR of the power-on reset circuit, the reset signal RSTN changes from logic 0 (Logic0) to logic 1 (Logic1). After other modules of the circuit system receive this signal, the global reset ends and normal operation starts.

[0081] During the process of the power supply voltage VDD dropping from the normal voltage to 0, only when the power supply voltage VDD is lower than the power-off threshold V PORF of the power-on reset circuit, the reset signal RSTN changes from logic 1 to logic 0, and other modules in the circuit system perform a global reset after receiving this signal.

[0082] For the power-on reset circuit as Figure 2 shown, set the output voltage of the pre-stage circuit as V1, the output voltage of the first inverter as V2, the voltage of the second inverter as V4, the voltage between the drain of NMOS4 and the source of NMOS3 as V3, the output voltage of the third inverter as V5 (i.e., the input voltage of the first input terminal of the AND operation module is set as V5), and the input voltage of the second input terminal of the AND operation module as V6.

[0083] During the power-on process, when the power supply voltage VDD is greater than 0 and less than V TH4 , NMOS1 to NMOS4 are all in the off state. At this time, the node voltage of V1 is equal to VDD.

[0084] In this case, since the voltage value of VDD is too small to turn on PMOS1, there is a small leakage current in NMOS2. Therefore, the node voltage of V2 is between 0 and VDD and is closer to 0. Further, for PMOS2 and NMOS5, the two form an inverter. Therefore, the leakage current of PMOS2 makes the node voltage of V4 between 0 and VDD and closer to VDD.

[0085] During this process, in order to avoid the influence of the V2 node voltage on the subsequent circuit reset, the fourth inverter, the fifth inverter, and the capacitor C1 are used to generate V6 (the potential of V6 is 0) with a time delay, and the potential of V6 (0) and the potential of V5 (0) are input into the AND operation module together, so that the reset signal of the data of the AND operation module is 0.

[0086] As the power supply voltage VDD continues to increase, when VDD is in the range of V TH4 to V TH2 , since the gate and drain of NMOS1 are connected, in this case, the node voltage of V1 is equal to the conduction voltage of NMOS1, that is, V1 = V TH1 . During this process, the leakage current of NMOS2 gradually increases, and PMOS1 is not conducting. The node voltage of V2 is pulled down to ground by NMOS2. In this state, the node voltage of V2 is 0. For PMOS2 and NMOS5, when the node voltage of V2 is 0, PMOS2 conducts and NMOS5 turns off. The node voltage of V4 is pulled up to the power supply voltage VDD by PMOS2. Further, for NMOS4, at this time, the gate voltage of NMOS4 is equal to the node voltage of V4, that is, the gate voltage of NMOS4 is equal to the power supply voltage VDD, which is greater than the conduction voltage V TH4 of NMOS4, NMOS4 conducts, and the node voltage of V3 is pulled down to ground; for NMOS3, NMOS3 conducts, but the node voltage of V2 is always 0.

[0087] During this process, the node voltage of V4 is VDD, the potentials of V5 and V6 received by the AND operation module are both 0, and the reset signal output by the AND operation is still 0.

[0088] As the power supply voltage VDD continues to increase, since the node voltage of V1 is always equal to V TH1 (that is, the gate voltages of NMOS2 and PMOS1 are always equal to V TH1) and since VTH4 is less than VTH3. Therefore, the pull-down current flowing through NMOS3 and NMOS4 will no longer increase with the increase of VDD. During this process, the leakage current of POMS1 gradually conducts as the power supply voltage VDD increases, and the node voltage of V2 gradually rises.

[0089] When the node voltage of V2 gradually rises to V2 greater than V TH5 In this case, NMOS5 conducts, and the node voltage of V4 will be pulled down as NMOS5 conducts until the node voltage of V4 is less than V TH4 , NMOS4 turns off. In this case, the voltage of V3 will rise, and NMOS3 remains in a weak-on state until the power supply voltage VDD is equal to the power-on threshold V PORR of the power-on reset circuit. In this state, the node voltage of V2 is equal to the power supply voltage VDD, the node voltage of V4 is equal to 0, and the node voltage of V4 is input to the output filtering circuit, so that the potentials of the first input terminal and the second input terminal of the AND operation module of the output filtering circuit are both 1, and finally a reset signal with an output potential of 1 is output to complete the power-on process of the reset circuit.

[0090] For the power-down process of the power-on reset circuit:

[0091] When the power supply voltage VDD drops from the normal value, the node voltage of V2 decreases as the power supply voltage VDD decreases until the node voltage of V2 is less than V TH5 At this time, the node voltage of V4 rises, NMOS4 and NMOS3 conduct, and the node voltage of V2 is pulled down to 0. At this time, the power supply voltage VDD is equal to the power-down threshold V PORF of the power-on reset circuit. After that, the node voltage of V2 is 0, the node voltage of V4 is equal to the power supply voltage VDD, and the current IPD flowing through NMOS3 and NMOS4 is approximately equal to 0, and the reset signal finally output by the power-on reset circuit remains 0.

[0092] Based on the description of the power-on process and the power-down process of the power-on reset circuit with hysteresis effect described above, it can be seen that the reset voltage of the power-on reset circuit is determined by V1, V2, and V TH5 The power consumption of the power-on reset circuit during operation is determined by the first resistor R1 of the pre-stage circuit and V TH1 . In an alternative embodiment of the present application, the resistance value of R1 is about 10 Mohm. In a typical application scenario where VDD = 3.3V, the static current of the power-on reset circuit is less than 0.5 μA.

[0093] Furthermore, the hysteresis function of the power-on reset circuit is determined by the node voltage of V2 reaching the power-on threshold V PORR and the power-down threshold V PORFIt is determined by the difference between the corresponding power supply voltage VDD. During the power-on process, when the node voltage of V2 is equal to V TH5 the current flowing through NMOS3 and NMOS4 is limited to a constant pull-down current (IPD); during the power-off process, if the node voltage of V2 is equal to V TH5 the pull-down current flowing through NMOS3 and NMOS4 is approximately equal to 0.

[0094] Therefore, with the pull-up ability of PMOS1 unchanged, during the power-on process, the power supply voltage corresponding to when the node voltage of V2 is equal to V TH5 is greater than the power supply voltage corresponding to when the node voltage of V2 is equal to V during the power-off process TH5 that is, V PORR >V PORF .

[0095] In the embodiment of the present application, the hysteresis of the power-on reset circuit is mainly affected by the magnitude of the current of IPD, that is, affected by V1 = V TH1 and the size of NMOS3; the larger the IPD, the more obvious the hysteresis. Therefore, the IPD should not be too large. If it exceeds the pull-up ability of PM1, V2 will always be pulled down to 0, and RSTN will be locked at 0, resulting in functional failure. When the IPD is within a reasonable range and the size of NMOS3 is increased to increase the hysteresis, it should be ensured that NMOS3 and NMOS4 are adjusted proportionally so that the IPD is always limited by NMOS3 to prevent the current determined by NMOS4 from being too large when VDD is too high, causing V2 to be always pulled low.

[0096] In summary, the power-on reset circuit with hysteresis effect provided by the present application can set the conduction voltages of the NMOS transistors in the pre-circuit, the comparison inverter circuit, and the control circuit, and through the control circuit, during the power-on process, as the power supply voltage gradually increases and the PMOS transistor of the first inverter conducts, the output power supply of the first inverter gradually increases until the output voltage of the first inverter is greater than the conduction voltage of the NMOS transistor of the second inverter, completing the power-on; and during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases until the output voltage of the first inverter is less than the conduction voltage of the NMOS transistor of the second inverter, completing the power-off. The power-on reset circuit with hysteresis effect can realize the hysteresis effect of the power-on reset circuit during the power-on process and the power-off process, and can provide a new research idea for the power-on reset circuit in the field of electronic technology.

[0097] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A power-on reset circuit with hysteresis effect, characterized in that: include: Preamplifier circuit, comparison inversion circuit, control circuit; The input end of the preamplifier circuit is connected to a power supply, and the output end of the preamplifier circuit is connected to the comparison inversion circuit, so as to provide an output voltage to the comparison inversion circuit; The comparison inverting circuit comprises a first inverter and a second inverter, wherein the first input end of the first inverter is connected to the output end of the preamplifier circuit; the second input end of the first inverter is connected to the power supply; the output end of the first inverter is connected to the first input end of the second inverter; and the second input end of the second inverter is connected to the power supply; The comparison inversion circuit is used to output a first reset signal based on the voltage output by the preamplifier circuit and the power supply voltage; The first input terminal of the control circuit is connected to the output terminal of the preamplifier circuit; the second input terminal of the control circuit is connected to the output terminal of the first inverter; the third input terminal of the control circuit is connected to the output terminal of the second inverter; The control circuit is used for gradually increasing the output voltage of the first inverter during the power-on process as the power supply voltage gradually increases and the PMOS tube of the first inverter is turned on, until the output voltage of the first inverter is greater than the turn-on voltage of the NMOS tube of the second inverter, thereby completing the power-on process; And during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases, until the output voltage of the first inverter is less than the conduction voltage of the NMOS tube of the second inverter, and the power-off is completed.

2. The power-on reset circuit with hysteresis effect according to claim 1, characterized in that: The front-end circuit includes: a first NMOS tube and a first resistor; The drain of the first NMOS tube is respectively connected to one end of the first resistor and the gate of the first NMOS tube; the other end of the first resistor is connected to the power supply; the source of the first NMOS tube is grounded; wherein the drain of the first NMOS tube serves as an output end to provide an output voltage to the comparison inverting circuit.

3. The power-on reset circuit with hysteresis effect according to claim 1, characterized in that: The first inverter includes a first PMOS tube and a second NMOS tube; The gate of the first PMOS tube is connected to the gate of the second NMOS tube, and is connected to the output end of the preamplifier circuit as the first input end of the first inverter; The source of the first PMOS tube is connected to the power supply as the second input end of the first PMOS tube; The drain of the first PMOS tube is connected to the drain of the second NMOS tube, and is connected to the input of the second inverter as the output of the first inverter; the source of the second NMOS tube is grounded.

4. The power-on reset circuit with hysteresis effect according to claim 3, characterized in that: The second inverter includes: a second PMOS tube and a fifth NMOS tube; The gate of the second PMOS tube is connected to the gate of the fifth NMOS tube, and is connected to the output end of the first inverter as the first input end of the second inverter; The source of the second PMOS tube is connected to the power supply as the second input end of the second PMOS tube; The drain of the second PMOS tube is connected to the drain of the fifth NMOS tube and serves as the output end of the second inverter; the source of the fifth NMOS tube is grounded.

5. The power-on reset circuit with hysteresis effect according to claim 4, characterized in that: The control circuit comprises: a third NMOS tube and a fourth NMOS tube; The source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the third NMOS tube is respectively connected to the first input end of the first inverter and the output end of the preamplifier circuit; the drain of the third NMOS tube is respectively connected to the output end of the first inverter and the first input end of the second inverter; The gate of the fourth NMOS tube is connected to the output end of the second inverter; the source of the fourth NMOS tube is grounded.

6. The power-on reset circuit with hysteresis effect according to claim 5, characterized in that: The front circuit includes a first NMOS tube; The relationship between the on-state voltages of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor is: In TH4 <V TH3 <V TH1 <V TH2 < <V TH5 ; Among them, V TH4 represents the on-state voltage of the fourth NMOS tube; V TH3 Represents the on-state voltage of the third NMOS tube; V TH1 Represents the on-state voltage of the first NMOS tube; V TH2 Represents the conduction voltage of the second NMOS tube; V TH5 Represents the on-state voltage of the fifth NMOS tube.

7. The power-on reset circuit with hysteresis effect according to claim 1, characterized in that: Also includes: Output filtering circuit; The input end of the output filtering circuit is connected to the output end of the comparison inversion circuit, and is used to receive the first reset signal and filter and output the first reset signal.

8. The power-on reset circuit with hysteresis effect according to claim 7, characterized in that: The output filtering circuit comprises: A third inverter, a fourth inverter, a fifth inverter, a first capacitor and an AND operation module; The input end of the third inverter is connected to the output end of the second inverter as the input end of the output filter circuit; the output end of the third inverter is connected to the first input end of the AND operation module and the input end of the fourth inverter respectively; The output end of the fourth inverter is connected to the input end of the fifth inverter and one end of the first capacitor respectively; the other end of the first capacitor is grounded; The output terminal of the fifth inverter is connected to the second input terminal of the AND operation module.

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