A domino-type multi-stage interlocking power consumption management circuit

Abstract

The present invention discloses a domino-type multi-stage interlocking power consumption management circuit, which belongs to the field of integrated circuit technology. It mainly solves the problem that traditional energy consumption management chips are difficult to adapt to fluctuations in process, voltage, and temperature, which may cause the problem of chip logic locking failure under special working conditions. The circuit includes a fuse logic generation circuit, a latch matrix, a back-end module, and a power sensing front end, and also includes a multi-stage timing interlocking circuit with a domino effect. The present invention optimizes the concept of power consumption management and locking timing, optimizes and manages power consumption in a multi-stage interlocking manner, abandons the control function of the enable signal, and performs adaptive sequential control in the power supply dimension. It is a supplementary power-on timing management method that ensures effective logic locking while adaptively reducing additional power consumption, and has positive practical significance and practical value.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a domino-type multi-stage interlocking power consumption management circuit. Background Art

[0002] A power management circuit is a hardware design module that optimizes energy efficiency by controlling the power consumption of electronic devices or systems. Its core goals include extending battery life, reducing heat generation, minimizing energy waste, and improving system reliability.

[0003] In the prior art, Figure 1 、 Figure 2 As shown in the figure, the power-on sequence of a traditional energy management chip using fuse trimming technology is usually divided into the following stages:

[0004] Phase 1: Power on and stabilize

[0005] The power management module monitors the voltage to ensure that it reaches a stable threshold and the relevant fuse circuit starts to operate.

[0006] Phase 2: Fuse data reading:

[0007] The fuse logic generation circuit including the fuse array begins to establish the fuse logic. The hardware reads the programmed fuse logic from the fuse array and transmits it to the subsequent module. At the same time, it is decoded into specific control signals, such as reference voltage trim control words, clock selection control words, verification keys, etc.

[0008] Phase 3: Logical lock takes effect

[0009] After the subsequent module updates the working state according to the fuse value, the relevant logic value is locked by the enable signal. At this time, the chip starts to be enabled and enters the working state where the fuse logic value is locked.

[0010] Phase 4: Normal Operation

[0011] The chip enters the preset working mode, and all logical behaviors and control words are constrained by the logic values of the fuse configuration.

[0012] The aforementioned power-up phase introduces inefficient power consumption. After the chip is powered on and the fuse logic is read, the fuse logic decoding circuit and fuse bias circuit continue to operate, regardless of whether the chip is enabled or disabled. The continued activation of the fuse programming circuit causes static power leakage. If the relevant modules are disabled after enabling, the shutdown static power consumption will be high before enabling. If the relevant modules are disabled before enabling and logic establishment is enabled after enabling, the chip will not be able to enter the correct initial logic state after power-up and before enabling, and will also experience high power consumption during operation.

[0013] If the fuse bias circuit and fuse logic generation circuit are turned off, there is a risk of timing competition, which may cause the fuse data latch to fail. If a fixed delay device is used to handle it, it will be difficult to adapt to fluctuations in process, voltage, and temperature, which may cause logic locking failure under special working conditions. Summary of the Invention

[0014] The purpose of the present invention is to provide a domino-type multi-stage interlocking power consumption management circuit, which mainly solves the problem that traditional energy consumption management chips are difficult to adapt to fluctuations in process, voltage, and temperature, which may cause the chip logic locking failure under special working conditions.

[0015] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0016] A domino-type multi-stage interlocking power consumption management circuit includes a fuse logic generation circuit, a latch matrix, a power sensing front end for a subsequent module, and a multi-stage timing interlocking circuit with a domino effect. The power sensing front end monitors the power supply status and generates a starting point control signal through a threshold comparator. The starting point control signal controls the multi-stage timing interlocking circuit to start chain timing. When the timing ends, a fuse logic locking signal is generated to the latch matrix, which locks the fuse logic independently of an enable signal and transmits it to the subsequent module. After the fuse logic locking signal is generated, the chain timing generates a shutdown signal to the fuse logic generation circuit. The shutdown signal is also independent of the enable signal and is used to shut down the fuse logic generation circuit.

[0017] Furthermore, in the present invention, the multi-stage timing interlock circuit includes a fuse logic timing locking circuit and a shutdown signal timing generation circuit; the fuse logic timing locking circuit is composed of a first timing unit and a first driving unit; the shutdown signal timing generation circuit is composed of a second timing unit and a second driving unit.

[0018] Furthermore, in the present invention, when the first timing unit and the second timing unit are digital circuits, the two timing units are composed of a cascade shift register and a timing endpoint monitoring module; when the power sensing front end detects that the power supply has reached the threshold level and flips to a high level, the oscillation clock collects the "high level" information into the cascade shift register, and continuously pushes the "starting point signal" to the subsequent stage through the clock. The oscillation clock cooperates with the cascade length of the cascade shift register, that is, the timing time length. When the "starting point signal" is pushed to the timing endpoint monitoring module, the timing endpoint monitoring module outputs a "secondary timing control" signal to the subsequent stage for relay timing, and at the same time generates a timing shutdown signal to shut down the cascade shift register.

[0019] Furthermore, in the present invention, the timing endpoint monitoring module is composed of four NAND gates N1 to NAND gate N4 and a first RS trigger; wherein, the starting point control signal is input from one input end of the NAND gate N2, the output end of the NAND gate N2 outputs a signal to the NAND gate N4 and one input end of the NAND gate N1, the output end of the NAND gate N4 outputs a signal to the other input end of the NAND gate N2 and the S end of the first RS trigger, the output end of the NAND gate N3 outputs a signal to the other input end of the NAND gate N1, the other input end of the NAND gate N4 and the R end of the first RS trigger, the output end of the NAND gate N1 outputs a signal to one input end of the NAND gate N3, and the other input end of the NAND gate N3 and the third input end of the NAND gate N4 input an oscillation clock signal.

[0020] Furthermore, in the present invention, when the first timing unit is an analog circuit, the first timing unit includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP4 whose gates are connected to each other, an NMOS transistor MN2 and a PMOS transistor MP5 whose gates are connected to the drain of the PMOS transistor MP1, a resistor R1 connected between the source of the NMOS transistor MN1 and the drain of the PMOS transistor MP5, a PMOS transistor MP2 whose source is connected to the source of the PMOS transistor MP4 and whose drain is connected to the drain of the PMOS transistor MP4 and the source of the PMOS transistor MP5, a gate connected to the gate of the PMOS transistor MP2 and whose source is connected to the source of the PMOS transistor MP2. The first driving unit comprises a PMOS transistor MP3 connected thereto, and a capacitor C1 connected between the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN1; wherein the gate and drain of the PMOS transistor MP2 are interconnected, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP4, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1, the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN2 are both connected to the first driving unit, and the source of the PMOS transistor MP3 is connected to VDD.

[0021] Furthermore, in the present invention, the first driving unit includes a first Schmitt trigger having an input terminal connected to the drain of the PMOS transistor MP3, a PMOS transistor MP6 having a source terminal connected to the source of the PMOS transistor MP3, an NMOS transistor MN3 having a gate terminal connected to the gate of the PMOS transistor MP6 and a source terminal connected to the source of the NMOS transistor MN2 and grounded, and a second RS trigger having an R terminal connected to the drain of the NMOS transistor MN3; wherein the drain and gate of the PMOS transistor MP6 are interconnected, and the output terminal of the first Schmitt trigger is connected to the S terminal of the second RS trigger.

[0022] Furthermore, in the present invention, when the second timing unit is an analog circuit, the second timing unit includes a PMOS transistor MP7, an NMOS transistor MN4, and a PMOS transistor MP8 whose gates are connected to each other, an NMOS transistor MN6 and a PMOS transistor MP11 whose gates are connected to the drain of the PMOS transistor MP7, a resistor R2 connected between the source of the NMOS transistor MN4 and the drain of the PMOS transistor MP11, a PMOS transistor MP9 whose source is connected to the source of the PMOS transistor MP8 and whose drain is connected to the drain of the PMOS transistor MP8 and the source of the PMOS transistor MP11, a gate connected to the gate of the PMOS transistor MP9 and whose source is connected to the drain of the PMOS transistor MP8 and the source of the PMOS transistor MP11, and a resistor R2 connected between the source of the NMOS transistor MN4 and the drain of the PMOS transistor MP11. The source of the PMOS transistor P9 is connected to a PMOS transistor MP10, and a capacitor C2 is connected between the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN4. The gate and drain of the PMOS transistor MP9 are interconnected, the source of the PMOS transistor MP7 is connected to the source of the PMOS transistor MP8, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN6, the source of the NMOS transistor MN6 is connected to the source of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the second driving unit, and the source of the PMOS transistor MP10 is connected to VDD.

[0023] Furthermore, in the present invention, the second driving unit is a second Schmitt trigger whose input terminal is connected to the drain of the PMOS transistor MP10.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) The present invention optimizes the power consumption management and locking sequence, adopts a multi-level interlocking method to optimize and manage the power consumption, abandons the control function of the enable signal, and performs adaptive sequential control in the power supply dimension. It is a supplementary power-on timing management method that ensures effective logic locking while adaptively reducing additional power consumption, and has positive practical significance and use value.

[0026] (2) The present invention adopts the domino signal chain control concept, which shuts down these modules step by step when powered on, thus getting rid of the constraints of the enable signal, saving power consumption, and ensuring a strict sequential relationship, thus avoiding errors in the working state import caused by timing conflicts. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a power-on timing diagram of the existing fuse trimming technology.

[0028] Figure 2 This is a principle block diagram of the processing method of the existing fuse trimming technology.

[0029] Figure 3This is a principle block diagram of the domino effect multi-stage interlocking processing method of the present invention.

[0030] Figure 4 It is a principle block diagram of the multi-stage interlocking circuit of the present invention.

[0031] Figure 5 This is a schematic diagram of the fuse logic timing lock circuit in the present invention.

[0032] Figure 6 This is a schematic diagram of the shutdown signal timing generation circuit in the present invention.

[0033] Figure 7 This is a schematic diagram of the digital circuit implementation principle of the timing unit of the present invention.

[0034] Figure 8 This is a schematic diagram of the digital circuit implementation principle of the timing endpoint monitoring of the present invention.

[0035] Figure 9 This is the power-on timing diagram for the traditional enable control fuse logic lock.

[0036] Figure 10 This is the power-on timing diagram for the traditional enable control fuse logic lock plus shutdown control.

[0037] Figure 11 This is a power-on timing diagram of the power-aware control fuse logic lock in the present invention.

[0038] Figure 12 This is a power-on timing diagram of the power consumption management with fuse logic locking according to the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described below with reference to the accompanying drawings and examples. The embodiments of the present invention include but are not limited to the following examples.

[0040] like Figure 3As shown, the present invention discloses a domino-type multi-stage interlocking power consumption management circuit, including a fuse logic generation circuit, a latch matrix, a subsequent module and a power sensing front end, and also includes a multi-stage timing interlocking circuit with a domino effect; wherein, the power sensing front end monitors the power supply status and generates a starting control signal through a threshold comparator. The starting control signal controls the multi-stage timing interlocking circuit, starts the chain timing, and generates a fuse logic lock signal to the latch matrix at the end of the timing, locks the fuse logic independently of the enable signal, and transmits it to the subsequent module; after the fuse logic lock signal is generated, the chain timing generates a shutdown signal to the fuse logic generation circuit, and the shutdown signal is also independent of the enable signal and is used to shut down the fuse logic generation circuit. wherein, the fuse logic generation circuit includes a bias circuit and a fuse logic establishment circuit. This not only ensures that the fuse logic is locked to the subsequent circuit, but also reduces the power consumption introduced by this part of the circuit in the enabled or disabled state. It forms a supplementary on-chip electric fuse logic reading method.

[0041] In this embodiment, if Figure 4 As shown, the multi-stage timing interlock circuit includes a fuse logic timing locking circuit and a shutdown signal timing generation circuit, which constitute the core of timing generation; the fuse logic timing locking circuit is composed of a first timing unit and a first driving unit; the shutdown signal timing generation circuit is composed of a second timing unit and a second driving unit.

[0042] The power sensing front end monitors the power status and generates a starting control signal through a threshold comparator, enabling a series of subsequent actions to be carried out.

[0043] Cascade control signal generation:

[0044] a: The starting control signal turns on the fuse logic timing lock module. After the countdown, the module generates two sets of signals. One set is the logic matrix locking signal, which is output to the latch matrix to logically lock the logic signal group generated by the fuse and transmit the locking logic to the subsequent module; the other set is the secondary timing control signal, which is used for the relay timing of the subsequent stage to ensure strict timing handover.

[0045] b: The secondary timing control signal turns on the shutdown signal timing generation module. After countdown, this module generates a bias network shutdown signal, which is used to turn off the bias network in the fuse logic generation circuit to achieve the purpose of reducing power consumption.

[0046] Domino Effect Timing Architecture:

[0047] Build a domino signal chain: power sensing signal → fuse logic lock enters countdown → generate logic lock control signal at the end of countdown → fuse logic establishment module enters shutdown countdown → generate shutdown signal to turn off fuse logic establishment module.

[0048] This idea is not limited to the counting requirements of fuse logic generation and locking, but is also applicable to other requirements that require power consumption management. For example, after the chip is powered on, some modules with light decisions or units with weak functions need to queue up to enter the working state. After the chip is working, these modules or units do not need to participate in the main signal chain. In this way, the domino signal chain control idea of this invention can be adopted to shut down these modules step by step when powered on, thereby getting rid of the constraints of the enable signal, saving power consumption, and ensuring a strict timing relationship before and after, avoiding errors in the import of working status caused by timing conflicts.

[0049] Example 1

[0050] The implementation methods of the fuse logic timing lockout circuit and the shutdown signal timing generation circuit are generally similar, with simple and easy-to-implement circuit structures. Both consist of a timing unit and a driving unit. The timing unit is composed of N-type and P-type transistors, resistors, and capacitors, while the driving unit is composed of SMITs, RS flip-flops, and N-type and P-type transistors.

[0051] In this embodiment, if Figure 5 As shown, the first timing unit is an analog circuit, which includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP4 whose gates are connected to each other, an NMOS transistor MN2 and a PMOS transistor MP5 whose gates are connected to the drain of the PMOS transistor MP1, a resistor R1 connected between the source of the NMOS transistor MN1 and the drain of the PMOS transistor MP5, a PMOS transistor MP2 whose source is connected to the source of the PMOS transistor MP4 and whose drain is connected to the drain of the PMOS transistor MP4 and the source of the PMOS transistor MP5, a PMOS transistor MP2 whose gate is connected to the gate of the PMOS transistor MP2 and whose source is connected to the source of the PMOS transistor MP2. The first driving unit comprises a first transistor MP3 and a capacitor C1 connected between the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN1; wherein the gate and drain of the PMOS transistor MP2 are interconnected, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP4, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1, the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN2 are both connected to the first driving unit, and the source of the PMOS transistor MP3 is connected to VDD.

[0052] The first driving unit includes a first Schmitt trigger (i.e. Figure 5The first Schmitt trigger includes a PMOS transistor MP6 having a source connected to the source of the PMOS transistor MP3, an NMOS transistor MN3 having a gate connected to the gate of the PMOS transistor MP6 and a source connected to the source of the NMOS transistor MN2 and grounded, and a second RS trigger having an R terminal connected to the drain of the NMOS transistor MN3; wherein the drain and gate of the PMOS transistor MP6 are interconnected, and the output terminal of the first Schmitt trigger is connected to the S terminal of the second RS trigger.

[0053] like Figure 6 As shown, the second timing unit is an analog circuit, which includes a PMOS transistor MP7, an NMOS transistor MN4, and a PMOS transistor MP8 whose gates are connected to each other, an NMOS transistor MN6 and a PMOS transistor MP11 whose gates are connected to the drain of the PMOS transistor MP7, a resistor R2 connected between the source of the NMOS transistor MN4 and the drain of the PMOS transistor MP11, a PMOS transistor MP9 whose source is connected to the source of the PMOS transistor MP8 and whose drain is connected to the drain of the PMOS transistor MP8 and the source of the PMOS transistor MP11, a gate connected to the gate of the PMOS transistor MP9 and whose source is connected to the source of the PMOS transistor MP9. The PMOS transistor MP10 is connected to the PMOS transistor MP10, and the capacitor C2 is connected between the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN4; wherein, the gate and drain of the PMOS transistor MP9 are interconnected, the source of the PMOS transistor MP7 is connected to the source of the PMOS transistor MP8, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN6, the source of the NMOS transistor MN6 is connected to the source of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the second driving unit, and the source of the PMOS transistor MP10 is connected to VDD.

[0054] In this embodiment, the second driving unit is a second Schmitt trigger (ie, Figure 6 SMIT2 triggers in .

[0055] For the circuit with fuse logic timing lock, when the chip starts to power on, the starting point control signal is low. The starting point control signal passes through the inverter composed of MP1 and MN1, and the NET0 node is powered on along with the power supply. MP5 is in the off state, MP4 pulls up the NET1 node voltage to a high level, and the mirror current source composed of MP2 and MP3 does not work; as the NET0 node voltage gradually increases, MN2 is initially turned on, giving NET2 an initial state of 0, and the logic matrix lock signal group and the secondary timing control signal both output low levels.

[0056] When the power sensing front end detects that the power supply has reached the threshold level and flips to a high level, the NET0 node becomes a low level, MP5 is turned on, MP4 is turned off, the NET1 node voltage is pulled down by MP5, and the mirror current source composed of MP2 and MP3 starts working. MP3 conducts current to charge capacitor C1, and the NET2 node voltage gradually rises. Since the NET0 node voltage is pulled down, MN2 is turned off, allowing the NET2 node voltage to effectively pass through the SMIT trigger. When the voltage rises to reach the SMIT threshold, the logic matrix lock signal group and the secondary timing control signal both output low and high levels, relaying the drive of the subsequent circuit.

[0057] The concept behind the domino signal chain is that once a control signal is triggered, the subsequent cascade control timing is initiated irreversibly. After the chip is powered on, the gate voltages of MP6 and MN3 float in an intermediate state, forming a tie-low logic state. MN3 pulls down the level of NET3. At this point, once the SMIT output goes high, generating a logic matrix lock signal, the RS flip-flop pulls the secondary timing control signal high, initiating the subsequent shutdown signal timer. Regardless of jitter in the SMIT output signal, the secondary timing control is irreversible. While the SMIT exhibits threshold hysteresis, the use of the RS flip-flop undoubtedly further improves timing reliability. In various engineering environments, the power supply may experience instability during power-up. Using a domino signal chain control approach can avoid timing conflicts caused by logic lock.

[0058] By changing the width-to-length ratio of R1 and MP2, the magnitude of the current at the current mirror source can be adjusted. By adjusting the mirror ratio of MP2 and MP3, the ratio of the mirror current to the charging current of the capacitor C1 can be adjusted. By adjusting the size of the capacitor C1, the charging time, that is, the timing time, can be adjusted. The circuit is simple and flexible to use.

[0059] Compared to the circuit with fuse logic timing lock, the shutdown signal timing generation circuit's input control signal is the aforementioned secondary timing control signal. The control principles of the remaining circuits are essentially the same as those of the fuse logic timing lock circuit and will not be elaborated on here. Because the present invention's use case does not involve additional modules in the cascade control, the subsequent stages of the shutdown signal generation circuit do not require additional timing, so the shutdown signal timing generation circuit does not use RS flip-flops to form a domino relay cascade.

[0060] Similarly, the timing time can be adjusted by adjusting the size of R2 and C2, as well as the aspect ratio and mirror ratio of MP9 and MP10.

[0061] Example 2

[0062] The timing unit of the aforementioned circuit is not limited to being implemented in the form of an analog circuit. Other variations of the timing unit can also be used, such as Figure 7Here, a clock is required, and the circuit that generates the clock can be a ring oscillator, but is not limited to a specific oscillator.

[0063] When the first timing unit and the second timing unit are digital circuits, the two timing units are composed of a cascade shift register and a timing endpoint monitoring module.

[0064] For the sake of convenience, taking the timing unit of the fuse logic timing lock circuit as an example, when the power sensing front end detects that the power supply has reached the threshold level and flips to a high level, the oscillation clock collects the "high level" information and sends it to the cascade shift register, and continuously pushes the "starting signal" to the subsequent stage through the clock. The oscillation clock and the cascade length of the register are the length of the timing time. When the "starting signal" is pushed to the timing end monitoring module, the timing end monitoring module outputs the "secondary timing control" signal to the subsequent stage for relay timing, and at the same time generates a timing shutdown signal to shut down the cascade shift register.

[0065] To prevent transmission errors caused by internal chip noise and improve timing reliability, the timing endpoint monitoring module uses a blocking and holding technique, resulting in a simple and easy-to-implement structure. The module consists of four NAND gates (N1, N2, N4) and a first RS flip-flop. The starting control signal is fed into one input of NAND gate N2. The output of NAND gate N2 feeds a signal to NAND gate N4 and one input of NAND gate N1. The output of NAND gate N4 feeds a signal to the other input of NAND gate N2 and the S terminal of the first RS flip-flop. The output of NAND gate N3 feeds a signal to the other input of NAND gate N1, the other input of NAND gate N4, and the R terminal of the first RS flip-flop. The output of NAND gate N1 feeds a signal to one input of NAND gate N3. The other input of NAND gate N3 and the third input of NAND gate N4 feed an oscillating clock signal.

[0066] For ease of illustration, let's take the timing unit of a fuse-logic timing lockout circuit as an example. When the start control signal is generated and pushed by the clock to the timing endpoint monitoring circuit, when the oscillation clock is low, the outputs of N3 and N4 are locked by the clock's low level. While the state of the start signal can affect the outputs of N1 and N2, it has no effect on N3 and N4, and the RS flip-flop remains unchanged.

[0067] Before the rising edge of the oscillation clock arrives, the start signal is high. Because the N3 and N4 clocks are locked at a low level, the outputs of N3 and N4 are 1, the output of N1 is 1, and the output of N2 is 0. At this point, the output states of N1 and N2 cannot be transmitted to the RS flip-flop through N3 and N4, and the flip-flop remains in its original state. When the oscillation clock arrives, the states of N1 and N2 are reflected in the RS flip-flop, and the output of N2 goes low, which acts on N4, leaving the output of N4 unchanged. The output of N3 drops low, causing the trigger output to change to 1. Therefore, as long as the high level of the start signal has been pushed to the timing endpoint monitoring circuit before the rising edge of the clock arrives, the output state of the flip-flop will change to 1 after the rising edge of the oscillation clock arrives, regardless of the state of the RS flip-flop. This generates the secondary timing control signal, ensuring the smooth execution of the subsequent cascade timing.

[0068] At the same time, the output of N3 is low, which acts on the input terminals of N4 and N1, locking N4 and N1. That is, during the period when the clock is high, no matter how the serial data changes, the output state of the trigger remains 1 irreversibly, thereby ensuring the reliability of timing endpoint monitoring.

[0069] The above process is applicable to the monitoring scenario where the starting signal is high. If the starting signal is low, the signal of the timing endpoint monitoring circuit can be reversely processed, which is also within the scope of application of the present invention.

[0070] Next, let's discuss the case where the start signal has not yet been established. If the start control signal is low before the rising clock edge arrives, the low-level clocks of N3 and N4 will lock the N3 and N4 outputs to 1, N1 to 0, and N2 to 1. In this case, the start control signal cannot be transmitted to N1 and N2 via N3 and N4. When the rising clock edge arrives, N1 outputs 0, causing N3 to remain locked. The 1 output of N2 turns on N4, causing its output to go low, causing the RS flip-flop output to go low. Therefore, as long as the start control signal input is low before the serial clock rising edge arrives, the flip-flop output will return to a low state after the serial clock rising edge, regardless of the flip-flop's state.

[0071] At the same time, N4 output is low, so that N2 is locked. Then, during the period when the clock is high, no matter how the starting control signal changes, the trigger output state remains low. The above-mentioned timing end monitoring module and cascade shift register circuit can both be used. Figure 8 If the noise environment inside the chip is relatively good, a common edge trigger can also be used according to design requirements.

[0072] The following example analyzes the circuit's operation. This invention is applicable to power-sequencing power management, using fuse trimming technology as an example. The simulation uses two fuse channels and a TSMC 180nm CMOS process.

[0073] Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 A chip power-up situation using fuse trimming technology is simulated. Figure 9 This is a chip power-up simulation with logic locked using EN enabled. "Power" represents the chip power supply, "Enable" is the chip enable signal, which activates the chip's operating state, and "Lock Signal" is the fuse logic lock signal, which locks the logic generated by the fuse module. "Locked Logic" represents the fuse logic locked by the lock signal and transmitted to downstream circuitry. "Supply Current" represents only the supply current of the fuse logic generation circuit during simulation, including the bias current used to establish the fuse logic. The simulation shows that when EN is enabled for logic lock, the "Supply Current" is 179uA after power-up. After enabling, the fuse logic is locked and transmitted to downstream circuitry. The "Supply Current" remains unchanged at 179uA.

[0074] In the picture Figure 10 is Figure 9 The shutdown signal is introduced based on the fuse logic. The "shutdown signal" in the figure means that after the fuse logic is locked, a shutdown signal is generated to turn off the module established by the fuse logic. The rest of the signals are the same. Figure 9 The simulation shows that after the enable signal is sent, the "supply current" drops to 195nA as the shutdown signal is generated. However, after the chip is powered on and before the enable signal arrives, the "supply current" remains at 179uA, adding additional power consumption overhead and being unfriendly in the disabled state.

[0075] In the picture Figure 11 is Figure 9 On the basis, change "Enable" to "Normal Low", the power sensing front end generates the starting control signal, and the other signals are the same Figure 9 The simulation shows that after the "starting signal" is generated, the fuse logic enters the locking process. Although it is freed from the constraints of the enable signal, the "supply current" remains at 179uA, which increases additional static power consumption.

[0076] Figure 12This is a simulation of a multi-stage interlocking power consumption management circuit and method using the power-on timing control of the present invention. The "locking signal" is a fuse logic timing locking circuit, which is also a secondary timing control logic. For ease of understanding, the secondary timing control signal and the locking signal are combined and displayed in the figure. After the power sensing front end generates a "starting signal", it is timed and a "locking signal" is generated to lock the fuse logic and transmit it to the subsequent circuit. At the same time, the secondary timing control signal starts the shutdown timing, and generates a shutdown signal after the timing ends, effectively reducing the "power supply current". The simulation shows that the fuse locking process does not require the participation of the enable signal. From the outside of the chip, after a short delay after the chip is powered on, the additional power consumption can be turned off, and the "power supply current" is reduced to 195nA. Compared with the structure without the shutdown signal, the power consumption is only about 0.1% of 179uA.

[0077] The above embodiment is only one of the preferred implementation methods of the present invention and should not be used to limit the scope of protection of the present invention. Any changes or modifications that have no substantive meaning made to the main design concept and spirit of the present invention, as long as the technical problems solved are still consistent with the present invention, should be included in the scope of protection of the present invention.

Claims

1. A domino-type multi-stage interlocking power consumption management circuit, comprising a fuse logic generation circuit, a latch matrix, and a power sensing front end for a subsequent module, characterized in that: It also includes a multi-stage timing interlocking circuit with a domino effect; wherein, the power sensing front end monitors the power status and generates a starting control signal through a threshold comparator. The starting control signal controls the multi-stage timing interlocking circuit to start the chain timing. When the timing ends, a fuse logic locking signal is generated to the latch matrix, which locks the fuse logic independently of the enable signal and transmits it to the subsequent module; after the fuse logic locking signal is generated, the chain timing generates a shutdown signal to the fuse logic generation circuit. The shutdown signal is also independent of the enable signal and is used to shut down the fuse logic generation circuit.

2. A domino-type multi-stage interlocking power consumption management circuit according to claim 1, characterized in that: The multi-stage timing interlock circuit includes a fuse logic timing locking circuit and a shutdown signal timing generation circuit; the fuse logic timing locking circuit is composed of a first timing unit and a first driving unit; the shutdown signal timing generation circuit is composed of a second timing unit and a second driving unit.

3. A domino-type multi-stage interlocking power consumption management circuit according to claim 2, characterized in that: When the first timing unit and the second timing unit are digital circuits, both timing units are composed of a cascade shift register and a timing endpoint monitoring module; when the power sensing front end detects that the power supply has reached a threshold level and flips to a high level, the oscillation clock collects the "high level" information into the cascade shift register of the first timing unit, and continuously pushes the "starting point signal" to the subsequent stage through the clock. The oscillation clock cooperates with the cascade length of the cascade shift register of the first timing unit, that is, the timing time length. When the "starting point signal" is pushed to the timing endpoint monitoring module of the first timing unit, the timing endpoint monitoring module of the first timing unit outputs a "secondary timing control" signal to the subsequent stage for relay timing, and at the same time generates a timing shutdown signal to shut down the cascade shift register of the first timing unit.

4. A domino-type multi-stage interlocking power consumption management circuit according to claim 3, characterized in that: The timing endpoint monitoring module is composed of four NAND gates N1 to NAND gate N4 and a first RS trigger; wherein, the starting point control signal is input from one input end of NAND gate N2, the output end of NAND gate N2 outputs a signal to NAND gate N4 and one input end of NAND gate N1, the output end of NAND gate N4 outputs a signal to the other input end of NAND gate N2 and the S end of the first RS trigger, the output end of NAND gate N3 outputs a signal to the other input end of NAND gate N1, the other input end of NAND gate N4 and the R end of the first RS trigger, the output end of NAND gate N1 outputs a signal to one input end of NAND gate N3, and the other input end of NAND gate N3 and the third input end of NAND gate N4 input an oscillation clock signal.

5. A domino-type multi-stage interlocking power consumption management circuit according to claim 2, characterized in that: When the first timing unit is an analog circuit, the first timing unit includes a PMOS transistor MP1, an NMOS transistor MN1, and a PMOS transistor MP4 connected to each other at the gate, an NMOS transistor MN2 and a PMOS transistor MP5 connected to the drain of the PMOS transistor MP1, a resistor R1 connected between the source of the NMOS transistor MN1 and the drain of the PMOS transistor MP5, a PMOS transistor MP2 connected to the source of the PMOS transistor MP4 and the drain of the PMOS transistor MP4 and the source of the PMOS transistor MP5, a PMOS transistor MP3 connected to the gate of the PMOS transistor MP2 and the source of the PMOS transistor MP2. The S transistor MP3 and the capacitor C1 connected between the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN1; wherein the gate and drain of the PMOS transistor MP2 are interconnected, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP4, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1, the drain of the PMOS transistor MP3 and the source of the NMOS transistor MN2 are both connected to the first driving unit, and the source of the PMOS transistor MP3 is connected to VDD.

6. A domino-type multi-stage interlocking power consumption management circuit according to claim 5, characterized in that: The first driving unit includes a first Schmitt trigger having an input terminal connected to the drain of the PMOS transistor MP3, a PMOS transistor MP6 having a source terminal connected to the source of the PMOS transistor MP3, an NMOS transistor MN3 having a gate terminal connected to the gate of the PMOS transistor MP6 and a source terminal connected to the source of the NMOS transistor MN2 and grounded, and a second RS trigger having an R terminal connected to the drain of the NMOS transistor MN3; wherein the drain and gate of the PMOS transistor MP6 are interconnected, and the output terminal of the first Schmitt trigger is connected to the S terminal of the second RS trigger.

7. A domino-type multi-stage interlocking power consumption management circuit according to claim 6, characterized in that: When the second timing unit is an analog circuit, the second timing unit includes a PMOS transistor MP7, an NMOS transistor MN4, and a PMOS transistor MP8 connected to each other at the gate, an NMOS transistor MN6 and a PMOS transistor MP11 connected to the drain of the PMOS transistor MP7, a resistor R2 connected between the source of the NMOS transistor MN4 and the drain of the PMOS transistor MP11, a PMOS transistor MP9 connected to the source of the PMOS transistor MP8 and the drain of the PMOS transistor MP8 and the source of the PMOS transistor MP11, a gate connected to the gate of the PMOS transistor MP9 and the source connected to the source of the PMOS transistor MP9. The first embodiment of the present invention relates to a PMOS transistor MP10 connected to the first driving unit, and a capacitor C2 connected between the drain of the PMOS transistor MP10 and the source of the NMOS transistor MN4; wherein the gate and drain of the PMOS transistor MP9 are interconnected, the source of the PMOS transistor MP7 is connected to the source of the PMOS transistor MP8, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN6, the source of the NMOS transistor MN6 is connected to the source of the NMOS transistor MN4, the drain of the PMOS transistor MP10 is connected to the second driving unit, and the source of the PMOS transistor MP10 is connected to VDD.

8. The domino-type multi-stage interlocking power consumption management circuit according to claim 7, characterized in that: The second driving unit is a second Schmitt trigger whose input terminal is connected to the drain of the PMOS transistor MP10.

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