Phase-locked loop frequency configuration value determination method and device, equipment and medium

Abstract

The invention relates to a phase-locked loop frequency configuration value determination method and device, equipment and a medium, and the method comprises the steps: obtaining frequency control data of a frequency hopping source, converting the frequency control data into a preset system sequence, dividing the preset system sequence into a plurality of mark sequence segments, and determining a phase-locked loop frequency configuration value based on each mark sequence segment; determining a plurality of initial frequency division factors of the phase-locked loop, determining a target frequency division factor of the phase-locked loop in combination with the plurality of initial frequency division factors, and taking the target frequency division factor as a frequency configuration value; the method does not need to use a high-performance digital processor or an additional storage device, has the characteristics of low cost, small size and low power consumption, greatly reduces the data volume and the storage volume of the fractional frequency division value and the integer frequency division value, not only improves the calculation efficiency of the fractional frequency division value and the integer frequency division value, but also reduces the storage pressure of the FPGA or the MCU, and improves the calculation efficiency of the fractional frequency division value and the integer frequency division value. The working efficiency of the phase-locked loop is improved, and user requirements are better met.

Description

Technical Field

[0001] The present invention relates to the field of phase-locked loop control technology, and in particular to a method, device, equipment and medium for determining a frequency configuration value of a phase-locked loop. Background Art

[0002] The phase-locked loop is an essential device for the frequency source to generate a stable, accurate and adjustable frequency signal. The frequency hopping source implemented with the phase-locked loop requires a digital processor such as a field programmable gate array (FPGA) or a microcontroller unit (MCU) to calculate the frequency control data sent by the user and then convert it into the frequency configuration value of the phase-locked loop device. Digital processors such as FPGA or MCU often need to use floating point and multiplication and division operations to complete the calculation of the frequency configuration value of the small step (such as 10Hz) frequency hopping source.

[0003] The frequency configuration value of the relevant frequency hopping source is generally implemented in two ways: one is to directly use a digital processor such as FPGA or MCU that supports floating-point and multiplication and division operations to perform the operation directly. This method will lead to an increase in the use cost, equipment size and power consumption during the operation of the phase-locked loop frequency, and there is a long operation time, which cannot meet the frequency switching time requirement; the other is to complete the operation of all frequency points in advance, and directly build a table to store the operation results in the product. When the frequency needs to be switched, the digital processor such as FPGA or MCU finds the operation result by looking up the table. However, this method will require a larger storage space to store the operation results (the operation results often exceed the storage space integrated in the FPGA or MCU) when the frequency hopping source has a large number of frequency points (such as a broadband small-step frequency hopping source with hundreds of millions of frequency points), and a longer table lookup time to query the stored results, thereby reducing the working efficiency of the phase-locked loop and failing to meet user needs. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a method, device, equipment and medium for determining a frequency configuration value of a phase-locked loop to solve the above-mentioned technical problems.

[0005] The present invention provides a method for determining a frequency configuration value of a phase-locked loop, the method comprising: acquiring frequency control data of a frequency hopping source; converting the frequency control data into a preset base sequence, and dividing the preset base sequence into a plurality of marking sequence segments; the preset base sequence is obtained by accumulating different preset sequence segments; the preset sequence segments are used to characterize preset frequency points of the frequency hopping source; the frequency difference between adjacent preset frequency points is greater than or equal to a preset step frequency; based on each marking sequence segment, determining a plurality of initial frequency division factors of the phase-locked loop; combining the plurality of the initial frequency division factors, determining a target frequency division factor of the phase-locked loop, and using the target frequency division factor as the frequency configuration value.

[0006] In one embodiment of the present invention, the process of dividing the preset base sequence into multiple marked sequence segments includes: determining multiple bit ranges of the preset base sequence according to a preset segmentation threshold, and determining a bit range screening sequence based on each bit range to obtain multiple bit range screening sequences; and performing AND operations on the multiple bit range screening sequences and the preset base sequence respectively to obtain multiple marked sequence segments.

[0007] In one embodiment of the present invention, if the plurality of bit range screening sequences include a first bit range screening sequence, a second bit range screening sequence, a third bit range screening sequence and a fourth bit range screening sequence, then the plurality of bit range screening sequences are respectively ANDed with the preset base sequence to obtain a plurality of marking sequence segments, and the process includes: performing an AND operation on the preset base sequence and the first bit range screening sequence to obtain a first marking sequence segment; right-shifting the preset base sequence according to the number of bits of the first marking sequence segment to obtain a first shift sequence; performing an AND operation on the first shift sequence and the second bit range screening sequence; Operation is performed to obtain a second marking sequence segment; the first moving sequence is right-shifted according to the number of bits of the second marking sequence segment to obtain a second moving sequence, and the second moving sequence is ANDed with the third bit range screening sequence to obtain a third marking sequence segment; the second moving sequence is right-shifted according to the number of bits of the third marking sequence segment to obtain a third moving sequence, and the third moving sequence is ANDed with the fourth bit range screening sequence to obtain a fourth marking sequence segment; the preset base sequence is obtained by splicing the first marking sequence segment, the second marking sequence segment, the third marking sequence segment and the fourth marking sequence segment in bit order.

[0008] In one embodiment of the present invention, if the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, then the process of determining the target frequency division factor of the phase-locked loop in combination with multiple initial frequency division factors includes: adding multiple fractional frequency division values ​​to obtain the sum of fractional frequency division values; and adding multiple integer frequency division values ​​to obtain the sum of integer frequency division values; comparing the sum of fractional frequency division values ​​with a preset fractional frequency division threshold, and determining the target frequency division factor based on the comparison result, the sum of fractional frequency division values, and the sum of integer frequency division values.

[0009] In one embodiment of the present invention, the process of determining the target frequency division factor according to the comparison result, the sum of the decimal frequency division values, and the sum of the integer frequency division values ​​includes: if the sum of the decimal frequency division values ​​is less than the preset decimal frequency division threshold, the sum of the decimal frequency division values ​​is used as the target decimal frequency division value; the sum of the integer frequency division values ​​is used as the target integer frequency division value; and the target decimal frequency division value and the target integer frequency division value are used as the target frequency division factor; if the sum of the decimal frequency division values ​​is greater than or equal to the preset decimal frequency division threshold, the difference between the sum of the decimal frequency division values ​​and the preset decimal frequency division threshold is used as the target decimal frequency division value; the sum of the sum of the integer frequency division values ​​and the preset integer frequency division threshold is used as the target integer frequency division value; and the target decimal frequency division value and the target integer frequency division value are used as the target frequency division factor.

[0010] In one embodiment of the present invention, if the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, then before determining multiple initial frequency division factors of the phase-locked loop based on each marked sequence segment, the method also includes: accumulating different preset sequence segments according to each bit range to obtain multiple accumulated sequence segments; based on the value of each accumulated sequence segment and the preset phase-locked frequency, calculating the fractional frequency division value and the integer frequency division value of each accumulated sequence segment.

[0011] In one embodiment of the present invention, based on each mark sequence segment, the process of determining multiple initial frequency division factors of the phase-locked loop includes: selecting a mark sequence segment as a target mark sequence segment, comparing the target mark sequence segment with an accumulation sequence segment belonging to the same bit range; if the target mark sequence segment is successfully compared with any accumulation sequence segment belonging to the same bit range, then using the fractional frequency division value of the arbitrary accumulation sequence segment as a fractional frequency division value of the phase-locked loop; using the integer frequency division value of the arbitrary accumulation sequence segment as an integer frequency division value of the phase-locked loop; selecting another The mark sequence segment is used as an update mark sequence segment, and the update mark sequence segment is compared with the accumulation sequence segments belonging to the same bit range; if the update mark sequence segment is successfully compared with any accumulation sequence segment belonging to the same bit range, the decimal frequency division value of the arbitrary accumulation sequence segment is used as a decimal frequency division value of the phase-locked loop; the integer frequency division value of the arbitrary accumulation sequence segment is used as an integer frequency division value of the phase-locked loop, until each mark sequence segment is compared with multiple accumulation sequence segments, so as to obtain multiple integer frequency division values ​​and multiple decimal frequency division values ​​of the phase-locked loop.

[0012] According to one aspect of an embodiment of the present invention, a device for determining a frequency configuration value of a phase-locked loop is provided, the device comprising: a data acquisition module, used to acquire frequency control data of a frequency hopping source; a sequence division module, used to convert the frequency control data into a preset base sequence, and divide the preset base sequence into a plurality of marked sequence segments; the preset base sequence is obtained by accumulating different preset sequence segments; the preset sequence segments are used to characterize preset frequency points of the frequency hopping source; the frequency difference between adjacent preset frequency points is greater than or equal to a preset step frequency; a factor determination module, used to determine a plurality of initial frequency division factors of the phase-locked loop based on each marked sequence segment; a configuration value determination module, used to determine a target frequency division factor of the phase-locked loop in combination with the plurality of the initial frequency division factors, and use the target frequency division factor as the frequency configuration value.

[0013] According to one aspect of an embodiment of the present invention, there is provided an electronic device, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the method for determining a phase-locked loop frequency configuration value as described above.

[0014] According to one aspect of an embodiment of the present application, a computer storage medium is provided, including: computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer executes the above-mentioned method for determining a phase-locked loop frequency configuration value.

[0015] The beneficial effects of the present invention are as follows: the present invention obtains the frequency control data of the frequency hopping source, converts the frequency control data into a preset base sequence, and divides the preset base sequence into a plurality of mark sequence segments, determines a plurality of initial frequency division factors of the phase-locked loop based on each mark sequence segment, determines a target frequency division factor of the phase-locked loop in combination with the plurality of initial frequency division factors, and uses the target frequency division factor as the frequency configuration value. In the above process, in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, there is no need to directly perform floating-point operations and multiplication and division operations, thereby reducing the complexity of operations in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, thereby reducing the time spent on operations in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, and does not require the use of a high-performance digital processor or an additional storage device, and has the advantages of low cost, The characteristics of small size and low power consumption; in addition, since the accumulated sequence segments are obtained by adding different preset sequence segments, the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source, and the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency. Therefore, in the process of calculating the decimal division values ​​and integer division values ​​of all accumulated sequence segments, it is not necessary to calculate the decimal division values ​​and integer division values ​​of each preset step frequency, but only calculate the decimal division values ​​and integer division values ​​for the frequency points corresponding to the accumulated sequence segments, which greatly reduces the data volume and storage volume of the decimal division values ​​and the integer division values, not only improves the calculation efficiency of the decimal division values ​​and the integer division values, but also reduces the storage pressure of the FPGA or MCU, as well as the table lookup time of the decimal division values ​​and the integer division values, improves the working efficiency of the phase-locked loop, and better meets user needs.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 is a schematic diagram of an exemplary system architecture shown in an exemplary embodiment of the present application;

[0019] Figure 2 is a flow chart of a method for determining a phase-locked loop frequency configuration value shown in an exemplary embodiment of the present application;

[0020] Figure 3is a block diagram of a device for determining a frequency configuration value of a phase-locked loop shown in an exemplary embodiment of the present application;

[0021] Figure 4 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0023] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0025] In this application, the frequency range of the frequency hopping source is: 1500MHz~3000MHz, the preset frequency step is 10Hz, and the total number of frequency points is 150 million frequency points. The user controls the frequency control data (F VCO ) is represented by 1 29-bit data, the unit is 10Hz, the high bit is in front, and the frequency value corresponding to the frequency control data is F VCO *10Hz; the frequency hopping source product adopts a 24-bit fractional frequency ratio phase-locked loop, with a preset phase detection frequency (F PFD ) is 50000000 Hz, N represents the integer value of the phase-locked loop feedback frequency division (integer frequency division value), and F represents the decimal value of the phase-locked loop feedback frequency division (fractional frequency division value). The calculation formula of the integer frequency division value is as follows:

[0026] N = floor ((F VCO *10Hz) / F PFD ) Formula (1)

[0027] Where N represents the integer frequency division value of the phase-locked loop, F VCO Indicates the frequency control data of the frequency hopping source, F PFD Indicates the preset phase-locked frequency, and floor indicates the maximum integer less than or equal to it.

[0028] The calculation formula for the fractional frequency value is as follows:

[0029] F=INT((((F VCO *10Hz)-N*F PFD ) / F PFD )*16777216) Formula (2)

[0030] Where F represents the fractional frequency value of the phase-locked loop, F VCO Indicates the frequency control data of the frequency hopping source, F PFD Indicates the preset phase-locked frequency. INT means rounding to the nearest integer.

[0031] From formula (1) and formula (2), we can know that the frequency control data (F VCO ) is converted into integer and decimal frequency division values ​​for phase-locked loop configuration, which requires floating-point and multiplication and division operations. There are 150 million frequency points. If the integer and decimal frequency division values ​​of each frequency point are directly stored, the amount of data will be very large.

[0032] Figure 1 It is a schematic diagram of an exemplary system architecture shown in an exemplary embodiment of the present application.

[0033] Reference Figure 1 As shown, the system architecture may include an input device 101 and a computer device 101. The computer device 101 may be at least one of a desktop graphics processing unit (GPU) computer, a GPU computing cluster, a neural network computer, etc. Relevant technicians may use the computer device 101 to obtain the frequency control data of the frequency hopping source, convert the frequency control data into a preset base sequence, and divide the preset base sequence into a plurality of mark sequence segments, determine a plurality of initial frequency division factors of the phase-locked loop based on each mark sequence segment, determine a target frequency division factor of the phase-locked loop in combination with the plurality of initial frequency division factors, and use the target frequency division factor as a frequency configuration value. The input device 101 is used to input the frequency control data of the frequency hopping source sent by the user. In this embodiment, the input device 101 uses a voice input device or a touch screen device to input the frequency control data of the frequency hopping source, and provides it to the computer device 101 for processing.

[0034] Schematically, after acquiring the frequency control data of the frequency hopping source in the input device 101, the computer device 101 converts the frequency control data into a preset base sequence, and divides the preset base sequence into a plurality of mark sequence segments, and determines a plurality of initial frequency division factors of the phase-locked loop based on each mark sequence segment, and determines a target frequency division factor of the phase-locked loop in combination with the plurality of initial frequency division factors, and uses the target frequency division factor as the frequency configuration value. In the above process, in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, there is no need to directly perform floating-point operations and multiplication and division operations, which reduces the complexity of the operations in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, thereby reducing the time spent on the operations in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, and does not require the use of a high-performance digital processor or an additional storage device. The invention has the characteristics of low cost, small size and low power consumption; in addition, since the accumulated sequence segments are obtained by accumulating different preset sequence segments, the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source, and the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency, therefore, in the process of calculating the decimal frequency division values ​​and the integer frequency division values ​​of all accumulated sequence segments, it is not necessary to calculate the decimal frequency division values ​​and the integer frequency division values ​​of each preset step frequency, but only calculate the decimal frequency division values ​​and the integer frequency division values ​​for the frequency points corresponding to the accumulated sequence segments, which greatly reduces the data volume and storage volume of the decimal frequency division values ​​and the integer frequency division values, not only improves the calculation efficiency of the decimal frequency division values ​​and the integer frequency division values, but also reduces the storage pressure of the FPGA or MCU, as well as the table lookup time of the decimal frequency division values ​​and the integer frequency division values, improves the working efficiency of the phase-locked loop, and better meets user needs.

[0035] It should be noted that the method for determining the frequency configuration value of a phase-locked loop provided in the embodiment of the present application is generally executed by the computer device 101 , and accordingly, the device for determining the frequency configuration value of a phase-locked loop is generally disposed in the computer device 101 .

[0036] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0037] Figure 2 is a flowchart of a method for determining a phase-locked loop frequency configuration value according to an exemplary embodiment of the present application. The method for determining a phase-locked loop frequency configuration value can be executed by a computing and processing device. The computing and processing device can be Figure 1 The computer device 101 shown in FIG. Figure 2 As shown, the method for determining the frequency configuration value of a phase-locked loop includes at least steps S210 to S240, which are described in detail as follows:

[0038] In step S210, frequency control data of a frequency hopping source is obtained. In one embodiment of the present application, the frequency control data is obtained by being sent down by a user, and the frequency range of the frequency hopping source is 1500 MHz to 3000 MHz.

[0039] In step S220, the frequency control data is converted into a preset base sequence, and the preset base sequence is divided into a plurality of mark sequence segments. In one embodiment of the present application, the preset base sequence is obtained by accumulating different preset sequence segments; the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source; the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency, the preset step frequency is 10 Hz, and the preset base sequence is a binary sequence. For example, if the user wants to control the frequency hopping source to hop to the frequency point of 2134.56425 MHz, the F VCO The value is 213456425, which is represented by a binary number in a digital processor, that is, 01100101110010001011000101001 (29-bit binary). Then, taking the division into 4 tag sequence segments as an example, the preset binary sequence 01100101110010001011000101001 is divided into four sequence segments 01100101, 1100100, 0101100 and 0101001 in the order from high to low. Different preset sequence segments are shown in the following table:

[0040] Table 1

[0041] The bit position is 1 Preset sequence segments Preset frequency points Frequency Unit bit28 10000000000000000000000000000 2684.35456 MHz bit27 01000000000000000000000000000 1342.17728 MHz bit26 00100000000000000000000000000 671.08864 MHz bit25 00010000000000000000000000000 335.54432 MHz bit24 00001000000000000000000000000 167.77216 MHz bit23 00000100000000000000000000000 83.88608 MHz bit22 00000010000000000000000000000 41.94304 MHz bit21 00000001000000000000000000000 20.97152 MHz bit20 00000000100000000000000000000 10.48576 MHz bit19 00000000010000000000000000000 5.24288 MHz bit18 00000000001000000000000000000 2.62144 MHz bit17 00000000000100000000000000000 1.31072 MHz bit16 00000000000010000000000000000 655.36 KHz bit15 00000000000001000000000000000 327.68 KHz bit14 00000000000000100000000000000 163.84 KHz bit13 00000000000000010000000000000 81.92 KHz bit12 00000000000000001000000000000 40.96 KHz bit11 00000000000000000100000000000 20.48 KHz bit10 00000000000000000010000000000 10.24 KHz bit9 00000000000000000001000000000 5.12 KHz bit8 00000000000000000000100000000 2.56 KHz bit7 00000000000000000000010000000 1280 Hz bit6 00000000000000000000001000000 640 Hz bit5 00000000000000000000000100000 320 Hz bit4 00000000000000000000000010000 160 Hz bit3 00000000000000000000000001000 80 Hz bit2 00000000000000000000000000100 40 Hz bit1 00000000000000000000000000010 20 Hz bit0 00000000000000000000000000001 10 Hz

[0042] In Table 1, the 29-bit binary data is expanded bit by bit, and each bit represents a different preset frequency point when it is 1. The preset frequency points corresponding to different bits being 1 are accumulated to represent the frequency point to which the user wants to control the frequency hopping source to hop. For example, the preset sequence segment with bit 0 being 1 and the preset sequence segment with bit 1 being 1 are accumulated to obtain a new sequence segment 0000000000000000000000000000011. The frequency point represented by the new sequence segment is 30 Hz, and the decimal value 3 of 0000000000000000000000000011 is F VCO. If the integer frequency division value and the decimal frequency division value are calculated separately according to the frequency of each bit, the integer frequency division value and the decimal frequency division value corresponding to each bit can be obtained. The integer frequency division value and the decimal frequency division value corresponding to each bit are stored in a table. Then, when the frequency hopping source module is working, the integer frequency division value and the decimal frequency division value corresponding to each bit are found by looking up the table. Then, the integer frequency division value and the decimal frequency division value of each bit are accumulated to obtain the target integer frequency division value and the target decimal frequency division value corresponding to the frequency control data, so that the frequency control data represented by the binary sequence is split bit by bit, and then the integer frequency division value and the decimal frequency division value are calculated separately, instead of calculating the integer frequency division value and the decimal frequency division value according to each preset step frequency point, which can greatly reduce the amount of calculation and storage of the decimal frequency division value and the integer frequency division value.

[0043] In step S230, multiple initial frequency division factors of the phase-locked loop are determined based on each mark sequence segment. In one embodiment of the present application, the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, and each mark sequence segment has a corresponding fractional frequency division value and an integer frequency division value. Therefore, after obtaining each mark sequence segment, multiple fractional frequency division values ​​and multiple integer frequency division values ​​can be determined by comparison.

[0044] In step S240, the target frequency division factor of the phase-locked loop is determined in combination with a plurality of initial frequency division factors, and the target frequency division factor is used as the frequency configuration value. In one embodiment of the present application, the frequency control data of the frequency hopping source is obtained, the frequency control data is converted into a preset base sequence, and the preset base sequence is divided into a plurality of mark sequence segments, and based on each mark sequence segment, a plurality of initial frequency division factors of the phase-locked loop are determined, and the target frequency division factor of the phase-locked loop is determined in combination with a plurality of initial frequency division factors, and the target frequency division factor is used as the frequency configuration value. In the above process, after obtaining the frequency control data, in the process of determining the frequency configuration value of the phase-locked loop, there is no need to directly perform floating-point operations and multiplication and division operations, which reduces the complexity of the operation in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, thereby reducing the time spent on the operation in the process of determining the frequency configuration value of the phase-locked loop after obtaining the frequency control data, and does not require the use of a high-performance digital processor or an additional storage device, which has low cost, The characteristics of small size and low power consumption; in addition, since the accumulated sequence segments are obtained by adding different preset sequence segments, the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source, and the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency. Therefore, in the process of calculating the decimal division values ​​and integer division values ​​of all accumulated sequence segments, it is not necessary to calculate the decimal division values ​​and integer division values ​​of each preset step frequency, but only calculate the decimal division values ​​and integer division values ​​for the frequency points corresponding to the accumulated sequence segments, which greatly reduces the data volume and storage volume of the decimal division values ​​and the integer division values, not only improves the calculation efficiency of the decimal division values ​​and the integer division values, but also reduces the storage pressure of the FPGA or MCU, as well as the table lookup time of the decimal division values ​​and the integer division values, improves the working efficiency of the phase-locked loop, and better meets user needs.

[0045] In one embodiment of the present application, the process of dividing the preset binary sequence into a plurality of mark sequence segments includes:

[0046] According to the preset segmentation threshold, multiple bit ranges of the preset base sequence are determined, and according to each bit range, a bit range screening sequence is determined to obtain multiple bit range screening sequences. In one embodiment of the present application, the preset segmentation threshold can be determined based on the calculation amount of the decimal frequency division value and the integer frequency division value, the storage amount of the decimal frequency division value and the integer frequency division value, and the error amount of the decimal frequency division value and the integer frequency division value, which is not specifically limited here. After determining the preset segmentation threshold, the number of bit ranges is also determined, and each bit range needs to be determined based on the calculation amount of the decimal frequency division value and the integer frequency division value, the storage amount of the decimal frequency division value and the integer frequency division value, and the error amount of the decimal frequency division value and the integer frequency division value, which is not specifically limited here. After obtaining the bit range, each bit position in the bit range is set to 1 to obtain the bit range screening sequence.

[0047] Multiple bit range screening sequences are respectively ANDed with the preset binary sequence to obtain multiple tag sequence segments. In one embodiment of the present application, the preset segmentation threshold is 4, the number of bit ranges is 4, and the 4 bit ranges are (bit6-bit0), (bit13-bit7), (bit20-bit14) and (bit28-bit21), the bit range screening sequence corresponding to the bit range (bit6-bit0) is 00000000000000000000001111111, and the bit range (bit1 The bit range screening sequence corresponding to the bit range (bit3-bit7) is 0000000000000000000000011111111, the bit range screening sequence corresponding to the bit range (bit20-bit14) is 000000000000000000000011111111, and the bit range corresponding to the bit range (bit28-bit21) is 000000000000000000000111111111.

[0048] In one embodiment of the present application, if the plurality of bit range screening sequences include a first bit range screening sequence, a second bit range screening sequence, a third bit range screening sequence, and a fourth bit range screening sequence, then the plurality of bit range screening sequences are respectively ANDed with a preset base sequence to obtain a plurality of marking sequence segments, including:

[0049] The preset base sequence is ANDed with the first bit range screening sequence to obtain a first marking sequence segment. In one embodiment of the present application, the first bit range screening sequence is used to screen the values ​​of the first bit range, and taking the bit range screening sequence 0000000000000000000000001111111 corresponding to the bit range (bit6-bit0) as the first bit range screening sequence and the preset base sequence 01100101110010001011000101001 as an example, after the preset base sequence is ANDed with the first bit range screening sequence, the first marking sequence segment 0101001 is obtained.

[0050] The preset base sequence is right-shifted according to the number of bits of the first marking sequence segment to obtain a first moving sequence, and the first moving sequence is ANDed with the second bit range screening sequence to obtain a second marking sequence segment. In one embodiment of the present application, the second bit range screening sequence is used to screen the values ​​of the second bit range, and the bit range screening sequence corresponding to the bit range (bit13-bit7) is 0000000000000000000000111111 as the second bit range screening sequence, and the preset base sequence is 01100101110010001011000101001 as an example, the preset base sequence is right-shifted according to the number of bits of the first marking sequence segment to obtain a first moving sequence 0110010111001000101100, and after the first moving sequence is ANDed with the second bit range screening sequence, the second marking sequence segment 0101100 is obtained.

[0051] The first moving sequence is right-shifted according to the number of bits of the second marking sequence segment to obtain a second moving sequence, and the second moving sequence is ANDed with the third bit range screening sequence to obtain a third marking sequence segment. In one embodiment of the present application, the third bit range screening sequence is used to screen the values ​​of the third bit range, and the bit range screening sequence corresponding to the bit range (bit20-bit14) is 00000000000000000000001111111 as the third bit range screening sequence, and the preset binary sequence is 01100101110010001011000101001 as an example, the first moving sequence is right-shifted according to the number of bits of the second marking sequence segment to obtain a second moving sequence 011001011100100, and after the second moving sequence is ANDed with the third bit range screening sequence, the third marking sequence segment 1100100 is obtained.

[0052] The second moving sequence is right-shifted according to the number of bits of the third marking sequence segment to obtain a third moving sequence, and the third moving sequence is ANDed with the fourth bit range screening sequence to obtain a fourth marking sequence segment. In one embodiment of the present application, the preset base sequence is obtained by splicing the first marking sequence segment, the second marking sequence segment, the third marking sequence segment and the fourth marking sequence segment in bit order, and the fourth bit range screening sequence is used to screen the numerical value of the fourth bit range. Taking the bit range screening sequence 0000000000000000000000001111111 corresponding to the bit range (bit28-bit21) as the fourth bit range screening sequence and the preset base sequence of 01100101110010001011000101001 as an example, the second moving sequence is right shifted according to the number of bits of the third marking sequence segment to obtain a third moving sequence 01100101, and after the third moving sequence is ANDed with the fourth bit range screening sequence, the fourth marking sequence segment 01100101 is obtained.

[0053] In one embodiment of the present application, if the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, the process of determining the target frequency division factor of the phase-locked loop by combining multiple initial frequency division factors includes:

[0054] Multiple fractional frequency division values ​​are added to obtain a sum of fractional frequency division values; and multiple integer frequency division values ​​are added to obtain a sum of integer frequency division values. In one embodiment of the present application, the fractional frequency division values ​​corresponding to each mark sequence segment are added to obtain a sum of fractional frequency division values, and the integer frequency division values ​​corresponding to each mark sequence segment are added to obtain a sum of integer frequency division values.

[0055] The sum of the decimal frequency division values ​​is compared with the preset decimal frequency division threshold, and the target frequency division factor is determined according to the comparison result, the sum of the decimal frequency division values, and the sum of the integer frequency division values. In one embodiment of the present application, the preset decimal frequency division threshold is the overflow value of the decimal frequency division value. When a 24-bit binary sequence is used to represent the decimal frequency division value, the overflow value of the decimal frequency division value is 16777216. When the sum of the decimal frequency division values ​​is less than the preset decimal frequency division threshold, it is determined that the sum of the decimal frequency division values ​​has not overflowed; when the sum of the decimal frequency division values ​​is greater than or equal to the preset decimal frequency division threshold, it is determined that the sum of the decimal frequency division values ​​has overflowed, and according to the overflow of the sum of the decimal frequency division values, the target frequency division factor is determined to improve the accuracy of the target frequency division factor.

[0056] In one embodiment of the present application, the process of determining the target frequency division factor according to the comparison result, the sum of the fractional frequency division values, and the sum of the integer frequency division values ​​includes:

[0057] If the sum of the fractional frequency division values ​​is less than the preset fractional frequency division threshold, the sum of the fractional frequency division values ​​is used as the target fractional frequency division value; the sum of the integer frequency division values ​​is used as the target integer frequency division value; and the target fractional frequency division value and the target integer frequency division value are used as the target frequency division factor. In one embodiment of the present application, if the sum of the fractional frequency division values ​​is less than the preset fractional frequency division threshold, it is determined that the sum of the fractional frequency division values ​​has not overflowed, and there is no need to adjust the sum of the fractional frequency division values ​​and the sum of the integer frequency division values. Therefore, the sum of the fractional frequency division values ​​and the sum of the integer frequency division values ​​are used as the target frequency division factor.

[0058] If the sum of the fractional frequency division values ​​is greater than or equal to the preset fractional frequency division threshold, the difference between the sum of the fractional frequency division values ​​and the preset fractional frequency division threshold is used as the target fractional frequency division value; the sum of the sum of the integer frequency division values ​​and the preset integer frequency division threshold is used as the target integer frequency division value; and the target fractional frequency division value and the target integer frequency division value are used as the target frequency division factor. In one embodiment of the present application, the preset integer frequency division threshold can be set to 1 or other values, which are not specifically limited here. If the sum of the fractional frequency division values ​​is greater than or equal to the preset fractional frequency division threshold, it is determined that the sum of the fractional frequency division values ​​overflows, and the sum of the fractional frequency division values ​​and the sum of the integer frequency division values ​​need to be adjusted. Therefore, the adjusted sum of the fractional frequency division values ​​and the adjusted sum of the integer frequency division values ​​are used as the target frequency division factor, thereby improving the accuracy of the target frequency division factor.

[0059] In one embodiment of the present application, if the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, before determining a plurality of initial frequency division factors of the phase-locked loop based on each marking sequence segment, the method for determining a frequency configuration value of the phase-locked loop further includes:

[0060] According to each bit range, different preset sequence segments are accumulated to obtain multiple accumulated sequence segments. In one embodiment of the present application, taking the bit range (bit6-bit0) as an example, different preset sequence segments are accumulated to obtain 128 accumulated sequence segments, and a part of the 128 accumulated sequence segments is selected for illustration, and the selected part of the accumulated sequence segments is shown in the following table:

[0061] Table 2

[0062] Lookup table serial number value Accumulate sequence segment <![CDATA[F VCO Value (decimal)]]> Frequency value (Hz) FRAC_1 0 0 0 0 0 1 0000001 1 10 3 2 0000010 2 20 7 3 0000011 3 30 10 4 0000100 4 40 13 5 0000101 5 50 17 6 0000110 6 60 20 7 0000111 7 70 23 8 0001000 8 80 27 9 0001001 9 90 30 10 0001010 10 100 34 11 0001011 11 110 37 12 0001100 12 120 40 13 0001101 13 130 44 14 0001110 14 140 47 15 0001111 15 150 50 16 0010000 16 160 54 17 0010001 17 170 57 18 0010010 18 180 60

[0063] In Table 2, the decimal value of the accumulated sequence segment is VCO The value is consistent, the decimal value of the accumulated sequence segment is consistent with the table lookup number value, and the frequency value is F VCOSince the preset phase-locked frequency is 50MHz and the frequency values ​​corresponding to the 128 accumulated sequence segments are all less than 50MHz when the bit range is (bit6-bit0), the integer division value is 0. It is only necessary to calculate the fractional division value of the phase-locked loop and define the fractional division value in Table 2 as FRAC_1. FRAC_1 is the frequency value of the phase-locked loop when the preset phase-locked frequency is 50MHz, the integer division value is 0, and different F VCO In the case of a value, the fractional frequency value is calculated by formula (2).

[0064] Taking the bit range (bit13-bit7) as an example, different preset sequence segments are accumulated to obtain 128 accumulated sequence segments. A part of the 128 accumulated sequence segments is selected for illustration. The selected part of the accumulated sequence segments is shown in the following table:

[0065] Table 3

[0066]

[0067] In Table 3, the decimal value of the accumulated sequence segment is consistent with the table lookup sequence value, F VCO The value is 128 times the decimal value of the accumulated sequence segment, and the frequency value is F VCO Since the preset phase-locked frequency is 50MHz, the frequency values ​​corresponding to the 128 accumulated sequence segments are all less than 50MHz when the bit range is (bit13-bit7). Therefore, the integer division value is 0. It is only necessary to calculate the fractional division value of the phase-locked loop, and define the fractional division value in Table 3 as FRAC_2. FRAC_2 is the frequency value of the phase-locked loop when the preset phase-locked frequency is 50MHz, the integer division value is 0, and different F VCO In the case of a value, the fractional frequency value is calculated by formula (2).

[0068] Taking the bit range of (bit20-bit14) as an example, different preset sequence segments are accumulated to obtain 128 accumulated sequence segments. A part of the 128 accumulated sequence segments is selected for illustration. The selected part of the accumulated sequence segments is shown in the following table:

[0069] Table 4

[0070] Lookup table serial number value Accumulate sequence number <![CDATA[F VCO Value (decimal)]]> Frequency value (kHz) FRAC_3 0 0 0*2^14 0 0 1 0000001 1*2^14 163.84 54976 2 0000010 2*2^14 327.68 109951 3 0000011 3*2^14 491.52 164927 4 0000100 4*2^14 655.36 219902 5 0000101 5*2^14 819.2 274878 6 0000110 6*2^14 983.04 329853 7 0000111 7*2^14 1146.88 384829 8 0001000 8*2^14 1310.72 439805 9 0001001 9*2^14 1474.56 494780 10 0001010 10*2^14 1638.4 549756 11 0001011 11*2^14 1802.24 604731 12 0001100 12*2^14 1966.08 659707 13 0001101 13*2^14 2129.92 714683 14 0001110 14*2^14 2293.76 769658 15 0001111 15*2^14 2457.6 824634 16 0010000 16*2^14 2621.44 879609 17 0010001 17*2^14 2785.28 934585 18 0010010 18*2^14 2949.12 989560 19 0010011 19*2^14 3112.96 1044536 20 0010100 20*2^14 3276.8 1099512 21 0010101 21*2^14 3440.64 1154487 22 0010110 22*2^14 3604.48 1209463 23 0010111 23*2^14 3768.32 1264438 24 0011000 24*2^14 3932.16 1319414 25 0011001 25*2^14 4096 1374390 26 0011010 26*2^14 4259.84 1429365 27 0011011 27*2^14 4423.68 1484341 28 0011100 28*2^14 4587.52 1539316 29 0011101 29*2^14 4751.36 1594292 30 0011110 30*2^14 4915.2 1649267

[0071] In Table 4, the decimal value of the accumulated sequence segment is consistent with the table lookup sequence value, F VCO The value is 16384 times the decimal value of the accumulated sequence segment, and the frequency value is F VCOSince the preset phase-locked frequency is 50MHz and the frequency values ​​corresponding to the 128 accumulated sequence segments are all less than 50MHz when the bit range is (bit20-bit14), the integer division value is 0. It is only necessary to calculate the fractional division value of the phase-locked loop and define the fractional division value in Table 4 as FRAC_3. FRAC_3 is the frequency value corresponding to the preset phase-locked frequency of 50MHz, the integer division value of 0, and different F VCO In the case of a value, the fractional frequency value is calculated by formula (2).

[0072] Taking the bit range of (bit28-bit21) as an example, different preset sequence segments are accumulated and the maximum frequency of the frequency modulation source is used as a limit to obtain 144 accumulated sequence segments. A part of the 144 accumulated sequence segments is selected for description. The selected part of the accumulated sequence segments is shown in the following table:

[0073] Table 5

[0074] Lookup sequence value Accumulate sequence number <![CDATA[F VCO Value (decimal)]]> Frequency value (MHz) FRAC_4 N_1 0 0 0*2^21 0 0 0 1 00000001 1*2^21 20.97152 7036874 0 2 00000010 2*2^21 41.94304 14073749 0 3 00000011 3*2^21 62.91456 4333407 1 4 00000100 4*2^21 83.88608 11370282 1 5 00000101 5*2^21 104.8576 1629940 2 6 00000110 6*2^21 125.8291 8666815 2 7 00000111 7*2^21 146.8006 15703689 2 8 00001000 8*2^21 167.7722 5963347 3 9 00001001 9*2^21 188.7437 13000222 3 10 00001010 10*2^21 209.7152 3259880 4 11 00001011 11*2^21 230.6867 10296755 4 12 00001100 12*2^21 251.6582 556413 5 13 00001101 13*2^21 272.6298 7593287 5 14 00001110 14*2^21 293.6013 14630162 5 15 00001111 15*2^21 314.5728 4889820 6 16 00010000 16*2^21 335.5443 11926695 6 17 00010001 17*2^21 356.5158 2186353 7 18 00010010 18*2^21 377.4874 9223228 7 19 00010011 19*2^21 398.4589 16260102 7 20 00010100 20*2^21 419.4304 6519760 8 21 00010101 21*2^21 440.4019 13556635 8 22 00010110 22*2^21 461.3734 3816293 9 23 00010111 23*2^21 482.345 10853168 9 24 00011000 24*2^21 503.3165 1112826 10 25 00011001 25*2^21 524.288 8149700 10 26 00011010 26*2^21 545.2595 15186575 10 27 00011011 27*2^21 566.231 5446233 11 28 00011100 28*2^21 587.2026 12483108 11

[0075] In Table 5, the decimal value of the accumulated sequence segment is consistent with the table lookup sequence value, F VCO The value is 2097152 times the decimal value of the accumulated sequence segment, and the frequency value is F VCO Since the frequency value in Table 5 may be greater than the preset phase-locking frequency 50MHz, it is necessary to calculate the integer division value and the fractional division value, and define the fractional division value in Table 5 as FRAC_4, and the integer division value as N_1, where N_1 is the preset phase-locking frequency 50MHz and different F VCO The integer frequency division value calculated by formula (1) under the condition of the preset phase detection frequency of 50MHz, different integer frequency division values, and different F VCO In the case of a value, the fractional frequency value is calculated by formula (2).

[0076] Based on the value of each accumulated sequence segment and the preset phase detection frequency, the fractional frequency division value and the integer frequency division value of each accumulated sequence segment are calculated. In one embodiment of the present application, if the bit range of the accumulated sequence segment is (bit6-bit0), the accumulated sequence segment is converted into a decimal value, and the decimal value (F VCO value), the preset phase-locked frequency is substituted into formula (1), and the integer frequency division value of the cumulative sequence segment is calculated; after the integer frequency division value of the cumulative sequence segment is obtained, the integer frequency division value of the cumulative sequence segment and the decimal value (F VCOvalue), the preset phase-locking frequency is substituted into formula (2) to calculate the fractional frequency value of the cumulative sequence segment; if the bit range of the cumulative sequence segment is (bit13-bit7), the cumulative sequence segment is converted into a decimal value, and the decimal value of the cumulative sequence segment is multiplied by 128 to obtain the F of the cumulative sequence segment. VCO value, the F of the accumulated sequence segment VCO Substitute the value and the preset phase-locking frequency into formula (1) to calculate the integer frequency division value of the cumulative sequence segment; after obtaining the integer frequency division value of the cumulative sequence segment, the integer frequency division value of the cumulative sequence segment and the F of the cumulative sequence segment are added. VCO Substitute the value and the preset phase-locking frequency into formula (2) to calculate the fractional frequency value of the cumulative sequence segment; if the bit range of the cumulative sequence segment is (bit20-bit14), the cumulative sequence segment is converted into a decimal value, and the decimal value of the cumulative sequence segment is multiplied by 16384 to obtain the F of the cumulative sequence segment. VCO value, the F of the accumulated sequence segment VCO Substitute the value and the preset phase-locking frequency into formula (1) to calculate the integer frequency division value of the cumulative sequence segment; after obtaining the integer frequency division value of the cumulative sequence segment, the integer frequency division value of the cumulative sequence segment and the F of the cumulative sequence segment are added. VCO Substitute the value and the preset phase-locking frequency into formula (2) to calculate the fractional frequency value of the cumulative sequence segment; if the bit range of the cumulative sequence segment is (bit28-bit21), the cumulative sequence segment is converted into a decimal value, and the decimal value of the cumulative sequence segment is multiplied by 2097152 to obtain the F of the cumulative sequence segment. VCO value, the F of the accumulated sequence segment VCO Substitute the value and the preset phase-locking frequency into formula (1) to calculate the integer frequency division value of the cumulative sequence segment; after obtaining the integer frequency division value of the cumulative sequence segment, the integer frequency division value of the cumulative sequence segment and the F of the cumulative sequence segment are added. VCO The value and the preset phase-locked frequency are substituted into formula (2) to calculate the fractional frequency division value of the accumulated sequence segment. After obtaining the integer frequency division value and the fractional frequency division value of the accumulated sequence segment, a one-to-one correspondence between the accumulated sequence segment and the integer frequency division value is established, and a one-to-one correspondence between the accumulated sequence segment and the fractional frequency division value is established to meet the requirement of determining the initial frequency division factor of the phase-locked loop by comparing the marked sequence segment with the accumulated sequence segment.

[0077] In one embodiment of the present application, the process of determining a plurality of initial frequency division factors of a phase-locked loop based on each marking sequence segment includes:

[0078] A marking sequence segment is selected as a target marking sequence segment, and the target marking sequence segment is compared with an accumulated sequence segment belonging to the same bit range; if the target marking sequence segment is successfully compared with any accumulated sequence segment belonging to the same bit range, the fractional frequency division value of the arbitrary accumulated sequence segment is used as a fractional frequency division value of the phase-locked loop; the integer frequency division value of the arbitrary accumulated sequence segment is used as an integer frequency division value of the phase-locked loop. In one embodiment of the present application, the marking sequence segment is compared with an accumulated sequence segment belonging to the same bit range, and if the marking sequence segment is successfully compared with any accumulated sequence segment belonging to the same bit range, the integer frequency division value of the arbitrary accumulated sequence segment is used as an integer frequency division value of the phase-locked loop, and the fractional frequency division value of the arbitrary accumulated sequence segment is used as a fractional frequency division value of the phase-locked loop.

[0079] Another marking sequence segment is selected as the update marking sequence segment, and the update marking sequence segment is compared with the cumulative sequence segment belonging to the same bit range; if the update marking sequence segment is successfully compared with any cumulative sequence segment belonging to the same bit range, the fractional frequency division value of any cumulative sequence segment is used as a fractional frequency division value of the phase-locked loop; the integer frequency division value of any cumulative sequence segment is used as an integer frequency division value of the phase-locked loop, until each marking sequence segment is compared with multiple cumulative sequence segments, and multiple integer frequency division values ​​and multiple fractional frequency division values ​​of the phase-locked loop are obtained. In one embodiment of the present application, other marking sequence segments are continuously compared with the cumulative sequence segments belonging to the same bit range until all marking sequence segments find corresponding integer frequency division values ​​and fractional frequency division values.

[0080] In one embodiment of the present application, the preset base sequence is divided into 4 segments, and the integer frequency division value and the decimal frequency division value corresponding to each marked sequence segment are calculated respectively. After analysis and judgment, the target decimal frequency division value has a truncation error of at most 2 (according to the round-up algorithm, each truncation error is less than 0.5. When divided into 4 segments, the maximum truncation error is 2). The truncation error 2 is converted into a frequency error of 6Hz, which meets the requirement of being less than the preset step frequency of 10Hz. After the preset base sequence is divided into 4 segments, it can be seen from Tables 2 to 4 that the total frequency value obtained by adding up the frequency values ​​corresponding to the marked sequence segments in Tables 2 to 4 is less than 50MHz (indicating that the decimal frequency division value accumulated from Tables 2 to 4 will not overflow). Therefore, the decimal frequency division value accumulated from Tables 2 to 5 will only overflow once at most. The data of Tables 2 to 5 are stored in the FPGA or MCU, and any F is calculated later. VCO When the corresponding integer division value and decimal division value are obtained, the target integer division value and the target decimal division value are determined by table lookup and shift operation, AND operation, conditional judgment and addition and subtraction operation, without floating point and multiplication and division operations.

[0081] In one embodiment of the present application, taking the example of a user controlling the frequency hopping source to hop to a frequency of 2134.56425 MHz, the F VCO The value is 213456425, which is represented by a 29-bit binary number in a digital processor, namely 01100101110010001011000101001. First, directly substitute 213456425 into formula (1) to obtain the following calculation result:

[0082] N=floor((213456425*10Hz) / 50000000Hz)=floor(42.691285)=42

[0083] Formula (3)

[0084] Substituting 213456425 and 42 directly into formula (2), we get the following result: F = INT ((((213456425*10Hz)-42*50000000Hz) / 50000000Hz)*16777216)

[0085] =INT(11597837.76256)=11597838 Formula (4)

[0086] Then, the method for determining the frequency configuration value of the phase-locked loop of the present application is operated as follows: (1) In the bit range (bit6-bit0), (bit13-bit7), (bit20-bit14) and (bit28-bit21), 01100101110010001011000101001 is divided into the mark point sequence segments 0101001, 0101100,

[0087] 1100100 and 01100101, the decimal value corresponding to 0101001 is 41. Find the lookup number value 41 in Table 2, and you can determine that the value of FRAC_1 is 138 (decimal). The decimal value corresponding to 0101100 is 44. Find the lookup number value 44 in Table 3, and you can determine that the value of FRAC_2 is 18898 (decimal). The decimal value corresponding to 1100100 is 100. Find the lookup number value 100 in Table 4, and you can determine that the value of FRAC_3 is 5497558 (decimal). The decimal value corresponding to 01100101 is 101. Find the lookup number value 101 in Table 5, and you can get the value of FRAC_4 is 6081244 (decimal), and the value of N_1 is 42 (decimal). Add FRAC_1, FRAC_2, FRAC_3, and FRAC_4, that is, the sum of 138, 18898, 5497558, and 6081244 is equal to 11597838. Since 11597838 is less than 16777216, it means that the accumulated fractional frequency division value has not overflowed and no carry is required. Then the target integer frequency division value is 42, and the target fractional frequency division value is 11597838. By comparison, the target frequency division factor directly calculated by formula (1) and formula (2) is consistent with the target frequency division factor obtained by the method for determining the frequency configuration value of the phase-locked loop of the present application, thereby verifying the accuracy and effectiveness of the method for determining the frequency configuration value of the phase-locked loop of the present application.

[0088] In one embodiment of the present application, the integer frequency division value and the decimal frequency division value of 150 million frequency points are simplified to the data of 528 frequency points for advance calculation and storage through the phase-locked loop frequency configuration value determination method of the present application. Then, the integer frequency division value calculation and the decimal frequency division value calculation of any preset step frequency point are completed by table lookup and simple shift operation, AND operation, addition and subtraction operation and conditional judgment. After obtaining the frequency control data, in the process of determining the phase-locked loop frequency configuration value, no floating point and multiplication and division operations are required. And the frequency error caused by the truncation error is less than 6Hz, which meets the requirement of less than the preset step frequency of 10Hz. At the same time, for different application situations, the segmentation can be adapted according to actual needs, which improves the application demand for small step frequency source (step frequency is less than the preset step frequency).

[0089] In one embodiment of the present application, the frequency error caused by truncation error needs to be eliminated by increasing the number of bits of precision calculated for each marker sequence segment while considering the amount of data storage and the amount of computation for subsequent data processing, so as to meet the various application requirements of different application scenarios.

[0090] In one embodiment of the present application, the storage space required for the target integer division value and the target fractional division value is reduced by a method for determining a phase-locked loop frequency configuration value, and after obtaining the frequency control information, only simple digital logic and integer addition and subtraction operations are required to determine the frequency configuration value of the small-step phase-locked loop register, thereby overcoming the problems of low-cost, small-volume, low-power FPGA or MCU not supporting floating-point and multiplication and division operations, limited self-integrated storage space or slow floating-point operations, and can be widely used in small-step frequency hopping source circuits.

[0091] The following describes an apparatus embodiment of the present application, which can be used to execute the method for determining the frequency configuration value of a phase-locked loop in the above-mentioned embodiment of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the embodiment of the method for determining the frequency configuration value of a phase-locked loop in the above-mentioned embodiment of the present application.

[0092] Figure 3 is a block diagram of a phase-locked loop frequency configuration value determination device shown in an exemplary embodiment of the present application. The device can be applied to Figure 1 The implementation environment shown in the figure is specifically configured in the computer device 101. The device can also be applied to other exemplary implementation environments and specifically configured in other devices. This embodiment does not limit the implementation environment to which the device is applied.

[0093] like Figure 3 As shown, the exemplary phase-locked loop frequency configuration value determining device includes:

[0094] The data acquisition module 301 is used to acquire the frequency control data of the frequency hopping source.

[0095] The sequence division module 302 is used to convert the frequency control data into a preset base sequence, and divide the preset base sequence into a plurality of mark sequence segments.

[0096] The factor determination module 303 is used to determine a plurality of initial frequency division factors of the phase-locked loop based on each marker sequence segment.

[0097] The configuration value determination module 304 is used to determine a target frequency division factor of the phase-locked loop by combining multiple initial frequency division factors, and use the target frequency division factor as a frequency configuration value.

[0098] In one embodiment of the present application, the frequency control data is sent down by the user, and the frequency range of the frequency hopping source is 1500MHz to 3000MHz.

[0099] In one embodiment of the present application, the preset base sequence is obtained by accumulating different preset sequence segments; the preset sequence segments are used to represent the preset frequency points of the frequency hopping source; the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency, the preset step frequency is 10 Hz, and the preset base sequence is a binary sequence. For example, if the user wants to control the frequency hopping source to hop to the frequency point of 2134.56425 MHz, the F VCO The value is 213456425, which is represented by a binary number in a digital processor, i.e. 01100101110010001011000101001 (29 bits binary). Then, taking the division into 4 mark sequence segments as an example, the preset base sequence 01100101110010001011000101001 is divided into four sequence segments 01100101, 1100100, 0101100 and 0101001 in order from high bit to low bit. Different preset sequence segments are shown in Table 1. In Table 1, 29 bits of binary data are expanded bit by bit. When each bit is 1, it represents a different frequency point. When different bits are 1, the corresponding frequency points are accumulated to represent the frequency point to which the user wants to control the frequency hopping source to hop. For example, the preset sequence segment with bit 0 being 1 and the preset sequence segment with bit 1 being 1 are accumulated to obtain a new sequence segment 0000000000000000000000000000011. The frequency point represented by the new sequence segment is 30 Hz, and the decimal value 3 of 00000000000000000000000000011 is FVCO. If the integer frequency division value and the decimal frequency division value are calculated separately according to the frequency of each bit, the integer frequency division value and the decimal frequency division value corresponding to each bit can be obtained. The integer frequency division value and the decimal frequency division value corresponding to each bit are stored in a table. Then, when the frequency hopping source module is working, the integer frequency division value and the decimal frequency division value corresponding to each bit are found by looking up the table. Then, the integer frequency division value and the decimal frequency division value of each bit are accumulated to obtain the final integer frequency division value and the final decimal frequency division value corresponding to the frequency control data. Thus, the frequency control data represented by the binary sequence is split bit by bit, and then the integer frequency division value and the decimal frequency division value are calculated separately, instead of calculating the integer frequency division value and the decimal frequency division value according to each preset step frequency point, which can greatly reduce the amount of calculation and storage of the decimal frequency division value and the integer frequency division value.

[0100] In one embodiment of the present application, the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, and each marking sequence segment has a corresponding fractional frequency division value and an integer frequency division value. Therefore, after obtaining each marking sequence segment, multiple fractional frequency division values ​​and multiple integer frequency division values ​​can be determined by comparison.

[0101] In one embodiment of the present application, frequency control data of a frequency hopping source is obtained, the frequency control data is converted into a preset base sequence, and the preset base sequence is divided into a plurality of mark sequence segments, and a plurality of initial frequency division factors of a phase-locked loop are determined based on each mark sequence segment, and a target frequency division factor of the phase-locked loop is determined in combination with the plurality of initial frequency division factors, and the target frequency division factor is used as a frequency configuration value. In the above process, in the process of determining the frequency configuration value of the phase-locked loop after the frequency control data is obtained, floating-point operations and multiplication and division operations do not need to be performed directly, which reduces the complexity of operations in the process of determining the frequency configuration value of the phase-locked loop after the frequency control data is obtained, thereby reducing the time spent on operations in the process of determining the frequency configuration value of the phase-locked loop after the frequency control data is obtained, and does not require the use of a high-performance digital processor or an additional storage device, and has the advantages of low cost, The characteristics of small size and low power consumption; in addition, since the accumulated sequence segments are obtained by adding different preset sequence segments, the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source, and the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency. Therefore, in the process of calculating the decimal division values ​​and integer division values ​​of all accumulated sequence segments, it is not necessary to calculate the decimal division values ​​and integer division values ​​of each preset step frequency, but only calculate the decimal division values ​​and integer division values ​​for the frequency points corresponding to the accumulated sequence segments, which greatly reduces the data volume and storage volume of the decimal division values ​​and the integer division values, not only improves the calculation efficiency of the decimal division values ​​and the integer division values, but also reduces the storage pressure of the FPGA or MCU, as well as the table lookup time of the decimal division values ​​and the integer division values, improves the working efficiency of the phase-locked loop, and better meets user needs.

[0102] It should be noted that the phase-locked loop frequency configuration value determination device provided in the above embodiment and the phase-locked loop frequency configuration value determination method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment, and will not be repeated here. In practical applications, the phase-locked loop frequency configuration value determination device provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0103] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by one or more processors, the electronic device implements the phase-locked loop frequency configuration value determination method provided in the above-mentioned embodiments.

[0104] Figure 4 The structure diagram of the computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that: Figure 4The computer system 400 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0105] like Figure 4 As shown, the computer system 400 includes a central processing unit (CPU) 401, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 402 or the program loaded from the storage part 408 to the random access memory (RAM) 403, such as executing the method in the above embodiment. In the RAM 403, various programs and data required for system operation are also stored. The CPU 401, ROM 402 and RAM 403 are connected to each other through a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0106] The following components are connected to the I / O interface 405: an input section 406 including a keyboard, a mouse, etc.; an output section 407 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to the I / O interface 405 as needed. A removable medium 411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 410 as needed so that a computer program read therefrom is installed into the storage section 408 as needed.

[0107] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 409, and / or installed from a removable medium 411. When the computer program is executed by a central processing unit (CPU) 401, various functions defined in the system of the present application are executed.

[0108] It should be noted that the computer-readable medium shown in the embodiment of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. This propagated data signal can take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0109] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0110] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0111] Another aspect of the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of a computer, causes the computer to execute the above-mentioned method for determining a phase-locked loop frequency configuration value. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0112] Another aspect of the present application also provides a computer program product or a computer program, the computer program product or the computer program includes a computer instruction, the computer instruction is stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method for determining the phase-locked loop frequency configuration value provided in each of the above embodiments.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for determining a phase-locked loop frequency configuration value, characterized in that: The method comprises: Obtain frequency control data of the frequency hopping source; The frequency control data is converted into a preset base sequence, and the preset base sequence is divided into a plurality of mark sequence segments; the preset base sequence is obtained by accumulating different preset sequence segments; the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source; the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency; Based on each of the marking sequence segments, determining a plurality of initial frequency division factors of the phase-locked loop; The target frequency division factor of the phase-locked loop is determined by combining the multiple initial frequency division factors, and the target frequency division factor is used as the frequency configuration value.

2. The method for determining a phase-locked loop frequency configuration value according to claim 1, characterized in that: The process of dividing the preset binary sequence into a plurality of marked sequence segments comprises: According to a preset segmentation threshold, a plurality of bit ranges of the preset binary sequence are determined, and a bit range screening sequence is determined according to each bit range to obtain a plurality of the bit range screening sequences; Performing AND operations on the plurality of bit range screening sequences and the preset base sequence respectively, to obtain a plurality of the marking sequence segments.

3. The method for determining the frequency configuration value of a phase-locked loop according to claim 2, characterized in that: If the plurality of bit range screening sequences include a first bit range screening sequence, a second bit range screening sequence, a third bit range screening sequence, and a fourth bit range screening sequence, then performing AND operations on the plurality of bit range screening sequences and the preset base sequence respectively to obtain a plurality of marking sequence segments includes: Performing an AND operation on the preset base sequence and the first bit range screening sequence to obtain a first marking sequence segment; Shifting the preset base sequence right according to the number of bits of the first marking sequence segment to obtain a first shift sequence, and performing an AND operation on the first shift sequence and the second bit range screening sequence to obtain a second marking sequence segment; Right-shift the first moving sequence according to the number of bits of the second marking sequence segment to obtain a second moving sequence, and perform an AND operation on the second moving sequence and the third bit range screening sequence to obtain a third marking sequence segment; The second moving sequence is right-shifted according to the number of bits of the third marking sequence segment to obtain a third moving sequence, and the third moving sequence is ANDed with the fourth bit range screening sequence to obtain a fourth marking sequence segment; the preset base sequence is obtained by splicing the first marking sequence segment, the second marking sequence segment, the third marking sequence segment and the fourth marking sequence segment in bit order.

4. The method for determining a phase-locked loop frequency configuration value according to any one of claims 1 to 3, characterized in that: If the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, the process of determining the target frequency division factor of the phase-locked loop by combining a plurality of the initial frequency division factors includes: Adding a plurality of the fractional frequency division values ​​to obtain a sum of the fractional frequency division values; and adding a plurality of the integer frequency division values ​​to obtain a sum of the integer frequency division values; The sum of the fractional frequency division values ​​is compared with a preset fractional frequency division threshold, and the target frequency division factor is determined according to the comparison result, the sum of the fractional frequency division values, and the sum of the integer frequency division values.

5. The method for determining the frequency configuration value of a phase-locked loop according to claim 4, characterized in that: The process of determining the target frequency division factor according to the comparison result, the sum of the fractional frequency division values, and the sum of the integer frequency division values ​​includes: If the sum of the fractional frequency division values ​​is less than the preset fractional frequency division threshold, the sum of the fractional frequency division values ​​is used as the target fractional frequency division value; the sum of the integer frequency division values ​​is used as the target integer frequency division value; and the target fractional frequency division value and the target integer frequency division value are used as the target frequency division factor; If the sum of the fractional frequency division values ​​is greater than or equal to the preset fractional frequency division threshold, the difference between the sum of the fractional frequency division values ​​and the preset fractional frequency division threshold is used as the target fractional frequency division value; the sum of the sum of the integer frequency division values ​​and the preset integer frequency division threshold is used as the target integer frequency division value; and the target fractional frequency division value and the target integer frequency division value are used as the target frequency division factor.

6. The method for determining a phase-locked loop frequency configuration value according to claim 2, characterized in that: If the initial frequency division factor includes a fractional frequency division value and an integer frequency division value, before determining a plurality of initial frequency division factors of the phase-locked loop based on each marking sequence segment, the method further includes: Accumulating different preset sequence segments according to each bit range to obtain multiple accumulated sequence segments; Based on the value of each accumulated sequence segment and the preset phase-locking frequency, the fractional frequency division value and the integer frequency division value of each accumulated sequence segment are calculated.

7. The method for determining a phase-locked loop frequency configuration value according to claim 6, characterized in that: The process of determining a plurality of initial frequency division factors of a phase-locked loop based on each marker sequence segment includes: A marking sequence segment is selected as a target marking sequence segment, and the target marking sequence segment is compared with an accumulation sequence segment belonging to the same bit range; if the target marking sequence segment is successfully compared with any accumulation sequence segment belonging to the same bit range, a fractional frequency division value of the arbitrary accumulation sequence segment is used as a fractional frequency division value of the phase-locked loop; an integer frequency division value of the arbitrary accumulation sequence segment is used as an integer frequency division value of the phase-locked loop; Another marking sequence segment is selected as an update marking sequence segment, and the update marking sequence segment is compared with the accumulation sequence segments belonging to the same bit range; if the update marking sequence segment is successfully compared with any accumulation sequence segment belonging to the same bit range, the fractional frequency division value of the arbitrary accumulation sequence segment is used as a fractional frequency division value of the phase-locked loop; the integer frequency division value of the arbitrary accumulation sequence segment is used as an integer frequency division value of the phase-locked loop, until each marking sequence segment is compared with multiple accumulation sequence segments, so as to obtain multiple integer frequency division values ​​and multiple fractional frequency division values ​​of the phase-locked loop.

8. A device for determining a frequency configuration value of a phase-locked loop, characterized in that: The device comprises: A data acquisition module, used to acquire frequency control data of a frequency hopping source; A sequence division module, used for converting the frequency control data into a preset base sequence, and dividing the preset base sequence into a plurality of marked sequence segments; the preset base sequence is obtained by accumulating different preset sequence segments; the preset sequence segments are used to characterize the preset frequency points of the frequency hopping source; the frequency difference between adjacent preset frequency points is greater than or equal to the preset step frequency; A factor determination module, used for determining a plurality of initial frequency division factors of a phase-locked loop based on each marking sequence segment; The configuration value determination module is used to determine a target frequency division factor of the phase-locked loop by combining the multiple initial frequency division factors, and use the target frequency division factor as the frequency configuration value.

9. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the method for determining the frequency configuration value of a phase-locked loop as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that: include: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the method for determining a frequency configuration value of a phase-locked loop according to any one of claims 1 to 7.

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