Circuit and method for improving stable work of phase-locked loop

Abstract

The invention discloses a circuit and a method for improving stable operation of a phase-locked loop, belongs to the technical field of electronics, and mainly solves the technical problem of unstable operation of the phase-locked loop when the sequence of power-on operation of the phase-locked loop and input of a reference clock is not constant. The circuit comprises a phase-locked loop, a one-to-two power divider of which one output end is connected with the phase-locked loop and which is used for dividing a reference clock into two paths, a detector of which the input end is connected with the other output end of the one-to-two power divider, and a comparator of which the input end is connected with the output end of the detector, the FPGA control module is connected with the output end of the comparator and the phase-locked loop, and the power supply module supplies power to the phase-locked loop and the FPGA control module. According to the invention, the analog switch is controlled to switch on the phase-locked loop through the FPGA, the register is configured for the phase-locked loop, and the working stability of the phase-locked loop is improved.

Description

Technical Field

[0001] The invention belongs to the field of electronic technology, and in particular relates to a circuit and a method for improving the stable operation of a phase-locked loop. Background Art

[0002] Frequency source is the basic signal source of electronic system. In modern electronic technology, the system is becoming more and more complex. The system cannot evaluate the timing between the power-on of the phase-locked loop and the reference clock input. The timing between the power-on of the phase-locked loop and the reference clock input is not constant, which can easily cause the timing to be disordered when the FPGA configures the registers for the phase-locked loop, resulting in unstable operation of the phase-locked loop and loss of lock. There is an urgent need for a method to improve the stability of the phase-locked loop. Summary of the invention

[0003] The purpose of the present invention is to provide a circuit and method for improving the stable operation of a phase-locked loop, mainly to solve the technical problem that the phase-locked loop is unstable when the sequence between the power-on operation of the phase-locked loop and the reference clock input is not constant.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is as follows: A circuit for improving the stable operation of a phase-locked loop comprises a phase-locked loop, and also comprises a one-to-two power divider whose output end is connected to the phase-locked loop and is used to divide the power of a reference clock into two paths, a detector whose input end is connected to the other output end of the one-to-two power divider, a comparator whose input end is connected to the output end of the detector, an FPGA control module connected to the output end of the comparator and to the phase-locked loop, and a power supply module for supplying power to the phase-locked loop and the FPGA control module.

[0005] Furthermore, in the present invention, the power supply module includes a first linear regulator and a second linear regulator of an external input power supply; wherein the output end of the first linear regulator is directly connected to the FPGA control module, and the output end of the second linear regulator is connected to the phase-locked loop after an analog switch; the analog switch is also connected to the FPGA control module.

[0006] Furthermore, in the present invention, the analog switch adopts a single-pole double-throw switch, the input end of the single-pole double-throw switch is connected to the output end of the second linear regulator, the control end of the single-pole double-throw switch is connected to the FPGA control module, one output end of the single-pole double-throw switch is connected to the phase-locked loop, and the other output end of the single-pole double-throw switch is grounded after a resistor R.

[0007] Based on the above circuit, the present invention also provides a method for improving the stable operation of a phase-locked loop, comprising the following steps: S1, using the detector to detect the external input reference clock and transmit the signal to the comparator, the FPGA control module receives the output level of the comparator, if it is a low level, it goes to step S2, if it is a high level, it goes to step S3; S2, FPGA control module output level controls analog switch to power off the phase-locked loop; S3, FPGA control module output level controls analog switch to power the phase-locked loop; S4, the FPGA control module configures the registers for the phase-locked loop to avoid an inconsistent sequence between the phase-locked loop power-on operation and the reference clock input.

[0008] Compared with the prior art, the present invention has the following beneficial effects: The present invention detects an external reference clock input through a detector, and then the FPGA controls the analog switch to power on the phase-locked loop and configure the register for the phase-locked loop, thereby avoiding the problem of phase-locked loop loss of lock due to disordered configuration timing of the phase-locked loop register when the order between the phase-locked loop power-on and the reference clock input is not constant, thereby improving the stability of the phase-locked loop operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is the overall principle block diagram of the present invention.

[0010] Figure 2 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0011] The present invention is further described below in conjunction with the accompanying drawings and embodiments. The embodiments of the present invention include but are not limited to the following embodiments.

[0012] like Figure 1 As shown, the present invention discloses a circuit for improving the stable operation of a phase-locked loop, including a phase-locked loop, and also including a one-to-two power divider whose output end is connected to the phase-locked loop for dividing the reference clock power into two paths, a detector whose input end is connected to the other output end of the one-to-two power divider, a comparator whose input end is connected to the output end of the detector, an FPGA control module connected to the output end of the comparator and connected to the phase-locked loop, and a power supply module for powering the phase-locked loop and the FPGA control module. The external input reference clock power is divided into two paths, one path provides a reference clock signal for the phase-locked loop, and the other path is detected by the detector. The detection level output by the detector is then compared by the comparator, and the output LVTTL level is fed back to the PPGA control module. The external input power supply is stabilized by a linear regulator and then input to an analog switch. The FPGA controls the analog switch to output a voltage to power the phase-locked loop, and the phase-locked loop outputs a signal.

[0013] When the FPGA control module receives a low level output from the comparator, it indicates that there is no reference clock input. The FPGA control module controls the analog switch to power off the phase-locked loop and does not configure the register for the phase-locked loop. When the FPGA receives a high level output from the comparator, it indicates that there is a reference clock input. The FPGA control module controls the analog switch to power on the phase-locked loop and configure the register for the phase-locked loop.

[0014] In this embodiment, the power supply module includes a first linear regulator and a second linear regulator with an external input power supply; wherein the output end of the first linear regulator is directly connected to the FPGA control module, and the output end of the second linear regulator is connected to the phase-locked loop through an analog switch; and the analog switch is also connected to the FPGA control module. The analog switch adopts a single-pole double-throw switch, the input end of the single-pole double-throw switch is connected to the output end of the second linear regulator, the control end of the single-pole double-throw switch is connected to the FPGA control module, one output end of the single-pole double-throw switch is connected to the phase-locked loop, and the other output end of the single-pole double-throw switch is grounded through a resistor R.

[0015] like Figure 2 As shown, based on the above circuit, the present invention also provides a method for improving the stable operation of a phase-locked loop, comprising the following steps: S1, using the detector to detect the external input reference clock and transmit the signal to the comparator, the FPGA control module receives the output level of the comparator, if it is a low level, it goes to step S2, if it is a high level, it goes to step S3; S2, FPGA control module output level controls analog switch to power off the phase-locked loop; S3, FPGA control module output level controls analog switch to power the phase-locked loop; S4, the FPGA control module configures the registers for the phase-locked loop to avoid an inconsistent sequence between the phase-locked loop power-on operation and the reference clock input.

[0016] Through the above design, the present invention detects that there is an external reference clock input through the detector, and the FPGA controls the analog switch to power on the phase-locked loop and configure the register for the phase-locked loop, thereby avoiding the problem of phase-locked loop loss of lock due to disordered configuration timing of the phase-locked loop register when the sequence between the phase-locked loop power-on and the reference clock input is not constant, thereby improving the stability of the phase-locked loop operation.

[0017] The above embodiment is only one of the preferred implementation modes of the present invention and should not be used to limit the protection scope of the present invention. Any changes or modifications that are made to the main design concept and spirit of the present invention and have no substantive significance, and the technical problems they solve are still consistent with the present invention, should be included in the protection scope of the present invention.

Claims

1. A circuit for improving the stable operation of a phase-locked loop, comprising a phase-locked loop, characterized in that: It also includes a one-to-two power divider with an output end connected to a phase-locked loop for dividing the reference clock power into two paths, a detector with an input end connected to another output end of the one-to-two power divider, a comparator with an input end connected to the output end of the detector, an FPGA control module connected to the output end of the comparator and to the phase-locked loop, and a power supply module for supplying power to the phase-locked loop and the FPGA control module.

2. A circuit for improving the stable operation of a phase-locked loop according to claim 1, characterized in that: The power supply module includes a first linear regulator and a second linear regulator for external input power; wherein the output end of the first linear regulator is directly connected to the FPGA control module, and the output end of the second linear regulator is connected to the phase-locked loop after passing through an analog switch; the analog switch is also connected to the FPGA control module.

3. A circuit for improving the stable operation of a phase-locked loop according to claim 2, characterized in that: The analog switch adopts a single-pole double-throw switch, the input end of the single-pole double-throw switch is connected to the output end of the second linear regulator, the control end of the single-pole double-throw switch is connected to the FPGA control module, one output end of the single-pole double-throw switch is connected to the phase-locked loop, and the other output end of the single-pole double-throw switch is grounded after a resistor R.

4. A method for improving the stable operation of a phase-locked loop, characterized in that: A circuit for improving the stable operation of a phase-locked loop as claimed in claim 3 is used. The following steps are involved: S1, using the detector to detect the external input reference clock and transmit the signal to the comparator, the FPGA control module receives the output level of the comparator, if it is a low level, it goes to step S2, if it is a high level, it goes to step S3; S2, FPGA control module output level controls analog switch to power off the phase-locked loop; S3, FPGA control module output level controls analog switch to power the phase-locked loop; S4, the FPGA control module configures the registers for the phase-locked loop to avoid an inconsistent sequence between the phase-locked loop power-on operation and the reference clock input.

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