High-precision frequency source self-adaptive taming method and system based on digital phase locking technology

Abstract

The invention discloses a high-precision frequency source adaptive taming method based on a digital phase-locked technology, and the method comprises the steps: carrying out the phase-locked digital processing of a local frequency source of a high-precision time frequency based on a phase-locked loop digital model, and adjusting the phase of the local frequency source; performing jitter reduction processing on a reference PPS signal generated by a reference frequency source to enable the jitter of the reference PPS signal to be within a preset range; and taming the reference PPS signal subjected to jitter processing to a local frequency source subjected to phase-locked digital processing. According to the invention, the digital phase locking technology is introduced into the frequency source taming system, so that the short-term stability of the system can be ensured, the long-term stability is greatly improved, the phase noise and the signal jitter are reduced, and the strict requirements of various high-precision time frequency applications are finally met.

Description

Technical Field

[0001] The present invention relates to the field of time and frequency technology, and more specifically, to a high-precision frequency source adaptive taming method and system based on digital phase-locked technology. Background Art

[0002] In the field of time and frequency, the stability and accuracy of the frequency source are crucial. With the full development and deployment of the Beidou navigation system, it has become increasingly feasible to use Beidou receivers as frequency reference sources. Beidou receivers can not only provide an accurate clock source around the clock, but their system reliability and coverage have also been widely recognized. However, the PPS (pulse per second) signal output by the Beidou receiver, although stable, is easily affected by external environmental factors such as weather conditions, building obstructions, and ionosphere changes, resulting in large signal jitter, which makes it difficult to meet the strict requirements of high-precision frequency synchronization.

[0003] Prior art 1 (application number CN202110306101.1) proposes a high-frequency, broadband, and high-precision phase-locked loop performance enhancement technology. Prior art 1 proposes various performance enhancement technologies for the phase-locked loop, an important circuit module in the rapidly developing wireless communication system, to make it have the advantages of high frequency, broadband, and high precision, including three technical contents: RF module high-frequency gain multiplication technology, based on the ordinary differential common source amplifier circuit, introduces negative resistance coupling tube technology to improve the overall transconductance of the circuit and thus improve the gain; two-stage fractional frequency division technology based on accumulator and Δ-Σ modulator, so that when the precision of fractional frequency division is very high, the power consumption and area of ​​the circuit will not increase geometrically like a single-stage fractional frequency divider; high linearity and large output range charge pump technology, which improves the operating frequency of the charge pump and reduces mismatch. However, prior art 1 cannot be integrated into a phase-locked loop for use.

[0004] Prior art 2 (application number CN202410078580.X) proposes a phase-locked loop circuit, system and method for determining the phase-locked loop locking time. Prior art 2 discloses a phase-locked loop circuit, system and method for determining the phase-locked loop locking time, and relates to the field of integrated circuit testing technology. The clock generator is connected to the clock buffer to obtain the clock signal corresponding to the current modulation depth; the clock buffer is connected to the phase-locked loop plug-in; the controller is connected to the clock buffer and the phase-locked loop plug-in respectively. Then, the PLL locking time determined by the artificial capture time proposed in prior art 2 is prone to deviation, which affects the accuracy of the captured signal and the accuracy of the subsequent evaluation of the locking capability.

[0005] Therefore, there is an urgent need for a taming technology that can effectively combine a high-precision reference source and a local frequency source. Summary of the invention

[0006] The technical solution of the present invention provides a high-precision frequency source adaptive taming based on digital phase-locked technology to solve the problem of how to achieve high-precision frequency synchronization so that the system can maintain highly consistent frequency output in various complex environments.

[0007] In order to solve the above problems, the present invention provides a high-precision frequency source adaptive taming method based on digital phase-locked technology, the method comprising:

[0008] Based on a phase-locked loop digital model, a local frequency source of high-precision time frequency is subjected to phase-locked digital processing, and the phase of the local frequency source is adjusted;

[0009] Performing jitter reduction processing on a reference PPS signal generated by a reference frequency source so that the jitter of the reference PPS signal is within a preset range;

[0010] The reference PPS signal after dithering is tamed to a local frequency source after phase-locked digital processing.

[0011] Preferably, the phase-locked loop digital model is used to perform phase-locked digital processing on the local frequency source of the high-precision time frequency, and is calculated according to the following formula:

[0012] INTEGRAL=KI×DPHASE

[0013] GAIN=KP×DPHASE×(-1)

[0014] CTR=INTEGRAL+GAIN

[0015] That is: CTR = KP × DPHASE × (-1) + KI × DPHASE;

[0016] Among them, INTEGRAL is the integral, KI is the integral parameter in PID control, KP is the proportion in PID control, GAIN is the gain, CTR is the frequency adjustment signal, and DPHASE is the difference between the local phase and the reference phase;

[0017] Redefine KI and KP as:

[0018]

[0019] After redefining KI and KP, the time constant T and the damping coefficient ζ are determined; the calculation formula of the final frequency regulation signal CTR is adjusted to:

[0020]

[0021] Based on the frequency adjustment signal CTR, the phase of the local frequency source is adjusted.

[0022] Preferably, the performing jitter reduction processing on the reference PPS signal generated by the reference frequency source so that the jitter of the reference PPS signal is within a preset range includes:

[0023] The reference PPS signal generated by the reference frequency source is subjected to jitter reduction processing through an ultra-strong filter.

[0024] Preferably, the reference PPS signal to be subjected to jitter processing further includes:

[0025] The jitter of the reference PPS signal output by the receiver is reduced to 1 / time constant of the jitter of the input PPS signal.

[0026] Preferably, the method further comprises: accelerating the taming of the reference PPS signal after the jitter processing to a local frequency source after the phase-locked digital processing:

[0027] The corresponding damping coefficient is determined by the difference between the local phase and the reference phase.

[0028] According to another aspect of the present invention, the present invention provides a high-precision frequency source adaptive taming system based on digital phase-locked technology, the system comprising:

[0029] A phase-locked digitization unit, used to perform phase-locked digitization processing on a local frequency source of high-precision time frequency based on a phase-locked loop digitization model, and adjust the phase of the local frequency source;

[0030] A low-jitter PPS generating unit, used for performing jitter reduction processing on a reference PPS signal generated by a reference frequency source, so that the jitter of the reference PPS signal is within a preset range;

[0031] The taming unit is used to tame the reference PPS signal that has been subjected to dithering to a local frequency source that has been subjected to phase-locked digital processing.

[0032] Preferably, the phase-locked digitization unit is used to perform phase-locked digitization processing on the local frequency source of the high-precision time frequency based on a phase-locked loop digitization model, and calculate according to the following formula:

[0033] INTEGRAL=KI×DPHASE

[0034] GAIN=KP×DPHASE×(-1)

[0035] CTR=INTEGRAL+GAIN

[0036] That is: CTR = KP × DPHASE × (-1) + KI × DPHASE;

[0037] Among them, INTEGRAL is the integral, KI is the integral parameter in PID control, KP is the proportion in PID control, GAIN is the gain, CTR is the frequency adjustment signal, and DPHASE is the difference between the local phase and the reference phase;

[0038] Redefine KI and KP as:

[0039]

[0040] After redefining KI and KP, the time constant T and the damping coefficient ζ are determined; the calculation formula of the final frequency regulation signal CTR is adjusted to:

[0041]

[0042] Based on the frequency adjustment signal CTR, the phase of the local frequency source is adjusted.

[0043] Preferably, the low-jitter PPS generating unit is used to perform jitter reduction processing on a reference PPS signal generated by a reference frequency source so that the jitter of the reference PPS signal is within a preset range, and is also used to:

[0044] The reference PPS signal generated by the reference frequency source is subjected to jitter reduction processing through an ultra-strong filter.

[0045] Preferably, the taming unit is used to tame the reference PPS signal after the jitter processing, and is also used to:

[0046] The jitter of the reference PPS signal output by the receiver is reduced to 1 / time constant of the jitter of the input PPS signal.

[0047] Preferably, the taming unit is further used to: accelerate the taming of the reference PPS signal after the jitter processing to the local frequency source after the phase-locked digital processing:

[0048] The corresponding damping coefficient is determined by the difference between the local phase and the reference phase.

[0049] The technical solution of the present invention proposes a method and system for adaptively taming a high-precision frequency source based on digital phase-locked technology, wherein the method includes: based on a phase-locked loop digital model, performing phase-locked digital processing on a local frequency source of high-precision time and frequency, and adjusting the phase of the local frequency source; performing jitter reduction processing on a reference PPS signal generated by a reference frequency source, so that the jitter of the reference PPS signal is within a preset range; and taming the processed reference PPS signal to a local frequency source that has been digitally processed by phase-locking. The technical solution of the present invention makes full use of the advantages of a high-precision reference source, while overcoming its inherent defects, and realizes high-precision synchronization and stability optimization of frequency signals by intelligently taming the local frequency source. The technical solution of the present invention introduces digital phase-locked technology into the frequency source taming system, which can greatly improve long-term stability while ensuring the short-term stability of the system, reduce phase noise and signal jitter, and ultimately meet the stringent requirements of various high-precision time and frequency applications. This technology is not only innovative and advanced in technical principles, but also shows extremely high value and broad application prospects in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] A more complete understanding of exemplary embodiments of the present invention may be obtained by referring to the following drawings:

[0051] Figure 1 A flow chart of a high-precision frequency source adaptive taming method based on digital phase-locked technology according to a preferred embodiment of the present invention;

[0052] Figure 2 1 is a schematic diagram of a phase-locked loop digital model according to a preferred embodiment of the present invention;

[0053] Figure 3 A schematic diagram of the stability of a frequency source when it is not tamed according to a preferred embodiment of the present invention;

[0054] Figure 4 A schematic diagram of the stability of a frequency source during taming according to a preferred embodiment of the present invention;

[0055] Figure 5 A schematic diagram of the overall architecture of a taming system according to a preferred embodiment of the present invention; and

[0056] Figure 6 The structure diagram of a high-precision frequency source adaptive taming system based on digital phase-locked technology according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0057] Now, exemplary embodiments of the present invention are described with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to disclose the present invention in detail and completely and to fully convey the scope of the present invention to those skilled in the art. The terms used in the exemplary embodiments shown in the accompanying drawings are not intended to limit the present invention. In the accompanying drawings, the same units / elements are marked with the same reference numerals.

[0058] Unless otherwise specified, the terms (including technical terms) used herein have the commonly understood meanings to those skilled in the art. In addition, it is understood that the terms defined in commonly used dictionaries should be understood to have the same meanings as those in the context of the relevant fields, and should not be understood as idealized or overly formal meanings.

[0059] Figure 1 The present invention is a flowchart of a high-precision frequency source adaptive taming method based on digital phase-locked technology according to a preferred embodiment of the present invention.

[0060] In view of the multiple key problems encountered in the frequency source taming process, the present invention proposes a solution based on an adaptive taming method and digital phase-locking technology. By comprehensively applying advanced digital phase-locking technology, the following technical capabilities are achieved:

[0061] (1) Effectively control and reduce the phase error accumulation caused by drift and aging of the local frequency source, significantly improving the long-term stability of the system;

[0062] (2) Optimize the PPS signal output by the receiver, reduce its jitter, and improve the overall stability and accuracy of the system;

[0063] (3) Take into account both short-term and long-term stability, achieve the best balance, and ensure stable system performance.

[0064] The present invention captures signals through a controller to obtain accurate first and second times, and avoids deviations from the PLL locking time determined by the current artificial capture time, thereby improving the accuracy of the captured signals and the accuracy of the subsequent evaluation of the locking capability, reducing the delay time, and improving the capture efficiency. In addition, different preset locking scenarios corresponding to different modulation depths make the locking scenarios covered by the present invention comprehensive, ensuring the normal operation of the circuit system.

[0065] The present invention proposes a method for adaptively taming a frequency source by using digital phase-locked technology. The system includes a local frequency source, a phase comparator, a frequency controller and a processor. The local frequency source is precisely controlled by the phase negative feedback mechanism of a digital phase-locked loop.

[0066] like Figure 1As shown, the present invention provides a high-precision frequency source adaptive taming method based on digital phase-locked technology, the method comprising:

[0067] Step 101: Based on a phase-locked loop digital model, phase-locked digital processing is performed on a local frequency source of high-precision time frequency, and the phase of the local frequency source is adjusted;

[0068] Preferably, based on the phase-locked loop digital model, the local frequency source of the high-precision time frequency is phase-locked digitally processed and calculated according to the following formula:

[0069] INTEGRAL=KI×DPHASE

[0070] GAIN=KP×DPHASE×(-1)

[0071] CTR=INTEGRAL+GAIN

[0072] That is: CTR = KP × DPHASE × (-1) + KI × DPHASE;

[0073] Among them, INTEGRAL is the integral, KI is the integral parameter in PID control, KP is the proportion in PID control, GAIN is the gain, CTR is the frequency adjustment signal, and DPHASE is the difference between the local phase and the reference phase;

[0074] Redefine KI and KP as:

[0075]

[0076] After redefining KI and KP, the time constant T and the damping coefficient ζ are determined; the calculation formula of the final frequency regulation signal CTR is adjusted to:

[0077]

[0078] Based on the frequency adjustment signal CTR, the phase of the local frequency source is adjusted.

[0079] Phase-locked digitization of the present invention: The phase-locked loop is a phase negative feedback system. When the system phase is locked, the phase difference is constant. At this time, the frequency of the local frequency source will be equal to the frequency of the reference source, and it has the characteristic of not changing with time. After the phase-locked loop is digitized, the following can be obtained: Figure 2 Model shown.

[0080] In this model, DPHASE represents the difference between the local phase and the reference phase. When digital phase negative feedback is performed, DPHASE is used to control the frequency adjustment signal CTR, that is, CTR = DPHASE × (-1). Through the feedback of the frequency controller, the output frequency of the local frequency source is controlled to achieve the goal of phase negative feedback. However, due to the drift and aging of the local frequency source, DPHASE will continue to accumulate, resulting in an increase in phase error. In order to suppress the accumulation of DPHASE, an integrator needs to be added to the system.

[0081] The digitization process of the phase-locked loop can be expressed as the following formula:

[0082] INTEGRAL=KI×DPHASE

[0083] GAIN=KP×DPHASE×(-1)

[0084] CTR=INTEGRAL+GAIN

[0085] That is: CTR = KP × DPHASE × (-1) + KI × DPHASE; because KI and KP in the formula are not convenient for engineering debugging, they are redefined as:

[0086]

[0087] After redefinition and transformation, the time constant T and damping coefficient ζ of the tamed system are obtained. The final formula becomes:

[0088]

[0089] The formula of the present invention is a discrete mathematical model, which is suitable for the realization and optimization of a digital phase-locked loop. This formula not only provides a stable time constant and damping coefficient for the system, but also provides a convenient way of debugging and optimization for practical engineering applications, ensuring the stability and reliability of the frequency source in high-precision time and frequency applications.

[0090] The algorithm code of the digital control algorithm of the phase-locked loop in the present invention is:

[0091] LongdoubleFreq_Ctrl=0;

[0092] LongDoubleIntegral = 0;

[0093] longdoubleGain = 0;

[0094] longdoubleTerm=100;

[0095] long double Damp = 0;

[0096] {

[0097] Gain=2*damp / (Term)

[0098] Integral+=DPHAE / (Term)^2

[0099] Freq_Ctrl=Integral+Gain*DPHAE

[0100] }

[0101] {} contains the code for loop execution.

[0102] Step 102: performing jitter reduction processing on a reference PPS signal generated by a reference frequency source so that the jitter of the reference PPS signal is within a preset range;

[0103] Preferably, performing jitter reduction processing on the reference PPS signal generated by the reference frequency source so that the jitter of the reference PPS signal is within a preset range includes:

[0104] The reference PPS signal generated by the reference frequency source is subjected to jitter reduction processing through an ultra-strong filter.

[0105] Preferably, the reference PPS signal after jitter processing further includes:

[0106] The jitter of the reference PPS signal output by the receiver is reduced to 1 / time constant of the jitter of the input PPS signal.

[0107] Preferably, the method further comprises: accelerating the taming of the processed reference PPS signal to a local frequency source that has undergone phase-locked digital processing:

[0108] The corresponding damping coefficient is determined by the difference between the local phase and the reference phase.

[0109] Step 103: tame the processed reference PPS signal to the local frequency source that has undergone phase-locked digital processing.

[0110] The generation of low jitter PPS in the present invention: In high-precision time and frequency applications, the local PPS signal is generated by the frequency division process of the local frequency source. When the hardware circuit design is reasonable and accurate, the jitter level of the local PPS signal is consistent with the jitter level of the local frequency source. When the output frequency of the local frequency source jitters by 1×10-11 per second, the jitter of the local PPS signal will be 10 picoseconds (ps) accordingly. This high-precision jitter control is the basis for achieving time and frequency synchronization.

[0111] The PPS taming system plays a vital role in this process. Its function can be regarded as a high-efficiency filter for the PPS signal. Under ideal conditions, that is, when the drift and aging effects of the local frequency source are ignored, the jitter amplitude of the PPS signal output by the receiver will be significantly reduced after passing through the PPS taming system. Specifically, the jitter of the output PPS signal will be reduced to 1 / time constant of the jitter of the input PPS signal. This optimization process significantly improves the stability and accuracy of the PPS signal, enabling it to better meet the needs of high-precision time and frequency applications.

[0112] The core mechanism of the taming system lies in its precise control and regulation of the local frequency source. By comprehensively applying digital phase-locking technology, the taming system can monitor and adjust the output of the local frequency source in real time to ensure that its frequency is highly consistent with the reference source. Especially when dealing with complex and dynamically changing environmental conditions, the taming system can effectively filter out various interference factors and reduce the jitter of the PPS signal to the lowest level.

[0113] In addition, the PPS taming system not only demonstrates its excellent filtering performance in theory, but also proves its excellent performance and reliability through multiple verifications and experiments in practical applications. Experimental data shows that after being processed by the taming system, the jitter level of the local PPS signal can be significantly reduced, thereby improving the synchronization accuracy of the entire time and frequency system. Especially in high-demand application scenarios, such as satellite navigation, precision measurement, and high-precision timing systems, the application of the taming system is particularly important and indispensable.

[0114] In the design and optimization process of the PPS taming system of the present invention, multiple factors need to be considered, including the characteristics of the local frequency source, the output performance of the receiver, and the influence of the external environment. Through systematic design and optimization, the taming system can not only maintain high-precision output under normal conditions, but also show excellent stability and reliability under extreme conditions. All this is due to the application of digital phase-locked technology and the optimized design of the overall system architecture.

[0115] The PPS taming system achieves great suppression of local PPS signal jitter through its efficient filtering and adjustment mechanism, significantly improving the synchronization accuracy and stability of the system. Its wide application in high-precision time and frequency applications not only demonstrates the advancement and practicality of the technology, but also lays a solid foundation for the development of future high-precision time synchronization technology.

[0116] The method for generating a low-jitter PPS signal in the present invention is as follows: the local PPS is generated by dividing the local frequency source. The jitter of the local PPS generated by the hardware divider can be equivalent to the jitter of the local frequency source. When the output frequency of the local frequency source jitters by 1×10-11 per second, the jitter of the local PPS is 10ps. The PPS taming system can be regarded as a super filter of the PPS. The half-life of this filter is the time constant mentioned in the first chapter. Therefore, without considering the drift and aging of the local frequency source, when the PPS output by the receiver passes through the PPS taming system, the jitter of the output PPS will be reduced to 1 / time constant of the input PPS jitter.

[0117] The overall architecture design of the taming system is as follows Figure 5 shown.

[0118] The present invention is based on the above method before and after taming, the stability of the local frequency source is as follows Figure 3 and Figure 4 The time constant of the taming system in the figure is 2000s, the local frequency source used by the taming system in the figure is a constant temperature crystal oscillator, and the test reference is a rubidium atomic clock.

[0119] It can be seen from the figure that before taming, the stability of the frequency source begins to deteriorate from 100s, which is in line with the stability characteristics of the constant temperature crystal oscillator; when tamed, the 1s stability and 10s stability of the frequency source are basically the same as when not tamed, but the stability drops rapidly from 100s. The data proves that taming does not significantly affect the short-term stability of the local frequency source, but can greatly improve the long-term stability of the local frequency source. And it can be seen from the data that after taming, the stability characteristics of the constant temperature crystal oscillator are not much different from the stability of the rubidium atomic clock, and the short-term stability is better.

[0120] Through the present invention, the system realizes high-precision frequency synchronization, significantly optimizes the jitter of the PPS signal, and greatly improves the long-term stability of the frequency source. Under the premise of ensuring that the short-term stability is not affected, the phase noise characteristics of the frequency source are successfully improved to ensure the purity and stability of the signal. Experiments have shown that the taming system can still maintain a high degree of stability and accuracy in a complex and changeable environment, showing excellent anti-interference ability and adaptability. The breakthrough progress of this technology makes it widely applicable in high-precision time and frequency application scenarios, including but not limited to satellite navigation, precision measurement, timing systems and other fields, laying a solid foundation for future development, and providing the industry with an efficient and reliable solution, which greatly promotes the advancement of time and frequency synchronization technology.

[0121] In practical applications, the taming system has demonstrated its wide applicability, especially in high-demand fields such as high-precision timing systems, satellite navigation systems, atomic clock calibration, and precision measuring instruments. For example, in the Beidou navigation system, the application of the taming system of the present invention can accurately tame the PPS signal output by the receiver to the local frequency source, thereby achieving highly accurate frequency synchronization. This synchronization mechanism not only greatly improves the timing accuracy of the system, but also significantly enhances its reliability. By utilizing the taming system, the Beidou navigation system can maintain excellent performance in a complex operating environment, ensuring accurate transmission and efficient application of signals. This technological innovation not only provides solid technical support for the navigation system, but also brings revolutionary progress to other high-precision time and frequency application fields, laying a solid foundation for future scientific and technological development.

[0122] Figure 6 The structure diagram of a high-precision frequency source adaptive taming system based on digital phase-locked technology according to a preferred embodiment of the present invention.

[0123] like Figure 6 As shown, the present invention provides a high-precision frequency source adaptive taming system based on digital phase-locked technology, the system comprising:

[0124] The phase-locked digitization unit 601 is used to perform phase-locked digitization processing on the local frequency source of the high-precision time frequency based on the phase-locked loop digitization model, and adjust the phase of the local frequency source;

[0125] Preferably, the phase-locked digitization unit 601 is used to perform phase-locked digitization processing on the local frequency source of the high-precision time frequency based on the phase-locked loop digitization model, and calculate according to the following formula:

[0126] INTEGRAL=KI×DPHASE

[0127] GAIN=KP×DPHASE×(-1)

[0128] CTR=INTEGRAL+GAIN

[0129] That is: CTR = KP × DPHASE × (-1) + KI × DPHASE;

[0130] Among them, INTEGRAL is the integral, KI is the integral parameter in PID control, KP is the proportion in PID control, GAIN is the gain, CTR is the frequency adjustment signal, and DPHASE is the difference between the local phase and the reference phase;

[0131] Redefine KI and KP as:

[0132]

[0133] After redefining KI and KP, the time constant T and the damping coefficient ζ are determined; the calculation formula of the final frequency regulation signal CTR is adjusted to:

[0134]

[0135] Based on the frequency adjustment signal CTR, the phase of the local frequency source is adjusted.

[0136] A low-jitter PPS generating unit 602 is used to perform jitter reduction processing on a reference PPS signal generated by a reference frequency source so that the jitter of the reference PPS signal is within a preset range;

[0137] The training unit 603 is used to train the processed reference PPS signal to a local frequency source that has undergone phase-locked digital processing.

[0138] Preferably, the low-jitter PPS generating unit 602 is used to perform jitter reduction processing on the reference PPS signal generated by the reference frequency source so that the jitter of the reference PPS signal is within a preset range, and is also used to:

[0139] The reference PPS signal generated by the reference frequency source is subjected to jitter reduction processing through an ultra-strong filter.

[0140] Preferably, the taming unit 603, used for the reference PPS signal output by the receiver, is further used for:

[0141] The jitter of the jittered reference PPS signal is reduced to 1 / time constant of the jitter of the input PPS signal.

[0142] Preferably, the taming unit 603 is further used to: accelerate the taming of the reference PPS signal after the jitter processing to the local frequency source after the phase-locked digital processing:

[0143] The corresponding damping coefficient is determined by the difference between the local phase and the reference phase.

[0144] A high-precision frequency source adaptive taming system based on digital phase-locked technology provided in an embodiment of the present invention corresponds to a high-precision frequency source adaptive taming method based on digital phase-locked technology provided in an embodiment of the present invention, and will not be described in detail here.

[0145] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The schemes in the embodiments of the present invention may be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0146] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0150] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

[0151] The invention has been described above with reference to a few embodiments. However, it is readily apparent to a person skilled in the art that other embodiments than the ones disclosed above are equally within the scope of the invention, as defined by the appended patent claims.

[0152] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a / said / the [means, components, etc.]" are to be openly interpreted as at least one instance of the means, components, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not necessarily have to be performed in the exact order disclosed, unless explicitly stated otherwise.

Claims

1. A high-precision frequency source adaptive taming method based on digital phase-locked technology, the method comprising: Based on a phase-locked loop digital model, a local frequency source of high-precision time frequency is subjected to phase-locked digital processing, and the phase of the local frequency source is adjusted; Performing jitter reduction processing on a reference PPS signal generated by a reference frequency source so that the jitter of the reference PPS signal is within a preset range; The reference PPS signal after dithering is tamed to a local frequency source after phase-locked digital processing.

2. The method according to claim 1, wherein the local frequency source of the high-precision time frequency is subjected to phase-locked digital processing based on the phase-locked loop digital model, and is calculated according to the following formula: INTEGRAL=KI×DPHASE GAIN=KP×DPHASE×(-1) CTR=INTEGRAL+GAIN That is: CTR = KP × DPHASE × (-1) + KI × DPHASE; in, INTEGRAL is the integral, KI is the integral parameter in PID control, KP is the proportion in PID control, GAIN is the gain, CTR is the frequency adjustment signal, and DPHASE is the difference between the local phase and the reference phase; Redefine KI and KP as: After redefining KI and KP, the time constant T and the damping coefficient ζ are determined; the calculation formula of the final frequency regulation signal CTR is adjusted to: Based on the frequency adjustment signal CTR, the phase of the local frequency source is adjusted.

3. The method according to claim 2, wherein the step of performing jitter reduction processing on the reference PPS signal generated by the reference frequency source so that the jitter of the reference PPS signal is within a preset range comprises: The reference PPS signal generated by the reference frequency source is subjected to jitter reduction processing through an ultra-strong filter.

4. The method according to claim 3, wherein the reference PPS signal subjected to the jitter processing further comprises: The jitter of the reference PPS signal output by the receiver is reduced to 1 / time constant of the jitter of the input PPS signal.

5. The method according to claim 2, further comprising: Accelerate the jittered reference PPS signal to the local frequency source that has been phase-locked and digitized: The corresponding damping coefficient is determined by the difference between the local phase and the reference phase.

6. A high-precision frequency source adaptive taming system based on digital phase-locked technology, the system comprising: A phase-locked digitization unit, used to perform phase-locked digitization processing on a local frequency source of high-precision time frequency based on a phase-locked loop digitization model, and adjust the phase of the local frequency source; A low-jitter PPS generating unit, used for performing jitter reduction processing on a reference PPS signal generated by a reference frequency source, so that the jitter of the reference PPS signal is within a preset range; The taming unit is used to tame the reference PPS signal that has been subjected to dithering to a local frequency source that has been subjected to phase-locked digital processing.

7. The system according to claim 6, wherein the phase-locked digitization unit is used to perform phase-locked digitization processing on the local frequency source of the high-precision time frequency based on the phase-locked loop digitization model, and is calculated according to the following formula: INTEGRAL=KI×DPHASE GAIN=KP×DPHASE×(-1) CTR==NTEGRAL+GAIN That is: CTR = KP × DPHASE × (-1) + KI × DPHASE; in, INTEGRAL is the integral, KI is the integral parameter in PID control, KP is the proportion in PID control, GAIN is the gain, CTR is the frequency adjustment signal, and DPHASE is the difference between the local phase and the reference phase; Redefine KI and KP as: After redefining KI and KP, the time constant T and the damping coefficient ζ are determined; the calculation formula of the final frequency regulation signal CTR is adjusted to: Based on the frequency adjustment signal CTR, the phase of the local frequency source is adjusted.

8. The system according to claim 7, wherein the low-jitter PPS generating unit is used to perform jitter reduction processing on a reference PPS signal generated by a reference frequency source so that the jitter of the reference PPS signal is within a preset range, and is further used to: The reference PPS signal generated by the reference frequency source is subjected to jitter reduction processing through an ultra-strong filter.

9. The system according to claim 8, wherein the taming unit is used to convert the jittered reference PPS signal into: The jitter of the reference PPS signal output by the receiver is reduced to 1 / time constant of the jitter of the input PPS signal.

10. The system according to claim 7, wherein the taming unit is further used to: accelerate the taming of the reference PPS signal after the jitter processing to the local frequency source after the phase-locked digital processing; The corresponding damping coefficient is determined by the difference between the local phase and the reference phase.

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