High-speed frequency divider for any integer with duty ratio of 50%

Abstract

The invention discloses a 50% duty ratio arbitrary integer high-speed frequency divider, which belongs to the field of integrated circuits, and comprises a first module, a second module, a third module and a fourth module, the frequency division control word of the first module is provided by the fourth module, and the output of the first module realizes frequency division of any integer; the second module performs frequency division operation or direct connection on the output of the first module under different frequency division ratios; the third module further corrects the output duty ratio of the second module; and the fourth module decodes an original frequency division control word and respectively controls the first module, the second module and the third module. Compared with a traditional pulse swallowing type frequency divider, the pulse swallowing type frequency divider has the advantages that original frequency division of any integer can be achieved, and the duty ratio of 50% can also be achieved. The high-speed frequency divider provided by the invention is applied to the GHz, especially the high-speed frequency divider of more than 2GHz, and the application scene is wider.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a 50% duty cycle arbitrary integer high-speed frequency divider. Background Art

[0002] In the design of clock frequency synthesizer, the device is usually required to generate a clock with a wide frequency range. This function is usually achieved by dividing the high-frequency clock with a wide frequency divider. The frequency divider is a relatively common module in digital circuits. It is usually implemented based on a counter. It can achieve any integer frequency division and the duty cycle can be optimized to 50%. However, the operating speed usually does not exceed 500MHz, otherwise the timing constraints are difficult to achieve.

[0003] The existing GHz frequency divider is a structure called a pulse swallowing counter, such as Figure 1 As shown in the figure, this structure can realize frequency division of any integer, but its duty cycle cannot reach 50%, and as the frequency division ratio increases, its duty cycle decreases, because its high-level pulse width is a fixed number of high-speed clock cycles, usually only 2~4, depending on the frequency division coefficient used by the dual-mode pre-divider. This feature will not cause any impact in most applications, because most applications are edge-triggered, only the rising edge or falling edge is used, and it is not sensitive to the level. For example, the reference clock divider and feedback clock divider used in the phase-locked loop.

[0004] However, this type of frequency divider cannot meet the application requirements in some applications. For example, for an analog-to-digital converter, its sampling clock needs to meet the sampling time and holding time, which correspond to the high level time and low level time of the clock respectively. If the duty cycle is too large or too small, the sampling time or holding time will exceed the specification and cannot be used. Therefore, conventional pulse swallowing frequency dividers cannot be used in these places where there are requirements for duty cycle. Summary of the invention

[0005] The object of the present invention is to provide a 50% duty cycle arbitrary integer high-speed frequency divider to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a 50% duty cycle arbitrary integer high-speed frequency divider, comprising a first module, a second module, a third module and a fourth module; The frequency division control word of the first module is provided by the fourth module, and the output of the first module realizes arbitrary integer frequency division; The second module performs frequency division operation or direct pass on the output of the first module at different frequency division ratios; The third module further corrects the output duty cycle of the second module; The fourth module decodes the original frequency division control word to control the first module, the second module and the third module respectively.

[0007] In one embodiment, the first module includes a dual-mode prescaler, a pulse counter, and a mode selector; The input end of the dual-mode pre-divider is connected to the CLK_IN input clock, and the output end is connected to the pulse counter; the output end of the pulse counter is connected to the mode selector; the output end of the mode selector is connected to the dual-mode pre-divider; the fourth module provides a frequency division control word to the pulse counter.

[0008] In one embodiment, the second module includes a 2-way divider and a selector; the output end of the pulse counter is connected to the 2-way divider and the selector at the same time; when the frequency division is greater than or equal to 8, the 2-way divider is enabled, and when it is less than 8, the pass-through is enabled; at this time, the output of the second module has an output duty cycle of not a perfect 50% when the frequency division is odd, and the high and low levels will differ by at most one CLK_IN clock cycle; an even frequency division has achieved a 50% duty cycle.

[0009] In one embodiment, the third module includes a duty cycle corrector, and the output end of the selector and the CLK_IN input clock are both connected to the duty cycle corrector; the third module corrects the odd-numbered duty cycle of the output of the second module to compensate for half of the CLK_IN clock cycle; and does not intervene in the even-numbered duty cycle.

[0010] In one implementation, the fourth module is a frequency division and duty cycle controller, which re-encodes the original frequency division control word according to different frequency division ratios, so as to finally obtain a correct frequency division ratio.

[0011] The present invention provides a 50% duty cycle arbitrary integer high-speed frequency divider, which can not only realize the original arbitrary integer frequency division but also realize a 50% duty cycle compared to the traditional pulse swallowing frequency divider. The high-speed frequency divider involved in the present invention is a high-speed frequency divider applied to GHz, especially above 2GHz, and has a wider application scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of a traditional pulse swallowing counter.

[0013] Figure 2 The present invention provides a schematic diagram of a 50% duty cycle arbitrary integer high-speed frequency divider structure. DETAILED DESCRIPTION

[0014] The following is a further detailed description of a 50% duty cycle arbitrary integer high-speed frequency divider proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0015] The present invention provides a 50% duty cycle arbitrary integer high-speed frequency divider, the structure of which is as follows: Figure 2 As shown, it includes 4 modules, namely: module 1 composed of a dual-mode pre-divider, a pulse counter, and a mode selector, module 2 composed of a 2-divider and a selector, module 3 composed of a duty cycle corrector, and module 4 composed of a frequency divider and a duty cycle controller.

[0016] Module 1 can be regarded as a traditional pulse swallowing counter, except that its frequency division control word is provided by module 4. Because 2-division is required in module 2, the original frequency division control word needs to be re-encoded in module 4. The output of module 1 can achieve any integer division, but its output clock duty cycle cannot reach 50%.

[0017] Module 2 contains a 2-frequency divider and a selector, because the output of module 1 needs to be divided or passed at different frequency division ratios, which is determined by module 3 according to different frequency division control words. When the frequency division is greater than or equal to 8, the 2-frequency divider is selected, and when it is less than 8, the pass-through is selected. Regardless of whether 2-frequency division or pass-through is selected, the duty cycle of the output of module 2 is still not a perfect 50% when the frequency division is odd, but the high and low levels will only differ by one CLK_IN clock cycle at most. The even frequency division has achieved a 50% duty cycle after module 2.

[0018] Module 3 further corrects the output duty cycle of module 2, specifically correcting the odd-numbered frequency-division duty cycle, while not intervening in the even-numbered frequency-division duty cycle. Since the odd-numbered frequency-division high and low levels differ by only one CLK_IN clock cycle, half a CLK_IN clock cycle needs to be compensated, and this half-cycle compensation is implemented by module 3.

[0019] Module 4 decodes the original frequency division control word to control the pulse counter, selector and duty cycle corrector respectively. Because the functions of these devices are slightly different under different frequency division ratio settings, the original frequency division control word needs to be decoded.

[0020] The original frequency division control word in module 1 of the present invention is re-encoded by module 4 according to different frequency division ratios, so as to finally obtain the correct frequency division ratio; the addition of module 2 can realize a 50% duty cycle of even-numbered frequency division, and the high and low level time of odd-numbered frequency division is at most only one CLK_IN clock cycle; then, module 3 performs half-cycle compensation on the odd-numbered frequency division duty cycle of module 2, and does not perform duty cycle intervention on the even-numbered frequency division, so as to realize that all frequency divisions have a 50% duty cycle; module 4 decodes the input frequency division control word to determine the frequency division control word sent to module 1 and decide whether 2-frequency division is required in module 2, and also decides whether half-cycle compensation is required in module 3 according to the odd-even frequency division.

[0021] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A 50% duty cycle arbitrary integer high-speed frequency divider, characterized in that: comprising a first module, a second module, a third module and a fourth module; The frequency division control word of the first module is provided by the fourth module, and the output of the first module realizes arbitrary integer frequency division; The second module performs frequency division operation or direct pass on the output of the first module at different frequency division ratios; The third module further corrects the output duty cycle of the second module; The fourth module decodes the original frequency division control word to control the first module, the second module and the third module respectively.

2. The 50% duty cycle arbitrary integer high speed frequency divider as claimed in claim 1, characterized in that: The first module includes a dual-mode prescaler, a pulse counter, and a mode selector; The input end of the dual-mode prescaler is connected to the CLK_IN input clock, and the output end is connected to the pulse counter; the output end of the pulse counter is connected to the mode selector; the output end of the mode selector is connected to the dual-mode prescaler; The fourth module provides a frequency division control word to the pulse counter.

3. The 50% duty cycle arbitrary integer high speed frequency divider as claimed in claim 2, characterized in that: The second module includes a 2-way divider and a selector; the output end of the pulse counter is connected to the 2-way divider and the selector at the same time; when the frequency division is greater than or equal to 8, the 2-way divider is enabled, and when it is less than 8, the pass-through is enabled; at this time, the output of the second module has an output duty cycle of not a perfect 50% when the frequency division is odd, and the high and low levels will differ by at most one CLK_IN clock cycle; the even frequency division has achieved a 50% duty cycle.

4. The 50% duty cycle arbitrary integer high speed frequency divider as claimed in claim 3, characterized in that: The third module includes a duty cycle corrector, and the output end of the selector and the CLK_IN input clock are both connected to the duty cycle corrector; the third module corrects the output odd-numbered frequency-divided duty cycle of the second module to compensate for half of the CLK_IN clock cycle; and does not intervene in the even-numbered frequency-divided duty cycle.

5. The 50% duty cycle arbitrary integer high speed frequency divider as claimed in claim 4, characterized in that: The fourth module is a frequency division and duty cycle controller, which re-encodes the original frequency division control word according to different frequency division ratios, so as to finally obtain the correct frequency division ratio.

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