Fractional multimode frequency divider circuit based on space-time averaging and phase interpolation technology

Abstract

The invention discloses a decimal multi-modulus frequency divider circuit based on space-time averaging and phase interpolation technologies. The decimal multi-modulus frequency divider circuit comprises a third-order noise shaping modulation module, a dynamic element matching and phase selection module, a phase switching frequency divider module and a pipelined phase interpolation module. The third-order noise shaping modulation module is used for performing time averaging on the input frequency dividing ratio to generate an instantaneous frequency dividing ratio; the dynamic element matching and phase selection module is used for spatially averaging the instantaneous frequency dividing ratio and generating a frequency divider control word and a phase interpolator control word; the phase switching frequency divider module is used for generating a clock signal corresponding to a frequency dividing ratio according to the frequency divider control word; and the pipelined phase interpolation module is used for performing phase interpolation according to the clock signal to generate a final clock signal with an accurate phase. According to the embodiment of the invention, the mutual cooperation of the modules is utilized, the fusion of the space-time averaging technology and the phase interpolation technology is realized, and the limitation of the space-time averaging technology is improved.

Description

Technical Field

[0001] The invention belongs to the field of frequency synthesizer design, and in particular relates to a fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology. Background Art

[0002] Fractional dividers are widely used in the feedback loops of various phase-locked loops to divide the high-frequency clock signal output by the phase-locked loop so that the divided frequency is the same as the reference clock frequency. The quantization noise of the fractional divider will greatly affect the phase noise of the final output clock. As modern wired communications develop towards ultra-large scale and extremely high data turnover rate, the fractional divider output is required to have low quantization noise.

[0003] Among the commonly used fractional divider quantization noise suppression methods, the phase compensation scheme based on the digital time converter (DTC) or phase interpolation circuit reduces the divider output quantization noise by reducing the divider frequency step. These two methods have high frequency division accuracy, but the high-frequency phase interpolation circuit or DTC circuit has a large power consumption and area overhead, which cannot meet the constraints of area and power consumption under ultra-large scale and extremely high data flip rate conditions. The quantization error suppression technology based on the finite impulse response filter (FIR) filter filters out the high-pass quantization noise by connecting a low-pass FIR filter at the output of the divider. This method has low accuracy, and the increase in the number of taps will also lead to increased hardware complexity and power consumption. The quantization noise suppression method based on space-time averaging technology makes the divider into an array, and uses dynamic element matching technology to make the output of the divider average in space, further reducing the quantization step and improving the quantization accuracy. Due to the high degree of digitization, it can have good PVT robustness and calibration-free performance. However, this method can only be applied to charge pump phase-locked loops, and to achieve higher accuracy the array size needs to grow exponentially, which has great limitations. Summary of the invention

[0004] The technical problem to be solved by the present invention is that, since the existing fractional divider quantization noise suppression method has various shortcomings, the present invention provides a fractional multi-mode divider circuit based on space-time averaging and phase interpolation technology.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a fractional multi-mode divider circuit based on space-time averaging and phase interpolation technology, including: a third-order noise shaping modulation module, a dynamic element matching and phase selection module, a phase switching divider module and a pipeline phase interpolation module;

[0006] The third-order noise shaping modulation module is used to perform time averaging on the input frequency division ratio to generate an instantaneous frequency division ratio, and the output end is connected to the input end of the dynamic element matching and phase selection module;

[0007] The dynamic element matching and phase selection module is used to spatially average the instantaneous frequency division ratio and generate a frequency divider control word and a phase interpolator control word, and the output end is connected to the input end of the phase switching frequency divider module and the input end of the pipeline phase interpolation module;

[0008] The phase switching frequency divider module is used to generate a clock signal of a corresponding frequency division ratio according to the frequency divider control word, and the output end is connected to the input end of the third-order noise shaping modulation module, the input end of the dynamic element matching and phase selection module, and the input end of the pipeline phase interpolation module;

[0009] The pipeline phase interpolation module is used to perform phase interpolation according to the clock signal to generate a final clock signal with an accurate phase.

[0010] Preferably, the third-order noise shaping modulation module comprises: a linear feedback shift register and a third-order noise shaping modulator;

[0011] The linear feedback shift register generates a pseudo-random number with a mean value of 0 as jitter added to the third-order noise shaping modulator, and the output end is connected to the input end of the third-order noise shaping modulator;

[0012] The third-order noise shaping modulator is used to integrate and differentiate the error generated when the decimal part of the input frequency division ratio is rounded down and quantized, perform noise shaping on the quantization noise, and obtain the instantaneous frequency division ratio.

[0013] Preferably, the third-order noise shaping modulator includes: a first first-order modulator, a second first-order modulator and a third first-order modulator; the first first-order modulator, the second first-order modulator and the third first-order modulator are cascaded; the input end of the first first-order modulator is connected to the input frequency division ratio; the input ends of the second first-order modulator and the third first-order modulator are connected to the output end of the linear feedback shift register.

[0014] Preferably, the dynamic element matching and phase selection module comprises: a data weight averaging unit and a phase selection unit;

[0015] The data weight averaging unit is used to perform spatial averaging on the instantaneous frequency division ratio and output a spatial average signal of the instantaneous frequency division ratio, and the output end is connected to the phase selection unit;

[0016] The phase selection unit is used to convert the spatial average signal of the instantaneous frequency division ratio into a frequency divider control word and a phase interpolator control word.

[0017] Preferably, the data weight averaging unit comprises: an accumulator, a code-to-thermometer code and a shift register; the phase selection unit comprises: a plurality of symbol calculators and adders;

[0018] The accumulator and the code-to-thermometer code input terminal are used to receive the instantaneous frequency division ratio; the accumulator and the code-to-thermometer code output terminal are connected to the shift register input terminal; the shift register is used to output the spatial average signal of the instantaneous frequency division ratio; the multiple sign calculator input terminals correspond to the shift register output terminals one by one, and are used to receive the spatial average signal of the instantaneous frequency division ratio; the sign calculator output terminal is connected to the adder input terminal; the adder output terminal is used to output the phase interpolator control word;

[0019] The frequency divider control word is obtained by adding the spatial average signal end signal of the instantaneous frequency division ratio to the instantaneous frequency division ratio.

[0020] Preferably, the symbol calculator comprises: an XOR gate, a first D flip-flop and a second D flip-flop;

[0021] The XOR gate input terminal is respectively connected to the spatial average signal of the instantaneous frequency division ratio and the output terminal of the first D flip-flop; the XOR gate output terminal is connected to the input terminal of the first D flip-flop; the output terminal of the first D flip-flop is connected to the input terminal of the second D flip-flop; and the output terminal of the second D flip-flop is connected to the input terminal of the adder.

[0022] Among them, the multiple symbolic calculator logical expressions are:

[0023]

[0024] The N DWA，i [k] is the spatial average signal of the instantaneous frequency division ratio; DWA，A [k] is the end signal of the spatial average signal; the F i [k] is the output signal of the second D flip-flop.

[0025] Preferably, the phase switching divider module comprises: a multi-mode frequency division unit and a phase switching unit; the output end of the phase switching unit is connected to the input end of the multi-mode frequency division unit; the output end of the multi-mode frequency division unit is connected to the input end of the third-order noise shaping modulation module, the input end of the dynamic element matching and phase selection module, and the input end of the pipeline phase interpolation module; the frequency divider control word selection part is transmitted to the phase switching unit, and the operation part is transmitted to the multi-mode frequency division unit;

[0026] Wherein, the phase switching unit includes: a pulse generator, a counter, a clock buffer, a comparator, a D flip-flop and a state machine; the pulse generator output, the clock buffer output, the comparator output and the counter input are connected; the D flip-flop output and the counter output are connected to the comparator input; the comparator output and the clock buffer output are connected to the state machine input.

[0027] Preferably, the multi-mode frequency division unit comprises: a plurality of 2 / 3-mode frequency dividers; a cascade structure of the plurality of 2 / 3-mode frequency dividers; and an inverter and a NAND gate are arranged between the last two 2 / 3-mode frequency dividers, and a selector is connected to the output ends of the last two 2 / 3-mode frequency dividers.

[0028] Preferably, the pipeline phase interpolation module is a multi-stage pipeline structure; each stage of the pipeline includes: a phase interpolation unit and a multi-way selection unit;

[0029] The phase interpolation unit includes three phase interpolators; the multi-way selection unit includes: two selectors; the two-phase input clocks of the clock signal are input into the three phase interpolators in different arrangements; the three phase interpolator output signals are input into the two selectors in a pairwise distribution manner; wherein the two selector selection ends receive the phase interpolator control word, and the phase interpolator control word selects one of the three phase interpolator output signals.

[0030] Preferably, the phase interpolator comprises: 4 current sources, two PMOS tubes, two NMOS tubes and an AND gate;

[0031] The two PMOS tube sources and the two NMOS tube sources are connected to the four current sources in a one-to-one correspondence; the two PMOS tube gates and the AND gate input are the phase interpolator inputs; the AND gate output is connected to the two NMOS tube gates; the two PMOS tube drains and the two NMOS tube drains are the phase interpolator outputs.

[0032] Implementing the embodiments of the present invention has the following beneficial effects:

[0033] (1) The embodiment of the present invention uses each module to cooperate with each other, and uses the third-order noise shaping modulation module and the dynamic element matching and phase selection module to cooperate to realize the application of space-time averaging technology, and then uses the dynamic element matching and phase selection module to cooperate with the phase switching divider module to realize the application of phase interpolation technology, and uses the dynamic element matching and phase selection module to combine space-time averaging technology with phase interpolation technology. Not only can the phase interpolator work at a low frequency, reducing the area and power consumption of the phase interpolation circuit; it can also simplify the divider array in the space-time averaging technology into a single divider, so that the space-time averaging technology is extended to the sampling phase-locked loop, which greatly improves the limitations of the space-time averaging technology.

[0034] (2) In the embodiment of the present invention, a linear feedback shift register is used to dither the second first-order modulator and the third first-order modulator in the third-order noise shaping modulator, outputting a pseudo-random number with a mean value of 0, thereby breaking the periodicity of the output of the third-order noise shaping modulator and effectively reducing the decimal spurious output of the third-order noise shaping modulator.

[0035] (3) The embodiment of the present invention uses a data weight averaging unit to perform spatial averaging on the instantaneous frequency division ratio, thereby further improving the frequency division accuracy of the instantaneous frequency division ratio, reducing the quantization noise of the instantaneous frequency division ratio, and having high robustness to PVT.

[0036] (4) The embodiment of the present invention greatly reduces the area and power consumption of the pipelined phase interpolation module by designing the pipelined phase interpolation module as a multi-stage pipeline structure; and an AND gate is used in the phase interpolation unit to control the opening and closing of the pull-down network, thereby eliminating the short-circuit current of the phase interpolation unit and improving the linearity of the pipelined phase interpolation module.

[0037] (5) In the embodiment of the present invention, a multi-mode frequency division unit is designed as a cascade structure of multiple 2 / 3-mode frequency dividers, and the frequency division range of the fractional frequency divider is increased by using the frequency division ratio expansion technology. In addition, a forward phase switching technology is adopted in the phase switching unit to obtain the original minimum frequency division step of 1 / 4 on the basis of adding only a simple digital circuit, thereby improving the frequency division accuracy of the fractional frequency divider. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A circuit architecture diagram of a fractional multi-mode frequency divider based on space-time averaging and phase interpolation technology provided for the implementation of the present invention;

[0040] Figure 2 A diagram of the architecture of a third-order noise shaping modulation module provided for the implementation of the present invention;

[0041] Figure 3 A diagram of the architecture of the dynamic element matching and phase selection module provided for the implementation of the present invention;

[0042] Figure 4 A diagram of the phase switching frequency divider module architecture provided for the implementation of the present invention;

[0043] Figure 5 A diagram of the architecture of a multi-mode frequency division unit provided for the implementation of the present invention;

[0044] Figure 6 A diagram of the phase switching unit architecture provided by an embodiment of the present invention;

[0045] Figure 7 A pipelined phase interpolation module provided by an embodiment of the present invention;

[0046] Figure 8 A diagram of the phase interpolator architecture provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] like Figure 1 As shown, the present embodiment discloses a fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology, and the fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology includes: a third-order noise shaping modulation module 10, a dynamic element matching and phase selection module 20, a phase switching frequency divider module 30 and a pipeline phase interpolation module 40. The output end of the third-order noise shaping modulation module 10 is connected to the input end of the dynamic element matching and phase selection module. The output end of the dynamic element matching and phase selection module 20 is connected to the input end of the phase switching frequency divider module 30 and the input end of the pipeline phase interpolation module 40. The output end of the phase switching frequency divider module 30 is connected to the input end of the third-order noise shaping modulation module 10, the input end of the dynamic element matching and phase selection module 20, and the input end of the pipeline phase interpolation module 40.

[0049] The third-order noise shaping modulation module 10 is used to perform time averaging on the input frequency division ratio (FCW) to generate an instantaneous frequency division ratio (div[k]). The dynamic element matching and phase selection module 20 is used to perform spatial averaging on the instantaneous frequency division ratio and generate a frequency divider control word (divN[k]) and a phase interpolator control word (DCW). The phase switching frequency divider module 30 is used to generate a clock signal (Φ_Lead, Φ_Lag) corresponding to the frequency division ratio according to the frequency divider control word. The pipeline phase interpolation module 40 is used to perform phase interpolation on the clock signal to generate a final clock signal (Φ_div) with an accurate phase.

[0050] The fractional multi-mode divider circuit based on space-time averaging and phase interpolation technology adopts each module to cooperate with each other, and uses the third-order noise shaping modulation module 10 and the dynamic element matching and phase selection module 20 to realize the application of space-time averaging technology, and then uses the dynamic element matching and phase selection module 20 and the phase switching divider module 30 to realize the application of phase interpolation technology, and at the same time uses the dynamic element matching and phase selection module 20 to combine space-time averaging technology with phase interpolation technology. Not only can the phase interpolator work at a low frequency, reducing the area and power consumption of the phase interpolation circuit; it can also simplify the divider array in the space-time averaging technology into a single divider, so that the space-time averaging technology is extended to the sampling phase-locked loop, which greatly improves the limitations of the space-time averaging technology.

[0051] See also Figure 2 The third-order noise shaping modulation module 10 includes: a linear feedback shift register 120 and a third-order noise shaping modulator 110. The third-order noise shaping modulator 120 includes: a first first-order modulator 121, a second first-order modulator 122, a third first-order modulator 123 and a simple circuit. The output end of the linear feedback shift register 120 is connected to the input end of the third-order noise shaping modulator 110, specifically, the output end of the linear feedback shift register 120 is connected to the input ends of the second first-order modulator 122 and the third first-order modulator 123. The first first-order modulator 121, the second first-order modulator 122 and the third first-order modulator 123 are cascaded. The input end of the first first-order modulator 121 is connected to the input frequency division ratio.

[0052] The linear feedback shift register 110 generates a pseudo-random number with a mean value of 0 as a jitter added to the third-order noise shaping modulator 120, breaking the periodicity of the output of the third-order noise shaping modulator 120, and effectively reducing the decimal spurious output of the third-order noise shaping modulator. The third-order noise shaping modulator 120 is used to integrate and differentiate the error generated when the decimal part of the input frequency division ratio is rounded down and quantized, and perform noise shaping on the quantization noise to obtain the instantaneous frequency division ratio. In this embodiment, the linear feedback shift register 110 is 17 bits in size, and the third-order noise shaping modulator 120 constructs a high-pass noise transfer function by integrating and differentiating the error generated when the decimal part of the 17-bit input frequency division ratio is rounded down and quantized, performs noise shaping on the quantization noise, and finally outputs a 3-bit instantaneous integer frequency division ratio. Each first-order modulator has a data input d[n], an error output e[n] and a data output y[n]; the output e_1[n] of the first first-order modulator 121 is input into the data input d_2[n] of the second first-order modulator 122, and the output e_2[n] of the second first-order modulator 122 is input into the data input d_3[n] of the third first-order modulator 123. The sum of y_1[n], y_2[n] and y_3[n] of each first-order modulator is obtained to obtain a 3-bit output y[n] of the third-order noise shaping modulator 120, i.e., a 3-bit instantaneous integer division ratio.

[0053] See also Figure 3 The dynamic element matching and phase selection module 20 includes: a data weight averaging unit 210, a phase selection unit 220 and a simple circuit. The output end of the data weight averaging unit 210 is connected to the input end of the phase selection unit 220. The data weight averaging unit 210 includes: an accumulator 211, a code-to-thermometer code 212 and a shift register 213. The phase selection unit 220 includes: a plurality of symbol calculators 221 and an adder 222.

[0054] The input ends of the accumulator 211 and the code-to-thermometer code 212 are used to receive the instantaneous frequency division ratio. The output ends of the accumulator 211 and the code-to-thermometer code 212 are connected to the input end of the shift register 213. The shift register is used to output the spatial average signal of the instantaneous frequency division ratio. Specifically, the 3-bit instantaneous integer frequency division ratio div[k] is accumulated and summed and then divided by 16 to obtain the modulus. The output result is then passed through the 4-bit accumulator 211 and the binary code-to-thermometer code 212 respectively, and finally the code-to-thermometer code 212 is shifted by the shift register 213 by the number of times the value stored in the accumulator 211. In this way, the spatial average of the input instantaneous frequency division ratio is completed, and a 16-phase 1-bit frequency division ratio array is output. The input ends of the multiple symbol calculators 221 correspond to the output ends of the shift register 213 one by one, and are used to receive the spatial average signal of the instantaneous frequency division ratio. The output end of the symbol calculator 221 is connected to the input end of the adder 222. The output end of the adder 222 is used to output the phase interpolator control word (DCW). The divider control word (divN[k]) is obtained by adding the spatial average signal end signal of the instantaneous frequency division ratio and the instantaneous frequency division ratio, and then obtained and output by the adder in the simple circuit.

[0055] The symbol calculator 221 includes: an XOR gate 223, a first D flip-flop 224 and a second D flip-flop 225. The XOR gate 223 input terminal is connected to the spatial average signal of the instantaneous frequency division ratio and the output terminal of the first D flip-flop 223 respectively. The XOR gate 221 output terminal is connected to the first D flip-flop 223 input terminal. The first D flip-flop 223 output terminal is connected to the second D flip-flop 224 input terminal. The second D flip-flop 224 output terminal is connected to the adder 222 input terminal.

[0056] The logical expressions of the multiple symbol calculators 221 are:

[0057]

[0058] The N DWA，i [k] is the spatial average signal of the instantaneous frequency division ratio; DWA，A [k] is the end signal of the spatial average signal; the F i [k] is the output signal of the second D flip-flop. The end signal of the spatial average signal is the spatial average signal of the last instantaneous frequency division ratio among the spatial average signals of the instantaneous frequency division ratios. In this embodiment, there are 16 spatial average signals of the instantaneous frequency division ratios, and the end signal of the spatial average signal is the spatial average signal of the 16th instantaneous frequency division ratio.

[0059] The data weight averaging unit 210 is used to perform spatial averaging on the instantaneous frequency division ratio and output a spatial average signal of the instantaneous frequency division ratio. The phase selection unit 220 is used to convert the spatial average signal of the instantaneous frequency division ratio into a frequency divider control word and a phase interpolator control word. The data weight averaging unit performs spatial averaging on the instantaneous frequency division ratio, further improving the frequency division accuracy of the instantaneous frequency division ratio, reducing the quantization noise of the instantaneous frequency division ratio, and having high robustness to PVT.

[0060] See also Figure 4-Figure 6, the phase switching divider module 30 includes: a multi-mode frequency division unit 310 and a phase switching unit 320. The output end of the phase switching unit 320 is connected to the input end (Φ_PS) of the multi-mode frequency division unit 310, and the second-stage clock output (f2) of the multi-mode frequency division unit 310 is connected to the clock input end (clk) of the phase switching unit 320. The output end (fout) of the multi-mode frequency division unit 310 is connected to the input end of the third-order noise shaping modulation module 10, the input end of the dynamic element matching and phase selection module 20, and the input end of the pipeline phase interpolation module 40. The frequency divider control word selection part (sel) is transmitted to the phase switching unit 320, and the operation part (P) is transmitted to the multi-mode frequency division unit 310. The output of the multi-mode frequency division unit 310 is beat by two orthogonal clocks through two D flip-flops to generate two output clock signals (Φ_Lead, Φ_Lag).

[0061] The multi-mode frequency division unit 310 includes: a plurality of 2 / 3-mode frequency dividers 311. The plurality of 2 / 3-mode frequency dividers are cascaded. An inverter 313 and a NAND gate 312 are provided between the last two 2 / 3-mode frequency dividers. The output ends of the last two 2 / 3-mode frequency dividers are connected to a selector 314, so that the frequency division ratio is extended to be adjustable between 16 and 63. The phase switching unit 320 includes: a pulse generator (pulse gen) 321, a counter (counter) 322, a comparator (Compare logic) 323, a clock buffer (clk_buf) 324, a D flip-flop 325 and a state machine (FSM) 326. The output end of the pulse generator 321, the output end of the clock buffer 324, and the output end of the comparator 323 are connected to the input end of the counter 324. The output end of the D flip-flop 325 and the output end of the counter 322 are connected to the input end of the comparator 323. The output end of the comparator 323 and the output end of the clock buffer 324 are connected to the input end of the state machine 325. In this embodiment, the plurality of 2 / 3 modulus dividers 311 is five. Where clk is the output clock signal of the second 2 / 3 modulus divider 311, f DIVIt is the output clock of the multi-mode frequency division unit 310. p<1:0> is the frequency divider control word selection part, which is provided by the last two bits of the frequency divider control word. fsm<1:0> is the running part, which is used to complete the switching process between phases. The clock buffer 324 is used to enhance the driving capability of the multi-mode frequency division unit 310. When the rising edge of clk arrives, the value stored in the counter 322 is increased by 1, and the comparator 323 compares the value of the counter 322 with p<1:0>. When it is less than p<1:0>, the output en is 1, so that the output fsm<1:0> of the state machine 326 is increased by 1 at the next clock rising edge, which also completes a phase switch accordingly. Otherwise, the output en is 0, so that the output fsm<1:0> of the state machine 326 of the next cycle remains unchanged, and the enable signal of the counter 322 is set to zero, indicating that the phase switching unit 320 has completed the phase switching process of this cycle. f DIV When the falling edge is reached, the D flip-flop 325 resamples p<1:0> and sends the result to the input of the comparator 323. DIV When the rising edge of DID The pulse generator 321 generates a reset signal rst of the counter 322 to reset the counter 322, which also marks the beginning of the phase switching of the next cycle.

[0062] The multi-mode frequency division unit 310 is designed as a cascade structure of multiple 2 / 3-mode frequency dividers 311, and uses the frequency division ratio expansion technology to increase the frequency division range of the 2 / 3-mode frequency divider 311. The phase switching unit 320 uses the forward phase switching technology to obtain the original 1 / 4 minimum frequency division step on the basis of adding only a simple digital circuit, thereby improving the frequency division accuracy of the 2 / 3-mode frequency divider 311.

[0063] See also Figure 7-Figure 8 The pipeline phase interpolation module 40 is a multi-stage pipeline structure, and each stage of the pipeline includes: a phase interpolation unit 410 and a multi-way selection unit 420. The output end of the phase interpolation unit 410 is connected to the input end of the multi-way selection unit 420.

[0064] The phase interpolation unit 410 includes three phase interpolators 411. The multi-way selection unit 420 includes: two selectors 421. The two-phase input clocks (Φ_Lead, Φ_Lag) of the clock signal are input into the three phase interpolators 411 in different arrangements. There are three different arrangements of the two-phase input clocks, and the three different arrangements are respectively input into the three phase interpolators 411. The output signals of the three phase interpolators 411 are input into the two selectors in a two-by-two distribution manner. The selection ends of the two selectors receive the phase interpolator control word (DCW), and the phase interpolator control word selects one of the three phase interpolator output signals. Since the two selectors are controlled by the phase interpolator control word, the required output signal can be determined from the output signals of the three phase interpolators 411. That is, the output two-phase clock (Φ_Lead, Φ_Lag) of the phase switching divider module 30 is input into the input end of the pipeline phase interpolation module 40, and the phase interpolator control word (DCW) output by the dynamic element matching and phase selection module is input into the control end of the pipeline phase interpolation circuit. Each stage of the phase interpolation pipeline performs phase interpolation on the input two-phase clock, and the output three-phase clock then passes through the multi-way selection unit 420 to select the required two-phase phase clock according to the phase interpolation control word, and outputs it to the input of the next stage of the phase interpolation pipeline. Finally, the pipeline phase interpolation module 40 performs phase interpolation on the output two-phase clock according to the phase interpolator control word (DCW) to generate the final output clock (Φ_Lead) of the divider. div ).

[0065] The phase interpolator includes: 4 current sources 412, two PMOS tubes 413, two NMOS tubes 414 and an AND gate 415. The sources of the two PMOS tubes 413 and the sources of the two NMOS tubes 414 are connected to the four current sources 412 in a one-to-one correspondence. The gates of the two PMOS tubes 413 and the input of the AND gate 415 are the inputs of the phase interpolator 40. The output of the AND gate 415 is connected to the gates of the two NMOS tubes 414. The drains of the two PMOS tubes 413 and the drains of the two NMOS tubes 414 are the outputs of the phase interpolator 40. Among them, the pull-up network formed by the two PMOS tubes 413 and the pull-down network formed by the two NMOS tubes 414. When the input clock Φ inl , Φ in2 When both are high level, the pull-up network is completely turned off and the pull-down network is completely turned on. At this time, the capacitor ΔC is discharged to a low level. When the input clock Φ inl Low level, Φ in2 When the level is high, the pull-up network is turned off and on at the same time. Since the pull-down network is controlled by an AND gate, the pull-down network is completely turned off at this time, and the capacitor ΔC is The rate of charging is inl , Φ in2 When both are low level, the pull-up network is fully open and the pull-down network is fully closed. At this time, the capacitor ΔC is The rate of charging is Φ o The two-phase input clock Φ inl , Φ in2 The AND gate completely shuts off the pull-down network when one of the input clocks is at a low level and the other is at a high level, thereby eliminating the short-circuit current from the pull-up network to the pull-down network and improving the linearity of the pipeline phase interpolation circuit.

[0066] The pipeline phase interpolation module 40 is designed as a multi-stage pipeline structure, which greatly reduces the area and power consumption of the pipeline phase interpolation module. In addition, the phase interpolation unit 410 uses an AND gate to control the opening and closing of the pull-down network, eliminating the short-circuit current of the phase interpolation unit 410, thereby improving the linearity of the pipeline phase interpolation module 40.

[0067] In summary, the present invention designs the overall structure of the fractional multi-mode divider circuit based on space-time averaging and phase interpolation technology, so that each module cooperates with each other, and uses the third-order noise shaping modulation module and the dynamic element matching and phase selection module to realize the application of space-time averaging technology, and then uses the dynamic element matching and phase selection module to cooperate with the phase switching divider module to realize the application of phase interpolation technology, and at the same time uses the dynamic element matching and phase selection module to combine the space-time averaging technology with the phase interpolation technology. Not only can the phase interpolator work at a low frequency, reducing the area and power consumption of the phase interpolation circuit; it can also simplify the divider array in the space-time averaging technology into a single divider, so that the space-time averaging technology is extended to the sampling phase-locked loop, which greatly improves the limitations of the space-time averaging technology. In addition, the internal structure of each module has been improved to make its effect more significant.

[0068] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology, characterized in that: include: A third-order noise shaping modulation module, a dynamic element matching and phase selection module, a phase switching divider module, and a pipelined phase interpolation module; The third-order noise shaping modulation module is used to perform time averaging on the input frequency division ratio to generate an instantaneous frequency division ratio, and the output end is connected to the input end of the dynamic element matching and phase selection module; The dynamic element matching and phase selection module is used to spatially average the instantaneous frequency division ratio and generate a frequency divider control word and a phase interpolator control word, and the output end is connected to the input end of the phase switching frequency divider module and the input end of the pipeline phase interpolation module; The phase switching frequency divider module is used to generate a clock signal of a corresponding frequency division ratio according to the frequency divider control word, and the output end is connected to the input end of the third-order noise shaping modulation module, the input end of the dynamic element matching and phase selection module, and the input end of the pipeline phase interpolation module; The pipeline phase interpolation module is used to perform phase interpolation according to the clock signal to generate a final clock signal with an accurate phase.

2. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 1, characterized in that: The third-order noise shaping modulation module includes: a linear feedback shift register and a third-order noise shaping modulator; The linear feedback shift register generates a pseudo-random number with a mean value of 0 as jitter added to the third-order noise shaping modulator, and the output end is connected to the input end of the third-order noise shaping modulator; The third-order noise shaping modulator is used to integrate and differentiate the error generated when the decimal part of the input frequency division ratio is rounded down and quantized, perform noise shaping on the quantization noise, and obtain the instantaneous frequency division ratio.

3. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 2, characterized in that: The third-order noise shaping modulator includes: a first first-order modulator, a second first-order modulator and a third first-order modulator; the first first-order modulator, the second first-order modulator and the third first-order modulator are cascaded; the input end of the first first-order modulator is connected to the input frequency division ratio; the input ends of the second first-order modulator and the third first-order modulator are connected to the output end of the linear feedback shift register.

4. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 1, characterized in that: The dynamic element matching and phase selection module includes: a data weight averaging unit and a phase selection unit; The data weight averaging unit is used to perform spatial averaging on the instantaneous frequency division ratio and output a spatial average signal of the instantaneous frequency division ratio, and the output end is connected to the phase selection unit; The phase selection unit is used to convert the spatial average signal of the instantaneous frequency division ratio into a frequency divider control word and a phase interpolator control word.

5. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 4, characterized in that: The data weight averaging unit includes: an accumulator, a code-to-thermometer code and a shift register; the phase selection unit includes: a plurality of symbol calculators and adders; The accumulator and the code-to-thermometer code input terminal are used to receive the instantaneous frequency division ratio; the accumulator and the code-to-thermometer code output terminal are connected to the shift register input terminal; the shift register is used to output the spatial average signal of the instantaneous frequency division ratio; the multiple sign calculator input terminals correspond to the shift register output terminals one by one, and are used to receive the spatial average signal of the instantaneous frequency division ratio; the sign calculator output terminal is connected to the adder input terminal; the adder output terminal is used to output the phase interpolator control word; The frequency divider control word is obtained by adding the spatial average signal end signal of the instantaneous frequency division ratio to the instantaneous frequency division ratio.

6. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 5, characterized in that: The symbol calculator comprises: an XOR gate, a first D flip-flop and a second D flip-flop; The XOR gate input terminal is respectively connected to the spatial average signal of the instantaneous frequency division ratio and the output terminal of the first D flip-flop; the XOR gate output terminal is connected to the input terminal of the first D flip-flop; the output terminal of the first D flip-flop is connected to the input terminal of the second D flip-flop; and the output terminal of the second D flip-flop is connected to the input terminal of the adder. Among them, the multiple symbolic calculator logical expressions are: The N DWA，i [k] is the spatial average signal of the instantaneous frequency division ratio; DWA，A [k] is the end signal of the spatial average signal; the F i [k] is the output signal of the second D flip-flop.

7. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 1, characterized in that: The phase switching frequency divider module comprises: a multi-mode frequency division unit and a phase switching unit; the output end of the phase switching unit is connected to the input end of the multi-mode frequency division unit; the output end of the multi-mode frequency division unit is connected to the input end of the third-order noise shaping modulation module, the input end of the dynamic element matching and phase selection module, and the input end of the pipeline phase interpolation module; the frequency divider control word selection part is transmitted to the phase switching unit, and the operation part is transmitted to the multi-mode frequency division unit; Wherein, the phase switching unit includes: a pulse generator, a counter, a clock buffer, a comparator, a D flip-flop and a state machine; the pulse generator output, the clock buffer output, the comparator output and the counter input are connected; the D flip-flop output and the counter output are connected to the comparator input; the comparator output and the clock buffer output are connected to the state machine input.

8. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 7, characterized in that: The multi-mode frequency division unit comprises: a plurality of 2 / 3-mode frequency dividers; a cascade structure of the plurality of 2 / 3-mode frequency dividers; an inverter and a NAND gate are arranged between the last two 2 / 3-mode frequency dividers, and a selector is connected to the output ends of the last two 2 / 3-mode frequency dividers.

9. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 1, characterized in that: The pipeline phase interpolation module is a multi-stage pipeline structure; each stage of the pipeline includes: a phase interpolation unit and a multi-way selection unit; The phase interpolation unit includes three phase interpolators; the multi-way selection unit includes: two selectors; the two-phase input clocks of the clock signal are input into the three phase interpolators in different arrangements; the three phase interpolator output signals are input into the two selectors in a pairwise distribution manner; wherein the two selector selection ends receive the phase interpolator control word, and the phase interpolator control word selects one of the three phase interpolator output signals.

10. The fractional multi-mode frequency divider circuit based on space-time averaging and phase interpolation technology according to claim 9, characterized in that: The phase interpolator includes: 4 current sources, two PMOS tubes, two NMOS tubes and an AND gate; The two PMOS tube sources and the two NMOS tube sources are connected to the four current sources in a one-to-one correspondence; the two PMOS tube gates and the AND gate input are the phase interpolator inputs; the AND gate output is connected to the two NMOS tube gates; the two PMOS tube drains and the two NMOS tube drains are the phase interpolator outputs.

Images