A high-speed synchronous SAR ADC switching circuit

Abstract

The invention discloses a high-speed synchronous SAR ADC switch circuit, belonging to the technical field of integrated circuits; the invention comprises a coarse successive approximation, a fine successive approximation and a clock generation circuit; the coarse successive approximation comprises CDAC, CCMP and CSAR_LOG; the CDAC is composed of an M-bit switch capacitor array, adopts a sampling method of lower-level board sampling and uses a split capacitor method to split each bit capacitor into two half capacitors; the invention combines coarse successive approximation and fine successive approximation with weak pull-up and weak pull-down switches, redundant bit capacitors and corresponding timing control, thereby alleviating the on-chip decoupling capacitor required by a high-precision, high-speed synchronous SAR ADC due to Vrefp and Vrefn being packaged to parasitic inductance, thereby reducing the chip area and improving the sampling speed of the SAR ADC.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a high-speed synchronous SAR ADC switching circuit. Background Art

[0002] SAR ADC (Successive Approximation Analog-to-Digital Converter) is widely used due to its small area, low power consumption and high performance. Figure 1 This is the block diagram of synchronous SAR ADC, which is mainly composed of capacitor DAC (Digital to Analog converter) array, comparator, REF circuit (reference level drive circuit), clock logic and data logic; synchronous SAR ADC is often the first choice for general-purpose ADC due to its high stability, low noise and simple structure. General-purpose ADC requires the input range to reach the rail-to-rail range, so the reference level will be connected to the outside of the chip through the package line and connected to the power supply voltage on the board. When the sampling rate of the ADC reaches MS / s (megasamples per second) and the resolution of the ADC is ≥12bit (12 bits), due to the parasitic inductance of the package, the speed of the ADC will be limited by the establishment of the reference level, so that the ADC requires a large number of decoupling capacitors, which makes the application of the ADC also need to be accompanied by a considerable additional area to place the decoupling capacitors. Summary of the invention

[0003] In view of the deficiencies in the prior art, an object of the present invention is to provide a high-speed synchronous SAR ADC switch circuit.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] A high-speed synchronous SAR ADC switching circuit, including a coarse successive approximation circuit, a fine successive approximation circuit and a clock generation circuit;

[0006] The coarse successive approximation includes CDAC, CCMP and CSAR_LOG; the input signal and the reference levels Vrefp and Vrefn of the ADC are input to the switch array of CDAC, the capacitor top plates Vtop_cp and Vtop_cn of CDAC are connected to the input of the comparator CCMP, the clock signal of CCMP is CCmp_en, the outputs Qcp and Qcn of CCMP are connected to the input of CSAR_LOG, and CSAR_LOG outputs CDac_ctl <m:1>The switch array control signal connected to CDAC, on the other hand outputs FDac_ctl<N:N-M+1> As the control signal for the first M bits of the switch array of FDAC;

[0007] CDAC is composed of an M-bit switched capacitor array, which adopts the sampling method of the lower board sampling and uses the split capacitor method to split each bit of the capacitor into two half capacitors. When the capacitor is switched, the differential capacitor array is switched to the corresponding capacitor Vrefp and Vrefn to keep the output common mode level of the capacitor array unchanged;

[0008] The fine successive approximation includes FDAC, FCMP and FSAR_LOG; FDAC consists of an N-bit switched capacitor array, adopts the sampling method of the lower board sampling and uses the split capacitor method, where the first M bits of the N-bit capacitor array are controlled by CSAR_LOG, and the first M bits of the capacitor are arrive No need to use split capacitors. A capacitor of the same size is connected to the back and split into two capacitors of the same size and As a redundant bit capacitor, the redundant bit and the following capacitors adopt a split capacitor switching method;

[0009] The output Qfp and Qfn of FCMP are input to the FSAR_LOG module, and the FSAR_LOG module generates FDac_ctl <n-m:1>, as the low-order switched capacitor input control signal of FDAC, and the FSAR_LOG module outputs Dout as the digital output of the ADC successive approximation.

[0010] As a further solution of the present invention, the sampling switch only exists in arrive and , superior.

[0011] As a further embodiment of the present invention, and arrive and The corresponding switches are NMOS connected to Vrefn, PMOS connected to Vrefp to the normal switch, and The corresponding switches are NMOS connected to Vrefn, PMOS connected to Vrefp to the normal switch and the NMOS switch controlled by the bootstrap switch connected to the input terminal Vip.

[0012] As a further embodiment of the present invention, arrive The switch corresponding to the capacitor is connected to the input signal Vip by the NMOS device M0 controlled by the bootstrap switch, the NMOS device M2 is connected to Vrefn as a strong pull-down switch, the PMOS device M1 is connected to Vrefp as a strong pull-up switch, the NMOS device M4 is connected to Vrefn in series with the resistor R2 as a weak pull-down switch, and the PMOS device M3 is connected to Vrefp in series with the resistor R1 as a weak pull-up switch.

[0013] Compared with the existing solutions, the present invention has the following beneficial effects:

[0014] The present invention combines coarse successive approximation and fine successive approximation with weak pull-up and weak pull-down switches, redundant bit capacitors and corresponding timing control, and can alleviate the on-chip decoupling capacitor required for high-precision and high-speed synchronous SAR ADC due to Vrefp and Vrefn being packaged to parasitic inductance, thereby reducing the chip area and improving the sampling speed of the SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A structural schematic diagram of a synchronous SAR ADC block diagram.

[0016] Figure 2 This is a high-speed synchronous SAR ADC switch circuit in the present invention.

[0017] Figure 3 It is a timing diagram of the high-speed synchronous SAR ADC switch circuit in the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present invention are provided for the purpose of illustration and description, and are not intended to be exhaustive or to limit the present invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

[0019] Example 1

[0020] Reference Figure 2-Figure 3 As shown, the present invention is a high-speed synchronous SAR ADC switch circuit, which includes a coarse successive approximation circuit, a fine successive approximation circuit and a clock generation circuit.

[0021] The coarse successive approximation includes CDAC (coarse successive approximation switch capacitor array), CCMP (coarse successive approximation comparator), CSAR_LOG (coarse successive approximation logic), the input signal and the reference levels Vrefp and Vrefn of the ADC are input to the switch array of CDAC, the capacitor top plates Vtop_cp and Vtop_cn of CDAC are connected to the input of the comparator CCMP, the clock signal of CCMP is CCmp_en, the outputs Qcp and Qcn of CCMP are connected to the input of CSAR_LOG, and CSAR_LOG outputs CDac_ctl <m:1>The switch array control signal connected to CDAC, on the other hand outputs FDac_ctl<N:N-M+1> As the control signal for the first M bits of the switch array of FDAC.

[0022] CDAC is composed of an M-bit switched capacitor array. It adopts the sampling method of the lower-level board sampling and uses the split capacitor method to split each bit of capacitance into two half capacitors. When the capacitor is switched, the differential capacitor array is cut to the corresponding capacitors Vrefp and Vrefn to keep the output common-mode level of the capacitor array unchanged.

[0023] The fine successive approximation includes FDAC (fine successive approximation switched capacitor array), FCMP (fine successive approximation comparator) and FSAR_LOG (fine successive approximation logic).

[0024] The outputs Qfp and Qfn of FCMP are input to the FSAR_LOG module. The FSAR_LOG module generates FDac_ctl <n-m:1>, as the low-order switched capacitor input control signal of FDAC. The FSAR_LOG module outputs Dout as the digital output of the ADC successive approximation.

[0025] FDAC is composed of an N-bit switched capacitor array, adopts the sampling method of the lower board sampling and uses the split capacitor method, where the switches of the first M bits (N to N-M+1) of the N-bit capacitor array are controlled by CSAR_LOG, and the first M bits of the capacitor , arrive No need to use split capacitors. A capacitor of the same size is connected to the back and split into two identical capacitors and As a redundant bit capacitor, the redundant bit and the subsequent capacitor , arrive , and arrive The sampling switch only has split capacitor switching. arrive and and Yes, from and arrive and The corresponding switches are NMOS connected to Vrefn and PMOS connected to Vrefp to ordinary switches. and The corresponding switches are NMOS connected to Vrefn, PMOS connected to Vrefp to the normal switch and the NMOS switch controlled by the bootstrap switch connected to the input terminal Vip. arrive The switch corresponding to the capacitor is connected to the input signal Vip by the NMOS device M0 controlled by the bootstrap switch, the large width-to-length ratio NMOS device M2 is connected to Vrefn as a strong pull-down switch, the large width-to-length ratio PMOS device M1 is connected to Vrefp as a strong pull-up switch, the small width-to-length ratio NMOS device M4 is connected to Vrefn with a series resistor R2 as a weak pull-down switch, and the small width-to-length ratio PMOS device M3 is connected to Vrefp with a series resistor R1 as a weak pull-up switch.

[0026] See also Figure 3 , Figure 3 This is the timing diagram of the high-speed synchronous SAR ADC switch circuit. Clk_in is used as the synchronization clock of the entire high-speed synchronous SAR ADC. Clk_in generates the sampling clock CKS, CCMP clock signal Ccmp_en, and FCMP clock signal fcmp_en through the clock generation circuit. In the sampling stage, CKS is high, and the bootstrap sampling switch is turned on to connect the input signals Vip and Vin to the sampling capacitors of CDAC and FDAC. After the sampling is completed, CKS is pulled low. After half a clock cycle of the falling edge of CKS, Ccmp_en starts the CCMP comparator judgment at a high level to obtain Qcp and Qcn. After CASR_LOG, CDac_ctl is obtained. <m>The value of the capacitor array is obtained after the switch to obtain the capacitance to the bottom plate level CDac_O <m>Similarly, when the next Ccmp_en high level starts, the CCMP comparator judges and obtains Qcp and Qcn. After CASR_LOG, CDac_ctl is obtained. <m-1>The value of the capacitor array is obtained after the switch to obtain the capacitance to the bottom plate level CDac_O <m-1>. CSAR_LOG generates CDac_ctl <2> FDac_ctl will also be generated at the same time<N-M+2> ,control arrive The corresponding weak pull-up switch M3 and R1 or weak pull-down switch M4 and R2, after the weak pull-up and pull-down switches, the bottom plate potential of the capacitor slowly rises or falls to avoid overshoot of the reference level Vrefp and Vrefn. The next Ccmp_en high level to the CCMP comparator judgment result Qcp, Qcn, after CASR_LOG, CDac_ctl is obtained. <1> The value of FDac_ctl<N-M+1> Thus controlling The corresponding weak pull-up switch M3 and R1 or weak pull-down switch M4 and R2, the bottom plate potential of the same capacitor rises or falls slowly to avoid overshoot of the reference level Vrefp, Vrefn. It takes 1.5 clock cycles from the last rising edge of Ccmp_en to the first rising edge of Fcmp_en, which is half a clock cycle longer than the 1 clock cycle between the two Ccmp_en rising edges and the 1 clock cycle between the Fcmp_en rising edges. The first Fcmp_en rising edge corresponds to the first judgment result of FCMP, and then FDac_ctl is obtained after FASR_LOG.<N-M+1> , control redundant capacitor and The switch arrive The strong pull-up switch M1 or the strong pull-down switch M2 is turned on, providing capacitance arrive The connection to Vrefp and Vrefn is to the low-resistance channel. The subsequent FCMP is obtained and the judgment result is gradually generated by the FASR_LOG module. <n-m>to FDac_ctl <1> , and finally generates the ADC output digital signal Dout through the FASR_LOG module.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention. < / m> < / m>

Claims

1. A high-speed synchronous SARADC switching circuit, characterized in that: It includes coarse successive approximation, fine successive approximation and clock generation circuits; The coarse successive approximation includes CDAC, CCMP and CSAR_LOG; the input signal and the reference levels Vrefp and Vrefn of the ADC are input to the switch array of CDAC, the capacitor top plates Vtop_cp and Vtop_cn of CDAC are connected to the input of the comparator CCMP, the clock signal of CCMP is CCmp_en, the outputs Qcp and Qcn of CCMP are connected to the input of CSAR_LOG, and CSAR_LOG outputs CDac_ctl <m:1> The switch array control signal connected to CDAC, on the other hand outputs FDac_ctl<N:N-M+1> As the control signal for the first M bits of the switch array of FDAC;< / m:1> CDAC is composed of an M-bit switched capacitor array, which adopts the sampling method of the lower board sampling and uses the split capacitor method to split each bit of the capacitor into two half capacitors. When the capacitor is switched, the differential capacitor array is switched to the corresponding capacitor Vrefp and Vrefn to keep the output common mode level of the capacitor array unchanged; The fine successive approximation includes FDAC, FCMP and FSAR_LOG; FDAC is composed of an N-bit switch capacitor array, adopts the sampling method of the lower board sampling and uses the split capacitor method, where the first M bits of the N-bit capacitor array are controlled by CSAR_LOG, and the first M bits of the capacitor Cf n To Cf n-m+1 No need to use split capacitors, Cf n-m+1 A capacitor of the same size is connected to the back and split into two capacitors of the same size Cf (n-m+1)u and Cf (n-m+1)d As a redundant bit capacitor, the redundant bit and the subsequent capacitor Cf (0)u and Cf (0)d , Cf (1)u and Cf (1)d To Cf (n-m)u and Cf (n-m)d Adopt split capacitor switching method; The output Qfp and Qfn of FCMP are input to the FSAR_LOG module, and the FSAR_LOG module generates FDac_ctl <n-m:1> , as the low-order switched capacitor input control signal of FDAC, and the FSAR_LOG module output Dout as the digital output of the ADC successive approximation;< / n-m:1> The sampling switch only exists at Cf n To Cf n-m+1 and Cf (n-m+1)u , Cf (n-m+1)d superior; From Cf (n-m)u and Cf (n-m)d To Cf 0u and Cf 0d The corresponding switch is a common switch with NMOS connected to Vrefn and PMOS connected to Vrefp. (n-m+1)u and Cf (n-m+1)d The corresponding switches are ordinary switches with NMOS connected to Vrefn and PMOS connected to Vrefp, and an NMOS switch controlled by a bootstrap switch connected to the input terminal Vip; Cf n To Cf n-m+1 The switch corresponding to the capacitor is connected to the input signal Vip by the NMOS device M0 controlled by the bootstrap switch, the NMOS device M2 is connected to Vrefn as a strong pull-down switch, the PMOS device M1 is connected to Vrefp as a strong pull-up switch, the NMOS device M4 is connected to Vrefn in series with the resistor R2 as a weak pull-down switch, and the PMOS device M3 is connected to Vrefp in series with the resistor R1 as a weak pull-up switch.

2. A high-speed synchronous SARADC switching circuit according to claim 1, characterized in that: Clk_in is the synchronization clock of the entire high-speed synchronous SAR ADC. Clk_in generates the sampling clock CKS of FDAC and CDAC and the clock signals Ccmp_en and Fcmp_en of CCMP through the clock generation circuit. In the sampling stage, CKS is high, and the bootstrap sampling switch is turned on to connect the differential input signals Vip and Vin to the differential sampling capacitors of CDAC and FDAC. After the sampling is completed, CKS is pulled low. After half a clock cycle, Ccmp_en starts the high level of CCMP's comparator judgment to obtain the results of Qcp and Qcn, and CDac_ctl is obtained after CSAR_LOG. <m>The same conversion process is used to obtain the value from CDac_ctl <m>to CDac_ctl <2> , in CDac_ctl <2> CSAR_LOG updates FDac_ctl synchronously while updating <n>to FDac_ctl<N-M+2> The value of Cf n To Cf n-m+2 The corresponding weak pull-up switch M3 and R1 or the weak pull-down switch M4 and R2, after the weak pull-up and pull-down switches, the bottom plate potential of the capacitor rises or falls slowly, avoiding overshoot of the reference level Vrefp, Vrefn due to severe disturbance;< / n> < / m> < / m> The next Ccmp_en high level to CCMP comparator judgment results Qcp, Qcn, after CASR_LOG to get CDac_ctl <1> The value of FDac_ctl<N-M+1> Thus controlling Cf n-m+1 The corresponding weak pull-up switch M3 and R1, weak pull-down switch M4 and R2, the bottom plate potential of the same capacitor rises or falls slowly to avoid overshoot of the reference levels Vrefp and Vrefn; from the last rising edge of Ccmp_en to the first rising edge of Fcmp_en, it is extended by 1.5 clock cycles to give the slow switch a longer setup time; the first rising edge of Fcmp_en corresponds to the first judgment result of FCMP, and then FDac_ctl is obtained after FASR_LOG.<N-M+1> , control the redundant capacitor Cf (n-m+1)u and Cf (n-m+1)d switch, and Cf n To Cf n-m+1 The strong pull-up switch M1 or the strong pull-down switch M2 is turned on, providing the capacitor Cf n To Cf n-m+1 The low-resistance channel connected to Vrefp and Vrefn, and the judgment result of FCMP is obtained and gradually generates FDac_ctl through the FASR_LOG module <n-m> to FDac_ctl <1> , and finally generates the ADC output digital signal Dout through the FASR_LOG module.< / n-m>

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