WB algorithm hardware architecture based on early stop mechanism
By introducing a WB algorithm hardware architecture based on the early stop mechanism in the RS code decoding algorithm, the WB algorithm is transformed from the time domain to the frequency domain, and the difference value and polynomial update are processed in parallel, the problem of excessive resource consumption in the hardware implementation of the existing RS code decoding algorithm is solved, and the improvement of lower latency and power consumption is achieved.
Patent Information
- Application Number
- CN202410908221.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2025-02-28
AI Technical Summary
The existing RS code decoding algorithms have high circuit area and time delay in hardware implementation, and cannot adapt to diverse application scenarios, especially when solving key equations and calculations of differential values, the resource consumption is too large, resulting in high system delay and power consumption.
A hardware architecture of WB algorithm based on early stop mechanism is proposed, which transforms the WB algorithm from the time domain to the frequency domain, and shortens the critical path and improves the system's main frequency by processing the difference values and polynomial updates in parallel. In addition, the early stop mechanism stops the calculation in advance when specific conditions are met, which significantly reduces power consumption.
By processing the difference values and polynomial updates in parallel, the critical path length of the hardware implementation is shortened, the system delay is reduced and the main frequency is improved. In addition, the application of the early shutdown mechanism significantly reduces power consumption, making the hardware more efficient.
Smart Images
Figure CN119543960A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of decoding technology, and in particular to a hardware architecture of a WB algorithm based on an early stopping mechanism. Background Art
[0002] As a classic linear block code, Reed-Solomon (RS) code has received extensive attention and application since its introduction due to its superior ability to correct burst errors. It has a good development prospect in many fields such as wireless transmission, optical communication, deep space communication and data storage. With the large-scale expansion of global Internet applications and the increasing popularity of services such as cloud computing, big data and the Internet of Things, the amount of data in communication systems is increasing, and the requirements for communication quality are also increasing. However, the complex decoding algorithm of RS code leads to its large hardware circuit area and high latency, which makes it increasingly unable to adapt to various application scenarios. The RS decoding algorithm needs further research and improvement.
[0003] The decoding process of RS code can be divided into the following three steps:
[0004] 1. Calculate the syndrome;
[0005] 2. Solve key equations;
[0006] 3. Money Search and Misvaluation
[0007] Solving the key equation is a relatively complex step in the decoding process, and the hardware implementation requires more resources. The implementation algorithm of this module determines the overall performance of the RS decoder to a large extent.
[0008] The shortcomings of the existing decoding architecture are mainly in the following aspects:
[0009] The RS decoding algorithm based on FFT cannot use the RiBM hardware architecture with fewer resources because the form of the key equation is not suitable for the RiBM algorithm. The time-domain WB algorithm requires an additional FFT module. It cannot adapt to the increasingly complex application scenarios of RS codes and the increasing requirements for decoding performance in terms of computational complexity and hardware consumption.
[0010] Difference value in WB algorithm The calculation is performed temporarily in each round of iteration, so the calculation of the difference value and the update of the polynomial are performed serially, which will result in a longer critical path and higher latency in hardware implementation. The difference value in this technology has been calculated in the previous round of iteration, so it can be performed in parallel with the update of the polynomial, shortening the critical path and improving the main frequency of the entire system.
[0011] Both the RiBM algorithm and the WB algorithm use a one-dimensional systolic array architecture when implemented in hardware. Both require 2t (t is the error correction capability of the RS code) cycles to obtain the error position polynomial, which causes all processing units to be in a normally open state, resulting in a waste of power consumption. Summary of the invention
[0012] To solve the above problems, the present invention provides a hardware architecture of a WB algorithm based on an early stopping mechanism, and transforms the WB algorithm from the time domain to the frequency domain, thereby improving the overall performance of the decoder.
[0013] To achieve the above object, the technical solution adopted by the present invention is:
[0014] A hardware architecture of a WB algorithm based on an early stopping mechanism, characterized in that it includes a control module and a processing unit, wherein the processing unit includes a PE0 processing unit array and a PE1 processing unit array, wherein the PE0 processing unit array includes 2t PE0s, and the PE1 processing unit array includes t+1 PE1s; wherein each PE0 includes 3 registers, two multipliers and one adder, and each PE1 includes 2 registers, two multipliers and one adder;
[0015] The control module is used to initialize registers, control iterations and detect early stopping mechanisms;
[0016] The PE0 array is used to perform polynomial update calculations;
[0017] The PE1 array is used to perform difference value update calculation;
[0018] The control module executes the early stop mechanism through the Enable_PE signal. If the preset early stop mechanism is not satisfied, the Enable_PE signal is pulled high and the processing unit is controlled to work; if the preset early stop mechanism is satisfied, the Enable_PE signal is lowered, the processing unit does not work and returns the output polynomial.
[0019] Furthermore, the control module includes:
[0020] An initialization unit, used to initialize the registers in each processing unit;
[0021] An iteration control module, used to coordinate the work of each processing unit in each iteration;
[0022] The early stop detection unit is used to determine whether the early stop mechanism is satisfied and to control the working state of the processing unit.
[0023] Furthermore, the initialization unit is used to initialize t+1 groups of auxiliary polynomials, 2t groups of difference values and the rank of the auxiliary polynomials. After the initialization is successful, the Enable_PE signal is pulled high.
[0024] Furthermore, the iterative control module is used to execute a maximum of 2t cycles, and each cycle first updates the intermediate parameter δ generated in each round of updating process. [r] , and then update and calculate the difference value of 2t groups in parallel t+1 group of auxiliary polynomials and the rank of the auxiliary polynomial Where r is the number of cycles.
[0025] Furthermore, the intermediate parameter δ generated in each round of updating process [r] Update as follows:
[0026]
[0027] Furthermore, the difference value Update as follows:
[0028]
[0029] Among them, ω i are elements of the vector space.
[0030] Furthermore, the auxiliary polynomial Update as follows:
[0031]
[0032] Furthermore, the rank of the auxiliary polynomial Update according to the following formula:
[0033]
[0034] Furthermore, the preset early stopping mechanism is
[0035] The beneficial effects of the present invention are as follows: the present invention proposes a hardware architecture of a WB algorithm based on an early stopping mechanism, including a control module and a processing unit, the processing unit including a PE0 processing unit array and a PE1 processing unit array, each PE0 including 3 registers, two multipliers and an adder, each PE1 including 2 registers, two multipliers and an adder, so as to realize the calculation of the difference value and the update of the polynomial in parallel, shorten the critical path length of the hardware implementation, and reduce the system delay. The difference value is calculated in the last round of iteration, so it can be carried out in parallel with the update of the polynomial, and the main frequency of the whole system is improved. The frequency domain variant FEPWB algorithm that can be implemented in the hardware architecture can stop the calculation in advance when the early stopping mechanism is met, and significantly reduce the power consumption. When the number of errors e is less than or equal to t times, the result can be obtained without looping 2t times, and the calculation can be stopped and the result (key equation polynomial) can be obtained after only performing t+e calculations at most, so that the multipliers and adders can be dynamically disabled when the calculation is not needed in the hardware implementation, so as to achieve the purpose of reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 It is a structural diagram of the hardware architecture of a WB algorithm based on an early stopping mechanism in the present invention.
[0037] Figure 2 This is the data update flow chart of PE0 in the present invention
[0038] Figure 3 It is a circuit diagram of PE0 in the present invention.
[0039] Figure 4 It is a circuit diagram of PE1 in the present invention. DETAILED DESCRIPTION
[0040] See also Figure 1-4 As shown, the present invention relates to a structure of a hardware architecture of a WB algorithm based on an early stopping mechanism.
[0041] A hardware architecture of a WB algorithm based on an early stopping mechanism, characterized in that it includes a control module and a processing unit, wherein the processing unit includes a PE0 processing unit array and a PE1 processing unit array, wherein the PE0 processing unit array includes 2t PE0s, and the PE1 processing unit array includes t+1 PE1s; wherein each PE0 includes 3 registers, two multipliers and one adder, and each PE1 includes 2 registers, two multipliers and one adder;
[0042] The control module is used to initialize registers, control iterations and detect early stopping mechanisms;
[0043] The PE0 array is used to perform polynomial update calculations;
[0044] The PE1 array is used to perform difference value update calculation;
[0045] The control module executes the early stop mechanism through the Enable_PE signal. If the preset early stop mechanism is not satisfied, the Enable_PE signal is pulled high and the processing unit is controlled to work; if the preset early stop mechanism is satisfied, the Enable_PE signal is lowered, the processing unit does not work and returns the output polynomial.
[0046] It should be noted that Figure 1 The first row of the array consists of PE0s, and the structure of each PE0 is as follows Figure 3 As shown in Figure 1, it is used to complete the matrix operation in line 5 of the FEPWB algorithm. The data update flow chart of the register in PE0 is as follows: Figure 2 As shown, the following takes the rth round of loop as an example to illustrate (Note: the values in the three registers in are not 0). First, the three registers involved in the operation are provided by , and the value of is directly stored in the third register of . Two general multipliers implement and respectively, and then an adder is used to add the two to obtain , and store them in the first register of . Then is selected according to the value of and multiplied to obtain , and stored in the second register of . It can be found that as the iteration proceeds, the values of the three registers in PE0 are moved to the left by one processing unit after calculation at each clock, so this architecture is called a systolic array architecture. The reason why PE0 is designed to move one processing unit to the left in each iteration is that this can ensure that and are always on the left side of and are directly sent to the control module, which can save a circuit for selecting and .
[0047] Figure 1 The second row of arrays consists of PE1s, and the structure of PE1 is as follows Figure 4 As shown, it is used to complete the matrix operation of line 8 in the FEPWB algorithm. The update rules of PE1 and PE0 are the same, the difference is that after the update, it does not need to move to the left, but is stored in the corresponding register of the current processing unit, which can save power consumption. At the same time, due to the application of the early stopping mechanism, the output of the architecture is also output from a fixed position.
[0048] The control module is responsible for calculating δ [r] ,ω r and Enable_PE signals, and connect these three signals to Broadcast to each processing unit. The early stop mechanism is implemented by the signal Enable_PE. When the early stop mechanism is not satisfied, the Enable_PE signal will be pulled high, so that all processing units can be enabled to work. Otherwise, the processing unit will not work and keep the original data unchanged.
[0049] Furthermore, the control module includes:
[0050] An initialization unit, used to initialize the registers in each processing unit;
[0051] An iteration control module, used to coordinate the work of each processing unit in each iteration;
[0052] The early stop detection unit is used to determine whether the early stop mechanism is satisfied and to control the working state of the processing unit.
[0053] Furthermore, the initialization unit is used to initialize t+1 groups of auxiliary polynomials, 2t groups of difference values and the rank of the auxiliary polynomials. After the initialization is successful, the Enable_PE signal is pulled high.
[0054] Furthermore, the iterative control module is used to execute a maximum of 2t cycles, and each cycle first updates the intermediate parameter δ generated in each round of updating process. [r] , and then update and calculate the difference value of 2t groups in parallel t+1 group of auxiliary polynomials and the rank of the auxiliary polynomial Where r is the number of cycles.
[0055] Furthermore, the intermediate parameter δ generated in each round of updating process [r] Update as follows:
[0056]
[0057] Furthermore, the difference value Update as follows:
[0058]
[0059] Among them, ω i are elements of the vector space.
[0060] Furthermore, the auxiliary polynomial Update as follows:
[0061]
[0062] Furthermore, the rank of the auxiliary polynomial Update according to the following formula:
[0063]
[0064] Furthermore, the preset early stopping mechanism is
[0065] The FEPWB algorithm is shown in Algorithm 2:
[0066] Algorithm 2:The frequency-domain EPWB(FEPWB)algorithm
[0067]
[0068]
[0069] Step 1: Initialization;
[0070] Initialize the values that need to be updated before the loop calculation starts.
[0071]
[0072] The superscripts indicate the number of cycles.
[0073] Step 2: Perform multiple loop operations;
[0074] (1) In each cycle, the intermediate parameter δ generated during the round update process is first updated [r] , the following difference value Auxiliary polynomial and the rank of the auxiliary polynomial Can be done in parallel,
[0075] (2) Calculate when i = 0, 1, ..., 2t-1, a total of 2t groups
[0076] (3) Calculate a total of t+1 groups
[0077] (4) According to δ [r] Is it 1 to execute separately
[0078] (5) Final basis Is it true to return the output incomplete polynomial (W [r+1] (x0),W [r+1] (x1),…,W [r+1] (x t )).
[0079] In one embodiment, when the early stopping mechanism After satisfying or completing 2t calculations, the hardware architecture output of the WB algorithm based on the early stopping mechanism is the incomplete error position polynomial in ω0,ω1,…,ω t Valuation on: According to the key equation: We can get incomplete error estimation polynomials at ω0,ω1,…,ω t-1 The valuation on: (z1(ω0),z1(ω1),…,z1(ωt-1 ))=(λ1(ω0)s(ω0),λ1(ω1)s(ω1),…,λ1(ω t-1 )s(ω t-1 )).
[0080] In a hardware architecture of a WB algorithm based on an early stopping mechanism, the whole process of solving the key equation is as follows:
[0081] (1) It takes one clock to complete the initialization of the registers in each processing unit. The initial value of the register is already in Figure 1 After successful initialization, the Enable_PE signal is pulled high to enable all processing units to work.
[0082] (2) It takes multiple clocks to complete multiple cycles and update the polynomial. After each clock updates the polynomial, PE0 needs to move one processing unit to the left, and PE1 stores the updated result in the original register. If the early stopping mechanism is not satisfied, the polynomial update is repeated.
[0083] (3) After the early stop mechanism is satisfied, the Enable_PE signal is pulled low, all registers stop working, and the internal registers no longer flip.
[0084] (4) At the th clock, the incomplete error location polynomial is taken out from the first register of PE1.
[0085] In the complete decoding process, after the received vector enters the decoder, it first passes through the syndrome calculation module to calculate the frequency domain syndrome. Then we enter the hardware architecture of the parallel WB algorithm with early stopping mechanism and get and After multiplication, we get And perform IFFT operation on the two to obtain the incomplete error polynomial λ1(x) and the incomplete error estimation polynomial z1(x). Then enter the money search and error estimation module, where the money search is to find the zero point of the incomplete error polynomial λ1(x) as the error position, and the error estimation needs to use the new error estimation formula proposed in this paper, that is: Finally, the obtained result is added to the received vector to obtain the decoding result.
[0086] The specific process is as follows:
[0087] A binary extension domain It can be viewed as an m-dimensional vector space on F2. Denote a basis on the vector space by represents an element on the vector space, then each element ω i It can be expressed as in is the binary representation of i, that is
[0088] Binary extension domain On (n = 2 m ,k) RS code can be defined as:
[0089]
[0090] Note that each codeword is a polynomial in The multi-point estimates at these points can be efficiently calculated by LCH-FFT. The error correction capability of this (n,k) RS code is:
[0091] In the decoding process, (r0, r1…, r n-1 ) represents the receiving vector, (c0,c1,…,c n-1 )∈C represents the transmission codeword, represents the error vector, then: (r0,r1…,r n-1 )=(c0,c1,…,c n-1 )+(e0,e1,…,e n-1 );
[0092] The operator '+' means Bitwise addition on . Define the error position polynomial where ε={ω i :e i ≠0} is the set of error positions.
[0093] Let s(x) represent the companion polynomial and z(x) represent the error estimate polynomial, then the key equation can be expressed as
[0094] The problem to be solved in solving the key equation is: given the companion equation s(x), find λ(x) and z(x) that satisfy the key equation, requiring deg(z(x))<t, deg(λ(x))≤t.
[0095] After calculating λ(x) and z(x), the error estimate can be obtained by the following formula:
[0096]
[0097] By introducing the concept of an incomplete error location polynomial, denoted by λ1(x), which satisfies λ1(x)|λ(x) and Let λ(x)=λ0(x)λ1(x), then We can obtain λ0(x)|z(x); therefore, the incomplete error estimate polynomial is defined Then when i≥nk:
[0098]
[0099] Therefore, the error value can be obtained by only finding the incomplete error position polynomial λ1(x) and the incomplete error estimation polynomial z1(x).
[0100] The above implementation modes are merely descriptions of the preferred implementation modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary engineering and technical personnel in the field shall fall within the protection scope determined by the claims of the present invention.
Claims
1. A hardware architecture of a WB algorithm based on an early stopping mechanism, characterized in that: It includes a control module and a processing unit, wherein the processing unit includes a PE0 processing unit array and a PE1 processing unit array, wherein the PE0 processing unit array includes 2t PE0s, and the PE1 processing unit array includes t+1 PE1s; wherein each PE0 includes 3 registers, two multipliers and one adder, and each PE1 includes 2 registers, two multipliers and one adder; The control module is used to initialize registers, control iterations and detect early stopping mechanisms; The PE0 array is used to perform polynomial update calculations; The PE1 array is used to perform difference value update calculation; The control module executes the early stop mechanism through the Enable_PE signal. If the preset early stop mechanism is not satisfied, the Enable_PE signal is pulled high and the processing unit is controlled to work; If the preset early stopping mechanism is satisfied, the Enable_PE signal is lowered to disable the processing unit and return the output polynomial.
2. According to the hardware architecture of the WB algorithm based on the early stopping mechanism of claim 1, it is characterized in that: The control module comprises: An initialization unit, used to initialize the registers in each processing unit; An iteration control module, used to coordinate the work of each processing unit in each iteration; The early stop detection unit is used to determine whether the early stop mechanism is satisfied and to control the working state of the processing unit.
3. According to the hardware architecture of the WB algorithm based on the early stopping mechanism according to claim 2, it is characterized in that: The initialization unit is used to initialize t+1 groups of auxiliary polynomials, 2t groups of difference values and the rank of the auxiliary polynomials. After the initialization is successful, the Enable_PE signal is pulled high.
4. According to the hardware architecture of the WB algorithm based on the early stopping mechanism of claim 2, it is characterized in that: The iterative control module is used to execute a maximum of 2t cycles, and each cycle first updates the intermediate parameter δ generated in each round of update process. [r] , and then update and calculate the difference value of 2t groups in parallel t+1 group of auxiliary polynomials and the rank of the auxiliary polynomial Where r is the number of cycles.
5. The hardware architecture of the WB algorithm based on the early stopping mechanism according to claim 4 is characterized in that: The intermediate parameter δ generated in each round of updating process [r] Update as follows:
6. The hardware architecture of the WB algorithm based on the early stopping mechanism according to claim 4, characterized in that: The difference value Update as follows: Among them, ω i are elements of the vector space.
7. The hardware architecture of the WB algorithm based on the early stopping mechanism according to claim 5, characterized in that: The auxiliary polynomial Update as follows:
8. The hardware architecture of the WB algorithm based on the early stopping mechanism according to claim 5, characterized in that: The rank of the auxiliary polynomial Update according to the following formula:
9. The hardware architecture of the WB algorithm based on the early stopping mechanism according to claim 2, characterized in that: The preset early stopping mechanism is