RDMA and CXL protocol bidirectional high-speed conversion method, device and system

Abstract

The invention belongs to the field of FPGA (field programmable gate array) application design, and provides an RDMA (remote direct memory access) and CXL (common X-ray language) protocol bidirectional high-speed conversion method, which adopts a brand-new FPGA heterogeneous bidirectional protocol conversion idea as a core design idea; mass resources of an FPGA chip are used as an architecture carrier, a function kernel is designed in a pipeline mode, and protocol conversion is executed in a bidirectional concurrent mode. Centralized management is achieved, a plurality of different RDMA and CXL devices are comprehensively coordinated to efficiently complete communication protocol conversion tasks in parallel, and then real-time communication of different devices is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA application design, and in particular relates to a method, device and system for bidirectional high-speed conversion between RDMA and CXL protocols. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Currently, RDMA (Remote Direct Memory Access) and CXL (Compute Express Link) technologies have been widely used in many fields. However, due to technical barriers and protocol incompatibility, devices that only support the RDMA protocol and devices that only support the CXL protocol cannot directly communicate and exchange data, which significantly limits the efficient interaction between devices. To solve the above problems, although purchasing or upgrading equipment can achieve a certain degree of compatibility, the cost is high; software protocol conversion heavily relies on CPU collaborative participation, the protocol conversion efficiency is low, and it causes significant consumption of device CPU computing resources, affecting the overall system performance. Summary of the invention

[0004] In order to solve at least one of the technical problems existing in the above-mentioned background technology, the present invention provides a method, device and system for bidirectional high-speed conversion between RDMA and CXL protocols, which are used to meet the needs of high-efficiency conversion between RDMA and CXL protocols in the context of the big data era, so as to fundamentally solve the incompatibility problem between RDMA and CXL devices.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A first aspect of the present invention provides a method for high-speed bidirectional conversion between RDMA and CXL protocols, comprising the following steps:

[0007] receiving access requests from a plurality of request source devices;

[0008] Determine whether the target device address is directly connected to the switch corresponding to the current request source device. If so, the request source device directly accesses the storage of the target device address through the corresponding switch to receive the target data.

[0009] Otherwise, determine the type of the target device. If the target device is an RDMA device, identify the device type of the CXL request source device and the supported CXL protocol, and package the request details for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals.

[0010] If the target device is a CXL device, identify the device type and supported CXL protocol of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals;

[0011] The data after protocol conversion is sent to the request source device.

[0012] Furthermore, the protocol conversion from the CXL protocol signal to the RDMA protocol signal includes:

[0013] Receive original access request messages of various CXL protocols;

[0014] Decode the original access request messages of various CXL protocols and decompose them to obtain the CXL source address, RDMA target address, data length, CXL protocol version serial number and corresponding transmission data information in the original message;

[0015] The transmission data is grouped according to the CXL protocol version serial number, the grouped data is decoded according to the corresponding CXL protocol, the decomposed current signal is re-encoded, the re-encoding result is verified, and the converted data is obtained.

[0016] Further, the various CXL protocols include CXL1.0, CXL1.1, CXL2.0, CXL3.0 and CXL3.1 protocols.

[0017] Furthermore, the protocol conversion from the RDMA protocol signal to the CXL protocol signal includes:

[0018] Receive original messages that comply with the RDMA protocol;

[0019] Decode the original message that complies with the RDMA protocol to obtain the RDMA source address, CXL target address, data length, conversion requirement CXL protocol version serial number and corresponding transmission data information in the original message;

[0020] According to the conversion requirements, the CXL protocol version serial number reads the storage partitions corresponding to different versions, packages the decoded data and the data of different storage partitions, and encodes them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

[0021] Furthermore, the original access request messages of the various CXL protocols and the original messages conforming to the RDMA protocol are decoded in sequence according to the IPC / IP signal format.

[0022] A second aspect of the present invention provides a high-speed bidirectional conversion device between RDMA and CXL protocols, comprising a CXL-RDMA protocol conversion module, an RDMA-CXL protocol conversion module, a first conversion interface and a second conversion interface; one end of the first conversion interface is connected to the input end of the CXL-RDMA protocol conversion module, and the other end is connected to the output end of the RDMA-CXL protocol conversion module; one end of the second conversion interface is connected to the output end of the CXL-RDMA protocol conversion module, and the other end is connected to the input end of the RDMA-CXL protocol conversion module;

[0023] The CXL-RDMA protocol conversion module is configured to: identify the device type and supported CXL protocol of the CXL request source device, and package the request details for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals;

[0024] The RDMA-CXL protocol conversion module is configured to: identify the device type and supported CXL protocol of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals.

[0025] Further, the CXL-RDMA protocol conversion module includes a first TCP / IP signal decoding module, a CXL sub-protocol identification module, a plurality of sub-protocol decoding modules and an RDMA signal re-encoding module;

[0026] The TCP / IP signal decoding module is used to decode the original access request messages of various CXL protocols, and decompose the CXL source address, RDMA target address, data length, CXL protocol version serial number and corresponding transmission data information in the original message;

[0027] The CXL sub-protocol identification module is used to group the transmission data according to the CXL protocol version sequence number;

[0028] The multiple sub-protocol decoding modules are used to decode the packetized data according to the corresponding CXL protocol;

[0029] The RDMA signal encoding module is used to re-encode the decomposed current signal to obtain re-encoded data.

[0030] Further, the RDMA-CXL protocol conversion module includes a second TCP / IP signal decoding module and a plurality of sub-protocol encoding modules;

[0031] The second TCP / IP signal decoding module is used to decode the original message that complies with the RDMA protocol to obtain the RDMA source address, CXL target address, data length, conversion requirement CXL protocol version sequence number and corresponding transmission data information in the original message;

[0032] The multiple sub-protocol encoding modules are used to read storage partitions corresponding to different versions according to the conversion requirement CXL protocol version serial number, package the decoded data and the data of different storage partitions, and encode them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

[0033] Further, the device also includes a RDMAX signal transmission verification module and a CXL signal transmission verification module;

[0034] The RDMAX signal sending verification module is used to verify the RDMA protocol and TPC / IP format of the input data respectively, and after the verification is passed, the input data is sent to the RDMA switch in sequence;

[0035] The CXL signal sending verification module is used to verify the CXL protocol and TPC / IP format of the input data, and after the verification is passed, the input data is sent to the CXL switch in sequence.

[0036] A third aspect of the present invention provides a bidirectional conversion system between RDMA and CXL protocols, comprising a CXL device cluster, an RDMA device cluster, a CXL switch, an RDMA switch, and the apparatus described in the second aspect;

[0037] The CXL device cluster is connected to one end of the CXL switch, the other end of the CXL switch is connected to one end of the device, the other end of the device is connected to one end of the RDMA switch, and the other end of the RDMA switch is connected to the RDMA device cluster. Each CXL device cluster includes several different types of CXL devices, and each RDMA device cluster includes several RDMA hosts including CPUs, Buffers, and RDMA engines.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention adopts the brand-new "FPGA heterogeneous bidirectional protocol conversion" idea as the core design concept; uses the massive resources of FPGA chips as the architecture carrier, functional core pipeline design, and bidirectional concurrent execution of protocol conversion; realizes centralized management and overall coordination of multiple different RDMA and CXL devices to efficiently and parallelly complete communication protocol conversion tasks, thereby realizing real-time communication between different devices; fundamentally solves the incompatibility problem between RDMA and CXL devices.

[0040] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0042] Figure 1 This is an architecture diagram of a bidirectional conversion system between RDMA and CXL protocols provided by an embodiment of the present invention;

[0043] Figure 2 This is an architecture diagram of an FPGA-based RDMA-CXL protocol high-speed conversion device provided by an embodiment of the present invention;

[0044] Figure 3 is a flow chart of an application method for access request of a CXL device provided by an embodiment of the present invention;

[0045] Figure 4 is a flow chart of an application method for access request of an RDMA device provided by an embodiment of the present invention;

[0046] Figure 5 The present invention provides an FPGA core architecture design for an RDMA-CXL protocol high-speed conversion device. DETAILED DESCRIPTION

[0047] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0048] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0049] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0050] RDMA (Remote Direct Memory Access), remote direct data storage, was created to solve the latency of terminal data processing during network transmission. RDMA allows user-mode applications to directly read or write remote memory without kernel intervention and memory copying. Initially, it was only used in the field of high-performance computing. Recently, due to the increasingly prominent network bottlenecks in large-scale distributed systems and data centers, it has gradually entered the field of vision of more and more people.

[0051] CXL (Compute Express Link) is a new device interconnection technology standard that has become a new technology in the industry to break through the bottleneck of data exchange efficiency. It is not only used for memory capacity / bandwidth expansion, but also for heterogeneous interconnection and data center resource pool decoupling. In the data center, CXL technology can interconnect different computing and storage resources to complete data transmission and exchange tasks with higher system performance and efficiency.

[0052] In order to solve the problem of incompatibility between RDMA and CXL devices, the FPGA-based RDMA-CXL protocol high-speed conversion device of the present invention adopts the new "FPGA heterogeneous bidirectional protocol conversion" idea as the core design concept; uses the massive resources of FPGA chips as the architecture carrier, functional core pipeline design, and bidirectional concurrent execution of protocol conversion; realizes centralized management and overall coordination of multiple different RDMA and CXL devices to efficiently and parallelly complete the communication protocol conversion task, thereby realizing real-time communication between different devices;

[0053] The FPGA-based RDMA-CXL protocol high-speed conversion device designed by the present invention is compatible with multiple versions of CXL protocols such as CXL1.0, 1.1, 2.0, 3.0, 3.1, etc., supports all types of CXL devices such as CXL Type1, CXL Type2, CXL Type3, etc., and has a wide range of applications; and the CXL device cluster and RDMA device cluster that can be carried by the designed protocol conversion device support any number of access devices to expand, and the access is flexible; in addition, the FPGA-based RDMA-CXL protocol high-speed conversion device is responsible for protocol conversion by the functional core of the FPGA, and the pipeline design supports single-time bidirectional concurrent conversion, which significantly improves the protocol conversion and signal transmission efficiency of the system, and the present invention does not require the CPU of the access device to perform auxiliary operations, which greatly reduces the computing load of the device; at the same time, the design provides a detailed application method of the FPGA-based RDMA-CXL protocol high-speed conversion device, which can better realize the designed unified scheduling control and significantly improve the application performance of the CXL-RDMA hybrid system.

[0054] Figure 1It is an FPGA-based RDMA-CXL protocol high-speed conversion device architecture, including a CXL device cluster, an RDMA device cluster, a CXL switch, and an RDMA switch;

[0055] Each CXL device cluster includes several CXL Type1-NIC data accelerator card devices, CXL Type2-data accelerator card devices with storage, CXL Type3-CXL memory pool and other devices;

[0056] Each RDMA device cluster consists of several RDMA hosts including CPU, Buffer, and RDMA engine;

[0057] The CXL device cluster deploys several CXL application devices that can support any protocol of CXL1.0, CXL1.1, CXL2.0, CXL3.0, and CXL3.1. These devices are connected to the CXL switch through the network. Different CXL devices can directly exchange information through the CXL switch.

[0058] The RDMA device cluster deploys several RDMA hosts that support the RDMA transmission protocol. These devices are connected to the RDMA switch through the network. Different RDMA hosts can directly exchange information through the RDMA switch.

[0059] The CXL switch and the RDMA switch are respectively connected to the FPGA-based RDMA-CXL protocol high-speed conversion device through network cables. The high-speed conversion between the CXL protocol and the RDMA protocol is completed through the protocol conversion device, thereby completing the real-time communication between the CXL device cluster devices and the RDMA device cluster devices.

[0060] Figure 2 It is an FPGA-based RDMA-CXL protocol high-speed conversion device architecture, which includes two parts: core board hardware design and FPGA chip module design. The RDMA-CXL protocol high-speed conversion device hardware board includes FPGA chip, peripheral electronic devices, DDR4 memory, peripheral interface and PCB board.

[0061] The FPGA contains the application engineering module structure and specific information processing methods required for the normal operation of the RDMA-CXL protocol bidirectional high-speed conversion (the specific FPGA module composition and working mechanism are given in Part 3 of the specification); peripheral electronic devices include power supply interface, power supply chip, clock chip and necessary resistors and capacitors; peripheral interfaces include JTAG debugging interface, PCIe interface, and 2 Gigabit network ports. The PCB board is responsible for providing a carrier for FPGA chips and peripheral electronic devices.

[0062] The board is responsible for completing the collection, processing, and sending of information transmitted by the industrial wireless sensor network. It is also responsible for the power supply, clock input, various forms of IO communication of the FPGA core chip, and information interaction with the peripheral interface.

[0063] Gigabit network port 1 is connected to the CXL switch and is responsible for sending and receiving CXL protocol related signals; Gigabit network port 2 is connected to the RDMA switch and is responsible for sending and receiving RDMA protocol related signals;

[0064] For example, if the CXL protocol needs to be converted to the RDMA protocol, the FPGA receives the CXL signal sent by the CXL switch through Gigabit Ethernet port 1, and after completing the protocol conversion, sends the conversion result RDMA signal to the RDMA switch through Gigabit Ethernet port 2;

[0065] The application method of the FPGA-based RDMA-CXL protocol high-speed conversion device is divided into two parts: the access request of the CXL device and the access request of the RDMA.

[0066] Figure 3 The flowchart of the application method of the access request of the CXL device is shown, which specifically includes the following steps:

[0067] Step 1: The CXL device sends a data read access request to the CXL switch, including the target device address, target data storage address, and other information;

[0068] Step 2: The CXL switch receives the request and verifies the legitimacy of the source device address that sent the request.

[0069] Step 3: After the legitimacy verification is passed, the CXL switch determines whether the target device address has been directly connected to the current CXL switch. If yes, it jumps to step 4; if not, it jumps to step 6;

[0070] Step 4: The target device is a CXL device, and CXL requests the source device to directly access the storage of the target device address through the CXL switch;

[0071] Step 5: The CXL source device directly receives the target data through the CXL switch and jumps to step 10;

[0072] Step 6: If the target device is an RDMA device, the CXL switch identifies the device type and supported CXL protocol of the source device, and packages it with the request details for the target device and sends it to the FPGA-based RDMA-CXL protocol high-speed conversion device through Gigabit Ethernet port 1;

[0073] Step 7: The RDMA-CXL protocol high-speed conversion device performs IPC / IP signal decoding, CXL protocol decoding, RDMA signal recoding and other processes to complete the CXL to RDMA protocol conversion, and sends the converted request to the RDMA switch through Gigabit network port 2;

[0074] Step 8: The RDMA switch receives the request, directly extracts the corresponding requested target data from the target RDMA device, and sends it back to the RDMA-CXL protocol high-speed conversion device through Gigabit network port 2 in the RDMA protocol format;

[0075] Step 9: The RDMA-CXL protocol high-speed conversion device converts the received RDMA protocol format data into the CXL protocol format of the target device, and then sends the access result to the source CXL device through the CXL switch;

[0076] Step 10: Complete the data read access request.

[0077] Figure 4 The flowchart of the application method of access request of RDMA device is shown, including the following steps:

[0078] Step 1: The RDMA device sends a data read access request to the RDMA switch, including the target device address, target data storage address, and other information;

[0079] Step 2: The RDMA switch receives the request and verifies the legitimacy of the source device address that sends the request;

[0080] Step 3: After the legitimacy verification is passed, the RDMA switch determines whether the target device address has been directly connected to the current RDMA switch. If yes, it jumps to step 4; if not, it jumps to step 6;

[0081] Step 4: The target device is an RDMA device, and the RDMA request source device directly accesses the storage of the target device address through the CXL switch;

[0082] Step 5: The RDMA engine of the RDMA source device directly receives the target data through the RDMA switch and jumps to step 10;

[0083] Step 6: If the target device is a CXL device, the RDMA switch identifies the device type and supported CXL protocol of the target CXL device, and packages it with the request details for the target device and sends it to the FPGA-based RDMA-CXL protocol high-speed conversion device through Gigabit network port 2;

[0084] Step 7: The RDMA-CXL protocol high-speed conversion device performs IPC / IP signal decoding, RDMA protocol decoding, CXL signal recoding and other processes to complete the RDMA to CXL protocol conversion, and sends the converted request to the CXL switch through Gigabit network port 1;

[0085] Step 8: The CXL switch receives the request converted to the CXL protocol of the target device, directly extracts the corresponding target data from the target CXL device, and sends it back to the RDMA-CXL protocol high-speed conversion device through Gigabit network port 1 in the CXL protocol format;

[0086] Step 9: The RDMA-CXL protocol high-speed conversion device converts the received CXL protocol format data into the RDMA protocol format of the target device, and then sends the access result to the request source RDMA device through the RDMA switch;

[0087] Step 10: Complete the data read access request.

[0088] Figure 5 An FPGA core architecture for an RDMA-CXL protocol high-speed conversion device, including a CXL-RDMA protocol conversion partition and an RDMA-CXL protocol conversion partition;

[0089] Specifically, it includes CXL input data caching module, TPC / IP signal decoding module, CXL sub-protocol identification module, CXL1.0 / 1.1 protocol decoding module, CXL2.0 protocol decoding module, CXL3.0 / 3.1 protocol decoding module, RDMA signal recoding, TPC / IP signal encoding module, RDMA signal sending verification module, RDMA input data caching module, TPC / IP signal decoding module, MIG, CXL protocol encoding information acquisition FSM state machine, CXL1.0 / 1.1 protocol encoding module, CXL2.0 protocol encoding module, CXL3.0 / 3.1 protocol encoding module, CXL data aggregation and collection module, TPC / IP signal encoding module, CXL signal sending verification module, etc.

[0090] The operation of the FPGA core architecture of the RDMA-CXL protocol high-speed conversion device can be divided into two relatively independent stages:

[0091] 1. Convert CXL protocol signals to RDMA protocol signals;

[0092] This stage is performed by the CXL-RDMA protocol conversion partition of the FPGA.

[0093] When Gigabit Ethernet port 1 receives the original message that complies with the CXL1.0 / CXL1.1 / CXL2.0 / CXL3.0 / CXL3.1 protocol from the CXL switch, the CXL input data buffer module buffers the original data and sends it to the TPC / IP signal decoding module in sequence according to the IPC / IP signal format;

[0094] The TPC / IP signal decoding module decodes the received information, decomposes the CXL source address, RDMA target address, data length, CXL protocol version serial number and corresponding transmission data information in the original data, and sends it to the CXL sub-protocol identification module;

[0095] The CXL sub-protocol identification module identifies the CXL protocol version serial number (a single CXL-RDMA protocol conversion only allows the same CXL sub-protocol), divides the protocol into CXL1.0 / CXL1.1 group, CXL2.0 group, and CXL3.0 / CXL3.1 group according to the sub-protocol version, and sends the module input data to the CXL1.0 / CXL1.1 protocol decoding module, CXL2.0 protocol decoding module, and CXL3.0 / CXL3.1 protocol decoding module in a 64-bit AHB bus format according to the category; the CXL1.0 / CXL1.1 protocol decoding module, CXL2.0 protocol decoding module, and CXL3.0 / CXL3.1 protocol decoding module perform CXL protocol decoding specified by the corresponding sub-protocol on the input data, decompose all the original data of the current signal, and package and send it to the RDMA signal re-encoding module;

[0096] The RDMA signal recoding module performs encoding operations on the input data according to the RDMA protocol requirements, and sends the recoded information to the TPC / IP signal encoding module; the TPC / IP signal encoding module performs the encoding operations required for TPC / IP transmission on the input signal, and sends the results to the RDMA signal transmission verification module;

[0097] The RDMA signal sending verification module caches the received data, verifies the RDMA protocol and TPC / IP format of the input data respectively, and sends the input data to the RDMA switch via Gigabit network port 2 in sequence after the verification.

[0098] 2. Convert RDMA protocol signals to CXL protocol signals;

[0099] This stage is performed by the RDMA-CXL protocol conversion partition of the FPGA.

[0100] When Gigabit Ethernet port 2 receives the original message that complies with the RDMA protocol from the RDMA switch, the RDMA input data cache module caches the original data and sends it to the TPC / IP signal decoding module in sequence according to the IPC / IP signal format;

[0101] The TPC / IP signal decoding module decodes the received information, decomposes the RDMA source address, CXL target address, data length, conversion requirement CXL protocol version serial number and corresponding transmission data information in the original data, and sends it to the CXL protocol encoding information acquisition FSM state machine;

[0102] After the CXL protocol encoding information acquisition FSM state machine receives the TPC / IP signal decoding result, it controls the MIG storage reading module to read the corresponding storage partition of DDR4 according to the conversion requirement CXL protocol version serial number (CXL1.0 / CXL1.1 / CXL2.0 / CXL3.0 / CXL3.1 protocol), reads the corresponding CXL protocol conversion mode requirement information (including header signal, frame information, transmission step signal, etc.), and packages this information with the data to be converted received from the TPC / IP signal decoding module and distributes it to the corresponding CXL1.0 / CXL1.1 protocol encoding module, CXL2.0 protocol encoding module, CXL3.0 / CXL3.1 protocol encoding module (a single RDMA-CXL protocol conversion only allows the conversion of the same CXL sub-protocol); CXL1.0 / CXL1.1 protocol encoding module, CXL2.0 protocol encoding module, CXL3.0 / CXL3.1 protocol encoding module perform CXL protocol encoding specified by the corresponding sub-protocol on the input data, obtain the CXL protocol conversion result of the input original data and send the corresponding result to the CXL data aggregation collection module in sequence;

[0103] After receiving the CXL data of the target length, the CXL data aggregation and collection module aggregates and caches all input data, and packages all CXL protocol conversion results and sends them to the TPC / IP signal encoding module;

[0104] The TPC / IP signal encoding module performs the encoding operation required for TPC / IP transmission on the input signal and sends the result to the CXL signal sending verification module; the CXL signal sending verification module caches the received data, verifies the CXL protocol and TPC / IP format of the input data respectively, and after the verification is passed, sends the input data to the CXL switch in sequence through Gigabit Ethernet port 1.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for high-speed bidirectional conversion between RDMA and CXL protocols, comprising the following steps: receiving access requests from a plurality of request source devices; Determine whether the target device address is directly connected to the switch corresponding to the current request source device. If so, the request source device directly accesses the storage of the target device address through the corresponding switch to receive the target data. Otherwise, determine the type of the target device. If the target device is an RDMA device, identify the device type of the CXL request source device and the supported CXL protocol, and package the request details for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals. If the target device is a CXL device, identify the device type and supported CXL protocol of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals; The data after protocol conversion is sent to the request source device.

2. A method for high-speed bidirectional conversion between RDMA and CXL protocols as claimed in claim 1, characterized in that: The protocol conversion from CXL protocol signals to RDMA protocol signals includes: Receive original access request messages of various CXL protocols; Decode the original access request messages of various CXL protocols and decompose them to obtain the CXL source address, RDMA target address, data length, CXL protocol version serial number and corresponding transmission data information in the original message; The transmission data is grouped according to the CXL protocol version serial number, the grouped data is decoded according to the corresponding CXL protocol, the decomposed current signal is re-encoded, the re-encoding result is verified, and the converted data is obtained.

3. A method for high-speed bidirectional conversion between RDMA and CXL protocols as claimed in claim 1, characterized in that: The various CXL protocols include CXL1.0, CXL1.1, CXL2.0, CXL3.0 and CXL3.1 protocols.

4. A method for high-speed bidirectional conversion between RDMA and CXL protocols as claimed in claim 1, characterized in that: The protocol conversion from RDMA protocol signals to CXL protocol signals includes: Receive original messages that comply with the RDMA protocol; Decode the original message that complies with the RDMA protocol to obtain the RDMA source address, CXL target address, data length, conversion requirement CXL protocol version serial number and corresponding transmission data information in the original message; According to the conversion requirements, the CXL protocol version serial number reads the storage partitions corresponding to different versions, packages the decoded data and the data of different storage partitions, and encodes them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

5. A method for high-speed bidirectional conversion between RDMA and CXL protocols as claimed in claim 2 or 4, characterized in that: The original access request messages of various CXL protocols and the original messages conforming to the RDMA protocol are decoded in sequence according to the IPC / IP signal format.

6. A device for bidirectional high-speed conversion between RDMA and CXL protocols, comprising a CXL-RDMA protocol conversion module, an RDMA-CXL protocol conversion module, a first conversion interface and a second conversion interface; one end of the first conversion interface is connected to the input end of the CXL-RDMA protocol conversion module, and the other end is connected to the output end of the RDMA-CXL protocol conversion module; one end of the second conversion interface is connected to the output end of the CXL-RDMA protocol conversion module, and the other end is connected to the input end of the RDMA-CXL protocol conversion module; The CXL-RDMA protocol conversion module is configured to: identify the device type and supported CXL protocol of the CXL request source device, and package the request details for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals; The RDMA-CXL protocol conversion module is configured to: identify the device type and supported CXL protocol of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals.

7. The device for bidirectional high-speed conversion between RDMA and CXL protocols as claimed in claim 6, characterized in that: The CXL-RDMA protocol conversion module includes a first TCP / IP signal decoding module, a CXL sub-protocol identification module, a plurality of sub-protocol decoding modules and an RDMA signal re-encoding module; The TCP / IP signal decoding module is used to decode the original access request messages of various CXL protocols, and decompose the CXL source address, RDMA target address, data length, CXL protocol version serial number and corresponding transmission data information in the original message; The CXL sub-protocol identification module is used to group the transmission data according to the CXL protocol version sequence number; The multiple sub-protocol decoding modules are used to decode the packetized data according to the corresponding CXL protocol; The RDMA signal encoding module is used to re-encode the decomposed current signal to obtain re-encoded data.

8. The device for bidirectional high-speed conversion between RDMA and CXL protocols as claimed in claim 6, characterized in that: The RDMA-CXL protocol conversion module includes a second TCP / IP signal decoding module and a plurality of sub-protocol encoding modules; The second TCP / IP signal decoding module is used to decode the original message that complies with the RDMA protocol to obtain the RDMA source address, CXL target address, data length, conversion requirement CXL protocol version sequence number and corresponding transmission data information in the original message; The multiple sub-protocol encoding modules are used to read storage partitions corresponding to different versions according to the conversion requirement CXL protocol version serial number, package the decoded data and the data of different storage partitions, and encode them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

9. The device for bidirectional high-speed conversion between RDMA and CXL protocols as claimed in claim 6, characterized in that: The device also includes a RDMAX signal transmission verification module and a CXL signal transmission verification module; The RDMAX signal sending verification module is used to verify the RDMA protocol and TPC / IP format of the input data respectively, and after the verification is passed, the input data is sent to the RDMA switch in sequence; The CXL signal sending verification module is used to verify the CXL protocol and TPC / IP format of the input data, and after the verification is passed, the input data is sent to the CXL switch in sequence.

10. A bidirectional high-speed conversion system between RDMA and CXL protocols, characterized in that: comprising a CXL device cluster, an RDMA device cluster, a CXL switch, an RDMA switch, and the apparatus according to any one of claims 6 to 9; The CXL device cluster is connected to one end of the CXL switch, the other end of the CXL switch is connected to one end of the device, the other end of the device is connected to one end of the RDMA switch, and the other end of the RDMA switch is connected to the RDMA device cluster. Each CXL device cluster includes several different types of CXL devices, and each RDMA device cluster includes several RDMA hosts including CPUs, Buffers, and RDMA engines.

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