A low power consumption detection circuit based on OSP protocol

Abstract

The invention discloses a low-power detection circuit based on an OSP protocol, comprising: a clock source, an OSP detection circuit, a low-pass filter, an enabling circuit, a gating circuit and a timeout detection circuit; wherein a low-pass filter, an enabling circuit and a gating circuit are further arranged between the clock source and the OSP detection circuit; and a filtered output signal of the low-pass filter is loaded into the enabling circuit, the rising edge of the signal is used as the clock of a first DFF trigger in the enabling circuit, and the falling edge of the signal is used as the clock of a second DFF trigger in the enabling circuit; in the process of OSP signal detection of the invention, the clock of the OSP detection circuit is turned on only when a detection port of an external device changes, and the clock is in a closed state at other times, thereby greatly reducing power consumption.

Description

Technical Field

[0001] The present invention relates to the field of OSP technology, in particular to a low-power consumption detection circuit based on the OSP protocol. Background Art

[0002] The OSP protocol can be divided into the physical layer, data link layer and network layer. The physical layer completes the definition of electrical characteristics, physical connection definition, and Manchester encoding and decoding; the data link layer completes the definition of OSP data packet structure, message type definition, and conflict management; the network layer defines some applications, such as automatic addressing instructions.

[0003] refer to Figure 1 The physical layer has two I / O interfaces, each of which independently supports different communication modes, which are selected by connecting pull-up resistors and pull-down resistors to VDD (power supply) and GND (ground) respectively; among them,

[0004] CAN (USE) mode, which supports communication with microcontroller units, transceivers, and nodes through two independent transmit and receive lines (Tx and Rx), and the communication on each line is unidirectional;

[0005] LVDS mode, which supports inter-node communication and reduces electromagnetic interference (EMI) through differential signaling. The bit stream is Manchester encoded. This mode is selected by two pull-down resistors (which may be included in the node);

[0006] EOL mode is used to indicate that the unit is at the end of the link, that is, it is either the first or the last in the link. This mode can be selected by two different pull-up resistor configurations: the first is to connect a pull-up resistor to the SIOP pin of the device and a pull-down resistor to the SION pin. The second is to connect a pull-up resistor to the SION pin of the device and a pull-down resistor to the SIOP pin. Therefore, in the idle state in this mode, the SIOP pin is high and the SION pin is low, or the SIOP pin is low and the SION pin is high.

[0007] refer to Figure 2 The current osp detection circuit loads a clock source at the input end of the osp detection circuit. Since the Manchester encoding of the OSP protocol is 2.4Mhz, a high-frequency clock (such as 72Mhz) must be used to complete the detection during detection and decoding, so the power consumption of the entire module is high.

[0008] Existing technologies can no longer meet people's needs at this stage. Based on the current situation, it is urgent to improve existing technologies. Summary of the invention

[0009] The purpose of the present invention is to provide a low power consumption detection circuit based on the OSP protocol to solve the problems raised in the above background technology.

[0010] The present invention provides the following technical solution: a low-power detection circuit based on the OSP protocol, comprising: a clock source, an OSP detection circuit, a low-pass filter, an enable circuit, a gating circuit and a timeout detection circuit; wherein a low-pass filter, an enable circuit and a gating circuit are further provided between the clock source and the OSP detection circuit; and, a data end of the low-pass filter is externally connected to a detection port of a reception detection device, and a clock end of the low-pass filter is connected to a clock source; and the output end of the low-pass filter is respectively loaded to the enable circuit, the OSP detection circuit and the timeout detection circuit;

[0011] The low-pass filter is used as a pre-filter of the OSP detection circuit to filter out burrs less than 2.4x0.92%mhz;

[0012] The enabling circuit comprises: a first DFF trigger, a second DFF trigger and an OR gate; wherein the output ends of the first DFF trigger and the second DFF trigger are respectively connected to two input pins of the OR gate, and the output pin of the OR gate is connected to the gate control circuit as the enabling end of the enabling circuit; the asynchronous reset ends of the first DFF trigger and the second DFF trigger are connected to the output end of the timeout detection circuit;

[0013] The gating circuit comprises: a latch and an AND gate; the data end of the latch is connected to the enable end of the enable circuit, and the output end of the latch is connected to an input pin of the AND gate, and the other input pin of the AND gate and the enable end of the latch are connected to a clock source; the output pin of the AND gate is loaded into the OSP detection circuit and the timeout detection circuit as the gating clock of the gating circuit;

[0014] The OSP detection circuit is used to detect the OSP signal. Any change of the OSP signal can be used as the enable of the gated clock. When the gated clock is enabled, the gated clock is turned on.

[0015] The timeout detection circuit includes: a third DFF trigger, an XOR gate, an OR gate, a counter and a threshold judgment module; wherein the data end and the clock end of the third DFF trigger are respectively connected to the output end of the low-pass filter and the output end of the gate control circuit, and the output end of the low-pass filter and the output end of the third DFF trigger are respectively connected to two input ends of the XOR gate; the clock end of the counter is connected to the gated clock output by the gate control circuit, and the output end of the counter and the timeout threshold setting end are commonly connected to the threshold judgment module, and the output end of the threshold judgment module and the output end of the XOR gate are connected to the reset control end of the counter through the OR gate.

[0016] When the gated clock arrives, the counter of the timeout detection circuit starts counting; when the time for which the level of the detection port of the external reception detection device remains unchanged is less than or equal to the fixed threshold set by the timeout threshold setting end, the counter keeps counting; when the time for which the level of the detection port of the external reception detection device remains unchanged is greater than the fixed threshold set by the timeout threshold setting end, the threshold judgment module outputs a timeout pulse to clear the enable circuit and clear the count of the counter at the same time.

[0017] The present invention has the following beneficial effects:

[0018] During the OSP signal detection process of the present invention, the gated clock of the OSP detection circuit is turned on only when the detection port of the external device changes, and the gated clock is in a closed state at other times, which greatly reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the structure in which the pull-up resistor and pull-down resistor of the device are connected to VDD and GND respectively;

[0020] Figure 2 It is a structural schematic diagram of the high power consumption OSP detection circuit described in the background technology;

[0021] Figure 3 It is a schematic diagram of the overall structure of the present invention;

[0022] Figure 4 It is a schematic diagram of the specific structure of the enabling circuit of the present invention;

[0023] Figure 5 It is a structural schematic diagram of the gate control circuit of the present invention;

[0024] Figure 6 It is a structural schematic diagram of the timeout detection circuit of the present invention;

[0025] Figure 7 It is a timing diagram of the low-pass filter output signal of the present invention;

[0026] Figure 8 It is a timing diagram of the timeout detection circuit of the present invention when it is working;

[0027] Fig. 9 This is a timing diagram of the present invention when the communication mode is configured as CAN mode;

[0028] Fig.10 It is a timing diagram of the present invention when the communication mode is configured as LVDS mode;

[0029] Fig.11 It is a schematic diagram of the clock timing of the OSP detection circuit with high power consumption described in the background technology during operation. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field of the present invention without creative work are within the scope of protection of the present invention.

[0031] refer to Figure 3 The present invention provides the following technical solution: a low-power detection circuit based on the OSP protocol, comprising: a clock source, an OSP detection circuit, and a low-pass filter, an enabling circuit and a gating circuit are arranged between the clock source and the OSP detection circuit; wherein,

[0032] One data end of the low-pass filter is connected to the detection port of the reception detection device, and the clock end of the low-pass filter is connected to the clock source; and the output end of the low-pass filter is respectively loaded to the enabling circuit, the OSP detection circuit and the timeout detection circuit; the low-pass filter is used as a pre-filter of the OSP detection circuit, which can effectively prevent glitches smaller than 2.4x0.92%mhz from affecting the detection results; reference Figure 7 In this embodiment, when the communication mode is selected and configured as CAN mode, the SION pin of the device is connected to a pull-up resistor and is high by default. When the input low level is less than 2.4x0.92% MHz, the glitch is filtered out and the subsequent circuit does not work.

[0033] refer to Figure 4 The enabling circuit includes: a first DFF trigger (DFF1), a second DFF trigger (DFF2) and an OR gate; wherein the output ends of the first DFF trigger and the second DFF trigger are respectively connected to the two input pins of the OR gate, and the output pin of the OR gate is connected to the gating circuit as the enabling end of the enabling circuit; the asynchronous reset ends of the first DFF trigger and the second DFF trigger are mutually connected to the output end of the timeout detection circuit; when the signal filtered by the low-pass filter is output to the enabling circuit, the rising edge of the signal is used as the clock of the first DFF trigger in the enabling circuit, and the falling edge of the signal is used as the clock of the second DFF trigger in the enabling circuit, and the OSP detection circuit is used to detect the OSP signal, and any change of the OSP signal can be used as the enablement of the subsequent gating clock, and when the timeout flag of the timeout detection circuit arrives, the first DFF trigger and the second DFF trigger are reset.

[0034] refer to Figure 5, the gating circuit comprises: a latch and an AND gate; the data end of the latch is connected to the enable end of the enable circuit, and the output end of the latch is connected to an input pin of the AND gate, and the other input pin of the AND gate and the enable end of the latch are connected to a clock source; the output pin of the AND gate is loaded into the OSP detection circuit and the timeout detection circuit as the gating clock of the gating circuit; the gating clock is turned on only when the gating clock is enabled;

[0035] In this embodiment, the gate control circuit may also be another structure, including: a latch and an OR gate; the connection mode of the OR gate in the gate control circuit is the same as that of the AND gate, and the OR gate may directly replace the AND gate.

[0036] refer to Figure 6 , the timeout detection circuit includes: a third DFF trigger, an XOR gate, an OR gate, a counter and a threshold judgment module; wherein the data end and the clock end of the third DFF trigger are respectively connected to the output end of the low-pass filter and the output end of the gate control circuit, and the output end of the low-pass filter and the output end of the third DFF trigger are jointly loaded to the XOR gate; the clock end of the counter is connected to the gated clock output by the gate control circuit, and the output end of the counter and the timeout threshold setting end are jointly connected to the threshold judgment module, and the output end of the threshold judgment module and the output end of the XOR gate are connected to the reset control end of the counter through the OR gate;

[0037] refer to Figure 8 The timeout detection circuit completes the timeout detection by detecting the detection port SIOP / SION of the external reception detection device. When the gated clock arrives, the timeout detection circuit starts counting; when the output of the low-pass filter changes, the output terminal Q of the third DFF trigger will also change accordingly. The changed signal edge causes the XOR gate to generate a pulse or1 to clear the counter; at other times, the counter is always counting; when the level of the detection port SIOP / SION remains unchanged for a time greater than the fixed threshold set at the timeout threshold setting terminal, the threshold judgment module outputs a timeout pulse, thereby pulling up the pulse or2 to clear the counter count; and the timeout pulse resets the enabling circuit at the same time, turns off the gated clock, and the reception of this data packet ends.

[0038] refer to Fig. 9As an optional implementation of the present invention, in this embodiment, when the communication mode is configured as CAN mode, the ECU (electronic controller unit) sends a broadcast data packet, and the SION and SIOP pins are connected to pull-up resistors, which are high by default, and when the SION pin receives a normal data packet of the OSP protocol, after passing through a low-pass filter, the data packet is output normally, and when the first falling edge arrives, this falling edge will be inverted as a clock, and the output end Q of the second DFF trigger will be pulled high, thereby pulling the enable of the enable circuit high, and the gated clock is output, and the OSP detection circuit uses the gated clock to complete the detection. When the data of this data packet is received, the SION pin remains unchanged, and after the timeout detection circuit detects a timeout overflow, a timeout pulse is sent to reset the second DFF trigger, and the gated clock is turned off;

[0039] refer to Fig.10 As an optional implementation of the present invention, in this embodiment, when the communication mode is configured as LVDS mode, the ECU (electronic controller unit) sends a broadcast data packet to the device, and the SION and SIOP pins of the device are connected to pull-down resistors and are low by default. In the OSP protocol, when a node is idle (at least no signal changes within the timeout period) and any of the two lines changes its logic state, this is considered a start condition. When a transmission is completed, the line remains in a static state for at least the timeout period, which is regarded as a stop condition; the OSP protocol stipulates that in LVDS mode, 2 bits of start and stop high levels need to be sent before and after the OSP data packet; when the SION pin receives a normal OSP data packet, the data packet is output normally after passing through the low-pass filter. When the first rising edge arrives, this rising edge sets the first DFF trigger, and then the enable of the enable circuit is pulled high, the gated clock is output, and the OSP detection circuit uses the gated clock to complete the detection; when the LVDS mode stop is received, the SION pin is pulled low and remains unchanged. After the timeout detection circuit detects the timeout overflow, it sends a timeout pulse to reset the first DFF trigger, and the gated clock is turned off.

[0040] As an optional implementation of the present invention, in this embodiment, refer to Figure 2 and Fig.11 In order to detect that the data packets on the external receiving detection device are not lost, the traditional OSP detection circuit must detect the status of the detection port of the external device in real time. Figure 2 As can be seen from the clock timing diagram, the clock of the OSP detection circuit is always on and the power consumption is high; Fig. 9 or Fig.10In the above implementation mode of the present invention, the gated clock of the OSP detection circuit is turned on only when the detection port of the external device changes, and the gated clock is turned off at other times, which greatly reduces power consumption.

[0041] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low power consumption detection circuit based on the OSP protocol, comprising a clock source and an OSP detection circuit, characterized in that: It also includes a timeout detection circuit, and a low-pass filter, an enabling circuit and a gating circuit are provided between the clock source and the OSP detection circuit; the gating clock of the OSP detection circuit is turned on only when the detection port of the external device changes, and the gating clock is in a closed state at other times; One data end of the low-pass filter is connected to a detection port of a reception detection device, and one clock end of the low-pass filter is connected to a clock source; And the output end of the low-pass filter is respectively loaded to the enabling circuit, the OSP detection circuit and the timeout detection circuit; The enabling circuit comprises: a first DFF trigger, a second DFF trigger and an OR gate; wherein the output ends of the first DFF trigger and the second DFF trigger are respectively connected to two input pins of the OR gate, and the output pin of the OR gate is connected to the gate control circuit as the enabling end of the enabling circuit; the asynchronous reset ends of the first DFF trigger and the second DFF trigger are connected to the output end of the timeout detection circuit; The gating circuit comprises: a latch and an AND gate; the data end of the latch is connected to the enable end of the enable circuit, and the output end of the latch is connected to an input pin of the AND gate, and the other input pin of the AND gate and the enable end of the latch are connected to a clock source; the output pin of the AND gate is connected to the OSP detection circuit and the timeout detection circuit as the gating clock of the gating circuit; The timeout detection circuit includes: a third DFF trigger, an XOR gate, an OR gate, a counter and a threshold judgment module; wherein the data end and the clock end of the third DFF trigger are respectively connected to the output end of the low-pass filter and the output end of the gate control circuit, and the output end of the low-pass filter and the output end of the third DFF trigger are respectively connected to the two input ends of the XOR gate; the clock end of the counter is connected to the gated clock output by the gate control circuit, and the output end of the counter and the timeout threshold setting end are commonly connected to the threshold judgment module, and the output end of the threshold judgment module and the output end of the XOR gate are connected to the reset control end of the counter through the OR gate.

2. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: The low-pass filter is used as a pre-filter of the OSP detection circuit to filter out burrs less than 2.4x0.92% MHz.

3. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: The low-pass filter output signal is loaded into the enabling circuit, the rising edge of the signal is used as the clock of the first DFF flip-flop in the enabling circuit, and the falling edge of the signal is used as the clock of the second DFF flip-flop in the enabling circuit.

4. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: The OSP detection circuit is used to detect the OSP signal. Any change of the OSP signal can be used as the enablement of the gated clock. When the gated clock is enabled, the gated clock is turned on.

5. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: When the timeout flag of the timeout detection circuit arrives, the first DFF flip-flop and the second DFF flip-flop are cleared.

6. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: The gate control circuit also includes: a latch and an OR gate; The OR gate directly replaces the AND gate, and the connection mode of the OR gate in the gate control circuit is the same as that of the AND gate.

7. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: The output of the third DFF trigger changes as the output of the low-pass filter changes, and the signal edge of the change in the output of the third DFF trigger causes the XOR gate to generate a pulse to clear the counter.

8. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: When the gated clock arrives, the counter of the timeout detection circuit starts counting.

9. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: When the time for which the level of the detection port of the external reception detection device remains unchanged is less than or equal to the fixed threshold value set by the timeout threshold setting terminal, the counter continues to count.

10. The low power consumption detection circuit based on the OSP protocol according to claim 1, characterized in that: When the level of the detection port of the external reception detection device remains unchanged for a time greater than the fixed threshold set by the timeout threshold setting terminal, the threshold judgment module outputs a timeout pulse to clear the enabling circuit and clears the count of the counter at the same time.

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