Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises a first surface and a second surface which are opposite to each other, and the substrate is provided with a preformed first hole area; the method includes laser the preformed first hole region from the first surface to form a first laser trajectory and laser the preformed first hole region from the first surface to form a second laser trajectory. The first laser track and the second laser track are not overlapped. The method further includes etching the preformed first hole region to form a first hole.

Description

Technical Field

[0001] The embodiments of the present invention relate to an electronic device and a manufacturing method thereof, and more particularly to an electronic device including holes of various shapes (such as rectangular or polygonal) and a manufacturing method thereof. Background Art

[0002] In the manufacture of multi-layer circuit structures, circular conductive holes are often made to electrically connect two conductive layers. However, in some special applications, holes with special shapes (such as rectangles or polygons) may be made. Therefore, the manufacturing method for forming holes with special shapes (such as rectangles or polygons) needs to be further improved. Summary of the invention

[0003] The present invention provides a method for manufacturing an electronic device, comprising providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, and the substrate having a pre-formed first hole area. The method comprises performing laser etching on the pre-formed first hole area from the first surface to form a first laser track and performing laser etching on the pre-formed first hole area from the first surface to form a second laser track. The first laser track and the second laser track do not overlap. The method further comprises etching the pre-formed first hole area to form a first hole.

[0004] The present invention provides an electronic device, comprising a substrate having a first hole and a second hole, an electronic component disposed in the first hole, a connection structure disposed in the second hole, and a first conductive layer disposed on a first surface of the substrate. The electronic component is electrically connected to the connection structure via the first conductive layer, the shape of the top view contour of the first hole is different from the shape of the top view contour of the second hole, and the top view contour of the first hole includes a plurality of straight edges, and two adjacent straight edges of the plurality of straight edges are connected via an arc edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. It should also be noted that the accompanying drawings only illustrate typical embodiments of the present invention and should not be considered to limit the scope thereof. The present invention is also applicable to other embodiments.

[0006] Figures 1A to 1R FIG. 2 is a cross-sectional view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present invention.

[0007] Figure 2A FIG. 4 is a top view showing a laser track pattern for preforming a first hole region according to some embodiments of the present invention. Figure 2A-1 yes Figure 2AA partial enlarged view of the gap in the image. FIG. 2B to FIG. 2D 1 is a top view showing a laser track pattern for preforming a first hole region according to some other embodiments of the present invention.

[0008] Figure 3 FIG. 4 is a top view showing a laser track for preforming a second hole region according to some other embodiments of the present invention.

[0009] Figure 4A FIG. 1 is a top view of an electronic device at an intermediate manufacturing stage according to some embodiments of the present invention.

[0010] Figure 4B FIG. 1 is a top view of a first hole according to some embodiments of the present invention. Figure 4B-1 yes Figure 4B A partially enlarged top view of the first hole in the.

[0011] Figure 4C FIG. 4 is a top view showing a second hole according to some embodiments of the present invention.

[0012] Figure 5 According to some embodiments of the present invention, Figure 1C A partially enlarged cross-sectional view of a second hole of an electronic device in FIG.

[0013] Figure 6 According to some embodiments of the present invention, Figure 1R A partially enlarged cross-sectional view of the connection structure of the electronic device in FIG.

[0014] Reference numerals:

[0015] 100: Electronic devices

[0016] 102: Substrate

[0017] 102S1: First surface

[0018] 102S2: Second surface

[0019] 104: First Hole

[0020] 1041: Straight Edge

[0021] 1042: Arc edge

[0022] 104A: Pre-forming the first hole area

[0023] 106: Second Hole

[0024] 106A: Pre-formation of the second hole area

[0025] 108: Laser

[0026] 109: Etching process

[0027] 110: Attachment

[0028] 112: Electronic components

[0029] 114: Guide pad layer

[0030] 116: Filling layer

[0031] 118: Filling layer

[0032] 120 / 126: Seed layer

[0033] 122 / 128: Conductive structure

[0034] 124 / 132 / 136: Protective layer

[0035] 130: Insulation layer

[0036] 134 / 138: Rewiring structure

[0037] 135: First conductive layer

[0038] 139: Second conductive layer

[0039] 140: Insulation layer

[0040] 142: Electronic components

[0041] 143: Groove

[0042] 144: Encapsulation layer

[0043] 145: Filling layer

[0044] 146: Welded structure

[0045] 148: Connection structure

[0046] 148S1: Side 1

[0047] 148S2: Side 2

[0048] 150: Groove

[0049] 200 / 220 / 240 / 260 / 300: Laser track pattern

[0050] 202: First laser track

[0051] 2021: Part 1

[0052] 2022: Part 2

[0053] 204 / 204' / 204": Second laser track

[0054] 2041 / 2041': Partial

[0055] 206 / 206': Third laser track

[0056] 208: Laser Tracks

[0057] A / B / C: Virtual Line

[0058] CP: Bonding pad

[0059] d / d1 / d2 / d3 / D1 / D2 / H1 / H2: distance

[0060] D: Depth

[0061] L1 / L2 / W / W1 / Wt / Wm / Wb: Width

[0062] M / N: Area

[0063] OP: Notch

[0064] T: Thickness

[0065] T1: Protruding thickness

[0066] VP / VP': Virtual Point

[0067] LA / LB / LC / LD: Diameter

[0068] θ1 / θ2: Angle DETAILED DESCRIPTION

[0069] The following description lists various embodiments of the present invention to introduce the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the scope of the patent application. The following will refer to exemplary embodiments of the present invention in detail, and examples of exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and description to represent the same or similar parts.

[0070] The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention. In the drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0071] A structure (or layer, component, substrate) described in the present disclosure is located on / above another structure (or layer, component, substrate), which may refer to the two structures being adjacent and directly connected, or may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate gap) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present invention, when a certain structure is disposed "on" other structures, it may refer to that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0072] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not intended to limit the scope of the present invention.

[0073] Certain words are used throughout the specification and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names.

[0074] In the following description and claims, the words “including” and “comprising” are open-ended words, and thus should be interpreted as meaning “including but not limited to…”.

[0075] In addition, relative terms, such as "below" or "bottom" and "above" or "top", may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It is understood that if the device in the drawings is turned upside down, the component described on the "below" side will become the component on the "above" side.

[0076] In some embodiments of the present invention, terms such as "connection" and "interconnection" may refer to two structures being in direct contact, or two structures not being in direct (indirect) contact, with other structures being disposed between the two structures, unless otherwise specifically defined. Such terms may also include situations where both structures are movable, or where both structures are fixed. In addition, the term "electrically connected" includes energy transfer between two structures by means of direct or indirect electrical connection, or energy transfer between two separate structures by means of mutual induction.

[0077] It should be understood that when a component or film layer is referred to as being "on" or "connected to" another component or film layer, it may be directly on or directly connected to the other component or film layer, or there may be an intervening component or film layer between the two (indirect case). Conversely, when a component is referred to as being "directly on" or "directly connected to" another component or film layer, there may be no intervening component or film layer between the two. It should be understood that when a component or film layer is referred to as being "connected to" another component or film layer, it may be directly electrically connected to the other component or film layer, or it may be electrically connected to the other component or film layer via other conductive components.

[0078] The terms "approximately," "equal," "equal," or "same," "substantially," or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0079] Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular or "approximately" perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel or "approximately" parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0080] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify components. They do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claims.

[0081] In the present invention, the phrases “a given range is from a first value to a second value” and “a given range falls within the range from a first value to a second value” mean that the given range includes the first value, the second value and other values ​​therebetween.

[0082] It should be understood that according to embodiments of the present invention, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer or other suitable methods may be used to measure the depth, thickness, width, height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the components to be measured, and measure the depth, thickness, width, height of each component, or the spacing or distance between components.

[0083] The electronic device of the present invention may include electronic components. The electronic components may include passive components, active components or a combination thereof, such as connectors, capacitors, resistors, inductors, varactor diodes, variable capacitors, filters, diodes, transistors, sensors, micro-electro-mechanical-system (MEMS) components, liquid crystal chips, etc., but are not limited thereto. The diode may include a light-emitting diode or a non-light-emitting diode. The diode may include a PN junction diode, a PIN diode or a constant current diode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, a quantum dot light-emitting diode (quantum dot LED), a fluorescence diode, a phosphor diode, other suitable materials or a combination thereof, but are not limited thereto. The sensor includes, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but is not limited thereto. The electronic component may include a chip (die) or a light emitting diode chip (LED die), and the chip may be made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), sapphire or a glass substrate, but is not limited thereto. In another embodiment, the chip may include a semiconductor package component, such as a ball grid array (BGA) package component, a chip size package (CSP) component, a flip chip or a 2.5D / 3D semiconductor package component, but is not limited thereto.In another embodiment, the chip can be any flip chip bonding component, such as an integrated circuit (IC), transistors, thyristor rectifiers, valves, thin film transistors, capacitors, inductors, variable capacitors, filters, resistors, diodes, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but not limited to them. The chip may include, for example, a diode or a semiconductor chip (semiconductor die), but not limited to them. The chip may be a known good die (KGD), which may include various components, such as (but not limited to) wires, transistors, circuit boards, etc. Adjacent chips may have different functions from each other, such as an integrated circuit (IC), a radio frequency integrated circuit (RFIC), and a dynamic random access memory (DRAM), but not limited to them.

[0084] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used to represent the same or similar parts in the drawings and descriptions. Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used to represent the same or similar parts in the drawings and descriptions. The electronic device may include an artificial intelligence (AI) server device, a data center server device, an edge computing device, an Internet of Things device, a satellite communication device, a car device, a battery management device, an imaging device, a bonding device, a display device, a backlight device, an antenna device, a splicing device, a touch display, a curved display, or a non-rectangular electronic device (free shape display), but is not limited thereto. The electronic device may, for example, include a liquid crystal, a light emitting diode, fluorescence, phosphorescence, other suitable display media, or a combination of the foregoing, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. The electronic device described in the present invention may be applied to a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. It should be noted that the following embodiments may replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention. The features between the embodiments may be mixed and matched as desired as long as they do not violate the spirit of the invention or conflict with each other.

[0085] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the background or context of the relevant art and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in an embodiment of the present invention. One aspect of the present invention is to provide an electronic device including a novel circuit structure.

[0086] In some special requirements or applications (such as glass connectors or other applications, etc.), it may be necessary to form holes with special shapes (such as rectangular or polygonal shapes) in the substrate. However, the current process for forming holes with non-special shapes needs to be improved.

[0087] The present invention provides an electronic device including a hole of a special shape (e.g., a rectangle or a polygon) and a method for manufacturing the same. According to an embodiment of the present invention, a hole of a special shape (e.g., a rectangle, a polygon, etc.) can be produced in a substrate by using the laser track pattern design method of the present invention in a laser process. Through the size design of the laser track pattern, the contour shape of the hole formed subsequently at the corner can be more symmetrical. Furthermore, through the shape design of the laser track pattern, the etching time required in the subsequent etching process can be reduced or a relatively vertical hole sidewall can be obtained.

[0088] Figures 1A to 1R 1 is a cross-sectional view of an electronic device 100 at an intermediate manufacturing stage according to some embodiments of the present invention. It should be understood that for the sake of clarity, some components of the electronic device 100 may be omitted from the drawings and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 100 described below.

[0089] refer to Figure 1A In one embodiment, a substrate 102 is provided, and the substrate 102 includes a first surface 102S1 and a second surface 102S2 opposite to each other. In some embodiments, the substrate 102 includes a hard substrate, a soft substrate, or a combination thereof. For example, the material of the substrate 102 may include glass, quartz, sapphire, acrylic resin, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), a combination thereof, or other suitable substrate materials, but is not limited thereto.

[0090] refer to Figure 1B In one embodiment, the substrate 102 has a pre-formed first hole region 104A and / or a pre-formed second hole region 106A. The "hole" referred to in the present invention may include a through hole and a blind hole, but is not limited thereto. A through hole is a hole that passes through the substrate, and a blind hole is a hole that does not pass through the substrate. The following will be described by taking the example that the first hole 104 is a blind hole and the second hole 106 is a through hole, but is not limited thereto.

[0091] In some embodiments, the laser 108 is applied at least twice to the pre-formed first hole region 104A from the first surface 102S1 of the substrate 102. In some embodiments, the laser 108 is applied from the first surface 102S1 of the substrate 102 to modify the pre-formed first hole region 104A so that the pre-formed first hole region 104A is easily removed by etching.

[0092] Also refer to Figure 1B as well as FIG. 2A to FIG. 2D , Figure 2A FIG. 1 is a top view of a laser track pattern 200 for pre-forming a first hole region 104A according to some embodiments of the present invention. Figure 2A-1 yes Figure 2A A partial enlarged view of the gap OP in FIG.

[0093] In one embodiment, a laser 108 (eg, Figure 1B In addition, the pre-formed first hole region 104A is lasered from the first surface 102S1 and then lasered 108 to form a second laser track 204, thereby forming a laser track pattern 200 (as shown in FIG. 1 ) including the first laser track 202 and the second laser track 204. Figure 2A ). The pre-formed first hole area 104A is etched to form a first hole 104, but is not limited thereto. In one embodiment, the first laser track 202 may be formed first and then the second laser track 204 may be formed. In other embodiments, the second laser track 204 may be formed first and then the first laser track 202 may be formed. In one embodiment, in the direction of looking down at the substrate (i.e., in the third direction Z), the first laser track 202 and the second laser track 204 do not overlap. "Laser track" refers to the track of the center point of the laser. For simplicity, only the track of the center point of the laser is shown in the drawings of the present invention.

[0094] like Figure 2A As shown, in one embodiment, the first laser track 202 surrounds the second laser track 204. In one embodiment, the first laser track 202 includes a plurality of straight line portions (e.g., a first portion 2021 and a second portion 2022), and two adjacent ones of the plurality of straight line portions (e.g., the first portion 2021 and the second portion 2022) are not parallel and are separated by a gap OP. The adjacent two ones of the plurality of straight line portions are respectively the first portion 2021 and the second portion 2022 that are substantially perpendicular to each other, and the gap OP may be located between the first portion 2021 and the second portion 2022. It should be noted that although Figure 2AThe first laser track 202 is shown to include four straight line portions and their extension lines intersect to form a rectangle, but the present invention is not limited thereto. In other embodiments (not shown), the number and relative positions of the straight line portions may be adjusted as required, for example, the first laser track 202 may include five unconnected straight line portions and their extension lines intersect to form a pentagon, or may include six unconnected straight line portions and their extension lines intersect to form a hexagon.

[0095] Continue to see Figure 2A In one embodiment, the second laser track 204 includes a plurality of portions 2041. It should be noted that although Figure 2A The second laser track 204 is shown to include four parts 2041, and these parts 2041 (such as L-shaped, but not limited to this) are connected to each other to present a rectangular shape, but not limited to this. In other embodiments, the contour shape of the second laser track 204 can be formed in accordance with the contour shape of the first laser track 202, but not limited to this.

[0096] In some embodiments, the laser track pattern 200 further includes a third laser track 206, and the second laser track 204 may surround the third laser track 206. Figure 2A The third laser track 206 is shown as a plurality of dot-shaped portions, which are arranged in an array, for example, but not limited thereto. In other embodiments, different patterns of the third laser track 206 can be formed according to requirements. In other embodiments, the third laser track 206 can also be selectively omitted.

[0097] The following will refer to Figure 2B and Figure 2D Other embodiments of the present invention are described. FIG. 2B to FIG. 2D FIG. 2 is a top view of laser track patterns 220, 240, and 260 pre-forming the first hole region 104A according to some embodiments of the present invention. It should be noted that the features of various embodiments can be mixed and matched as long as they do not violate the spirit of the present invention or conflict with each other. In some embodiments, Figure 2B Laser track pattern 220 is similar to Figure 2A The laser track pattern 200 in FIG. 2 is different in that the second laser track 204' of the laser track pattern 220 has mutually unconnected portions 2041' (e.g., L-shaped portions) at the four corners corresponding to the first laser track 202, that is, there is a gap between adjacent portions 2041'. In some embodiments, Figure 2C Laser track pattern 240 is similar to Figure 2A The laser track pattern 200 in FIG. 1 is different in that the third laser track 206' presents a plurality of sequentially surrounding rings (eg, a plurality of sequentially surrounding rectangles, but not limited thereto). In some embodiments, Figure 2D Laser track pattern 240 is similar to Figure 2AThe laser track pattern 200 in the embodiment of the present invention is different in that the second laser track 204" is spiral-shaped, and the third laser track 206 may be selectively omitted. In some embodiments, since the laser track pattern 240 and / or the laser track pattern 260 have laser tracks with higher density, the laser track pattern 204" may be spiral-shaped, and the third laser track 206 may be omitted. Figure 1C The etching process 109 in the embodiment may have a higher etching efficiency (eg, a shorter etching time) or may obtain a more vertical hole sidewall, but is not limited thereto.

[0098] Also refer to Figure 2A As shown in FIG. 2A-1, in some embodiments, the range of the first laser track 202 has a maximum width L1 in the first direction X, and a maximum width L2 in the second direction Y. In one embodiment, two adjacent straight line portions are respectively a first portion 2021 and a second portion 2022 that are substantially perpendicular to each other, the notch OP is located between the first portion 2021 and the second portion 2022, and the extension line of the first portion 2021 and the extension line of the second portion 2022 in the straight line portion of the first laser track 202 intersect at a virtual point VP, the virtual point VP is at a first shortest distance d1 from the first portion 2021, and the virtual point VP is at a second shortest distance d2 from the second portion 2022. In some embodiments, at least one of the first shortest distance d1 and the second shortest distance d2 is greater than 0. For example, the first shortest distance d1 and the second shortest distance d2 are greater than 0 (d1>0; d2>0), the first shortest distance d1 is greater than 0 (d1>0) and the second shortest distance d2 is equal to 0 (d2=0), or the first shortest distance d1 is equal to 0 (d1=0) and the second shortest distance d2 is greater than 0 (d2>0). In some embodiments, the first shortest distance d1 and the second shortest distance d2 are between the following relationship:

[0099] and and But not limited to this. Or

[0100] and and But not limited to this,

[0101] When the first shortest distance d1 and the second shortest distance d2 meet the above conditions, the corner of the first hole 104 may be closer to a right angle or the contour shape may be more symmetrical.

[0102] In one embodiment, the second laser track 204 includes a plurality of portions 2041, one of the plurality of portions 2041 is adjacent to the notch OP. In one embodiment, the shortest distance d3 between the virtual point VP and the one of the portions 2041, and the first shortest distance d1, the second shortest distance d2, and the shortest distance d3 are between the following relationships:

[0103] or

[0104]

[0105] When the shortest distance d3 meets the above conditions, the corner of the first hole 104 formed subsequently can be closer to a right angle.

[0106] Return to reference Figure 1B And also refer to Figure 3 , Figure 3 FIG. 1 is a top view of a laser track pattern 300 for pre-forming the second hole region 106A according to some other embodiments of the present invention. In one embodiment, a laser 108 is applied from the first surface 102S1 of the substrate 102 to pre-form the second hole region 106A. Figure 1B In the embodiment of forming a through hole, when the substrate 102 is thicker, in addition to performing laser 108 on the pre-formed second hole region 106A from the first surface 102S1, laser 108 can also be performed on the pre-formed second hole region 106A from the second surface 102S2 (ie, double-sided laser modification), but is not limited thereto.

[0107] like Figure 3 As shown, the laser track pattern 300 in the second hole 106 may include a plurality of ring-shaped laser tracks 208 or spiral laser tracks (not shown) surrounding each other, but is not limited thereto. In this way, in the subsequent etching process (e.g. Figure 1C The etching process 109 in the embodiment may have a higher etching efficiency (eg, a shorter etching time) or may obtain a more vertical hole sidewall, but is not limited thereto.

[0108] Next, return to the reference Figure 1C In one embodiment, a laser and etching process 109 is performed on the pre-formed first hole region 104A and the pre-formed second hole region 106A to form the first hole 104 and the second hole 106, respectively. In some embodiments, the etching process 109 performed on the pre-formed first hole region 104A and the pre-formed second hole region 106A can be performed simultaneously, but is not limited thereto. In other embodiments, the etching process 109 of the pre-formed first hole region 104A and the pre-formed second hole region 106A can be performed separately. In some embodiments, the etching process 109 can be an (isotropic) etching process, such as a wet etching process and using an etchant (such as a hydrofluoric acid (HF) solution, other suitable etchants, or a combination thereof) to remove the region of the substrate 102 modified by the laser 108 (such as the pre-formed first hole region 104A and the pre-formed second hole region 106A), but is not limited thereto.

[0109] Also refer to Figure 1C as well as FIG. 4A to FIG. 4C 。 Figure 4A FIG. 4B-1 is a top view showing the electronic device 100 at an intermediate manufacturing stage, in which a first hole 104 and a second hole 106 that are approximately rectangular (the outer shape can be approximately circular, elliptical, but not limited thereto) are illustrated, but not limited thereto. Figure 1C is a cross-sectional view taken along the 1C-1C' line in Figure 4A . Figure 4B FIG. 4B-2 is a top view showing the first hole 104 according to some embodiments of the present invention. FIG. 4B-1 is Figure 4B a partially enlarged top view of the first hole 104 in Figure 4C FIG. 4B-1.

[0110] Referring to Figure 4A FIG. 4B-1, in one embodiment, the substrate 102 has a first hole 104 and a second hole 106, and the shape of the top view contour of the first hole 104 is different from the shape of the top view contour of the second hole 106. For example, the top view contour of the first hole 104 can be approximately rectangular, and the top view contour of the second hole 106 can be approximately circular, but not limited thereto. In other embodiments, according to the design requirements, the shape of the top view contour of the first hole 104 can be rectangular, polygonal or other suitable shapes, and the shape of the top view contour of the second hole 106 can be circular, elliptical, rectangular, polygonal or other suitable shapes.

[0111] Referring to Figure 4B FIG. 4B-2, in some embodiments, the top view contour of the first hole 104 includes a plurality of non-parallel straight edges 1041, and adjacent ones of these straight edges are connected, for example, via an arc edge 1042, but not limited thereto. In some embodiments, as Figure 4B-1 shown in

[0112] 0 < d / w ≤ 0.1 (for example, 0 < d / w ≤ 0.06),

[0113] wherein when the shortest distance d is small, the corner of the first hole 104 can be closer to a right angle.

[0114] As Figure 4CAs shown, the top view contour of the second hole 106 is approximately circular. At this time, the ratio between any two of the first diameter LA, the second diameter LB, the third diameter LC, and the fourth diameter LD is greater than 92% (for example, greater than 95%). In some embodiments, the top view contour dimensions (including area, length, and width) of the first hole 104 are different from those of the second hole 106 (including area, length, and width), but are not limited thereto.

[0115] Return to reference Figure 1C And refer to Figure 5 at the same time. Figure 5 is a partial enlarged sectional view of the second hole 106 of the electronic device 100 shown in some embodiments of the present invention. Figure 1C in.

[0116] As Figure 5 shown, in one embodiment, on the cross-section of the electronic device 100, the substrate 102 has a thickness T, and the side surface of the second hole 106 is an arc surface with a curvature radius a, but is not limited thereto. The thickness T of the substrate 102 can be obtained by taking the average value of the thicknesses at any three places corresponding to the non-hole part. In other embodiments (not shown), the second hole 106 may have a vertical side surface substantially perpendicular to the first surface 102S1 of the substrate 102. In some embodiments, the degree of concavity of the side surface of the second hole 106 is related to the thickness T of the substrate 102 and / or the process parameters of the etching process 109. When the process parameters of the etching process 109 are fixed, the thickness T and the curvature radius a satisfy the following relationship:

[0117] T / 2 < a ≤ 10T, or T < a ≤ 8T.

[0118] In some embodiments, there are included an included angle θ1 and an included angle θ2 between the first surface 102S1 of the substrate 102 and the side surface 102SS at the corresponding second hole 106 of the substrate 102 and between the second surface 102S2 of the substrate 102 and the side surface 102SS at the corresponding second hole 106 of the substrate 102, respectively, and the included angle θ1 and / or the included angle θ2 is greater than or equal to 90° (θ1 > 90° and / or θ2 > 90°). In some embodiments, a virtual line C can be defined at approximately half of the thickness T of the substrate 102, the virtual line C is substantially parallel to the first surface 102S1 of the substrate 102, and the side surface 102SS at the corresponding second hole 106 of the substrate 102 intersects the virtual line C at a point. A virtual line A can be defined between this point and the top end of the side surface 102SS (i.e., the point where the second hole 106 corresponds to the first surface 102S1), and the included angle θ1 is defined as the angle between the first surface 102S1 of the substrate 102 and the virtual line A. Similarly, the side surface 102SS at the corresponding two holes 106 of the substrate 102 intersects the virtual line C at a point. A virtual line B can be defined between this point and the bottom end of the side surface 102SS (i.e., the point where the second hole 106 corresponds to the second surface 102S2), and the included angle θ2 is defined as the angle between the second surface 102S2 of the substrate 102 and the virtual line B.

[0119] In some embodiments, such as Figure 5 , in the first direction X, the second hole 106 has a width Wt located on the first surface 102S1, a width Wb located on the second surface 102S2, and a width Wm located between the first surface 102S1 and the second surface 102S2. In some embodiments, the cross-section of the second hole 106 is substantially conical. For example, the width Wt is greater than the width Wm, and the width Wm is greater than the width Wb (Wt > Wm > Wb, but not limited thereto), but not limited thereto. In some embodiments, the cross-section of the second hole 106 is substantially conical, the width Wt is less than the width Wm, and the width Wm is less than the width Wb (Wt < Wm < Wb, but not limited thereto). In some embodiments, the side surface of the second hole 106 is a concave arc surface (i.e., substantially narrower at the middle of the corresponding hole), both the width Wt and the width Wb are greater than the width Wm (Wt > Wm and Wb > Wm), and the width Wt and the width Wb satisfy the following relationship:

[0120] 0.8 ≤ Wb / Wt ≤ 1.2, or 0.85 ≤ Wb / Wt ≤ 1.15,

[0121] Through the above design, the holes are relatively symmetric, or it is possible to reduce the influence on the connection of the conductive layers disposed on the first surface 102S1 and the second surface 102S2 of the substrate 102 due to too small a width on one side.

[0122] Return to reference Figure 1DIn one embodiment, the electronic component 112 is disposed in the first hole 104. In some embodiments, the electronic device 100 further includes an attachment 110 disposed under the electronic component 112 and a filling layer 116 disposed in the first hole 104 and covering the electronic component 112, but is not limited thereto.

[0123] In some embodiments, the electronic component 112 may include various types of passive components and active components, such as connectors, capacitors, resistors, inductors, varactor diodes, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but not limited thereto. The diode may include a light-emitting diode or a non-light-emitting diode. The diode includes a PN junction diode, a PIN diode, or a constant current diode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, a quantum dot light-emitting diode, a fluorescence diode, a phosphor diode, or other suitable materials or combinations thereof, but not limited thereto. The sensor may, for example, include a capacitive sensor, an optical sensor, an electromagnetic sensor, a fingerprint sensor (FPS), etc., but not limited thereto. The electronic component 112 may include a chip (die) or a light emitting diode chip (LED die), which may be made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), sapphire (Sapphire) or a glass substrate, but is not limited thereto.

[0124] In some embodiments, the electronic component 112 can be disposed or fixed in the first hole 104 through the attachment 110. The attachment 110 may include double-sided tape, curing glue or other suitable attachments, but is not limited thereto. In some embodiments, the electronic component 112 includes a pad 114, and the electronic component 112 is electrically connected to the pad 114. The material of the pad 114 may include nickel (Ni), copper (Cu), nickel alloy, copper alloy, other suitable materials or a combination thereof, but is not limited thereto.

[0125] In some embodiments, the filling layer 116 may fill at least a portion of the first hole 104. The filling layer 116 is used to protect the electronic component 112 and / or the conductive pad layer 114 to improve the reliability of the electronic device 100, but is not limited thereto. The filling layer 116 may include liquid epoxy, deformable gel, silicone rubber, or similar materials, but is not limited thereto. In some embodiments, the formation of the filling layer 116 includes disposing a filling material layer in the first hole 104 and covering the electronic component 112 and / or the conductive pad layer 114, and then selectively performing grinding to remove excess filling material layer and expose a portion of the conductive pad layer 114, thereby forming the filling layer 116, but is not limited thereto.

[0126] In one embodiment, after performing the planarization process, a connection structure 148 is formed or disposed in the second hole 106, such as Figure 1E to Figure 1M shown.

[0127] refer to Figure 1E In some embodiments, the filling layer 118 is filled into the second hole 106 and covers at least a portion of the first surface 102S1 and / or the second surface 102S2 of the substrate 102, but is not limited thereto. The material of the filling layer 118 may include epoxy resin, polyimide, other suitable resin materials, or a combination thereof, but is not limited thereto.

[0128] refer to Figure 1F to Figure 1G In some embodiments, a portion of the filling layer 118 is removed to expose the first surface 102S1 of the substrate 102 and / or a portion of the sidewall of the second hole 106, such as Figure 1F In some embodiments, after removing a portion of the filling layer 118 to expose the first surface 102S1 of the substrate 102 and / or a portion of the sidewall of the second hole 106, a first seed layer 120 is formed (deposited) from the first surface 102S1 of the substrate 102, as shown in FIG. Figure 1F The first seed layer 120 may be disposed on and / or in contact with the first surface 102S1 of the substrate 102, the guide pad layer 114, the filling layer 118 and / or a portion of the sidewall of the second hole 106. Figure 1GAs shown, in some embodiments, a first conductive structure 122 is formed (deposited) on the first surface 102S1 conductive structure of the substrate 102. In some embodiments, the material of the first seed layer 120 and the first conductive structure 122 may include gold (Au), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), ruthenium (Ru), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), manganese (Mn), zinc (Zn), alloys thereof, or combinations thereof, but not limited thereto. In some embodiments, the first seed layer 120 may be deposited using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD), an atomic layer deposition (ALD) process, other suitable methods, or combinations thereof, but not limited thereto. In some embodiments, the first conductive structure 122 may be deposited using an electroplating process, other suitable methods, or combinations thereof, but not limited thereto.

[0129] refer to Figure 1H In some embodiments, after forming the first protective layer 124 on the first surface 102S1 of the substrate 102, for example, the substrate 102 is turned upside down (that is, the second surface 102S2 faces upward). The first protective layer 124 can be used as a temporary protective film (TPF). In some embodiments, the first protective layer 124 can be used, for example, in the subsequent manufacturing process of the electronic device 100 (see the following Figure 1M ) is removed, but is not limited to this. In some embodiments, the first protective layer 124 may include a single layer of material or a composite material. When the first protective layer 124 is a composite material, it may include a film layer, an adhesive layer and / or a combination of other suitable materials, but is not limited to this. The above-mentioned film layer, for example, includes polyethylene terephthalate (PET), film polyimide (PI), other suitable materials and / or the above-mentioned combinations, but is not limited to this. The above-mentioned adhesive material, for example, includes pressure-sensitive adhesive, acrylic adhesive, epoxy resin (Epoxy), silicone (Silicone), other suitable materials and / or the above-mentioned combinations, but is not limited to this.

[0130] Next, in some embodiments, as Figure 1H, the filling layer 118 on the other side is removed to expose the second surface 102S2 of the substrate 102, another portion of the sidewall of the second hole 106, and / or a portion of the first seed layer 120 (e.g., a portion of the first seed layer 120 filled in the second hole 106). In some embodiments, the first seed layer 120 exposed in the second hole 106 is removed by an etching process, but is not limited thereto.

[0131] refer to Figures 1I to 1J In some embodiments, a second seed layer 126 is formed (deposited) from the second surface 102S2 of the substrate 102, such as Fig. 1I The second seed layer 126 may be disposed on the second surface 102S2 of the substrate 102, the first conductive structure 122, and / or another portion of the sidewall of the second hole 106. Next, in some embodiments, a second conductive structure 128 is deposited (or disposed) from the second surface 102S2 of the substrate 102, such as Figure 1J In some embodiments, the materials and formation methods of the second seed layer 126 and the second conductive structure 128 can refer to Figure 1F to Figure 1G For the sake of brevity, the first seed layer 120 and the first conductive structure 122 are not described in detail herein.

[0132] refer to Figure 1K In some embodiments, the second seed layer 126 and / or a portion of the second conductive structure 128 on the second surface 102S2 of the substrate 102 are removed to expose the second surface 102S2. A polishing method (such as chemical mechanical polishing (CMP), but not limited thereto) may be used to remove the second seed layer 126 and / or a portion of the second conductive structure 128 disposed on the second surface 102S2, but not limited thereto.

[0133] refer to Figure 1LIn some embodiments, a first insulating layer 130 is formed on the second surface 102S2 of the substrate 102 and covers the second conductive structure 128. In some embodiments, the material of the first insulating layer 130 may include an inorganic insulating material, an organic insulating material, a combination of the foregoing, or any suitable insulating material, but is not limited thereto. According to some embodiments, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or a combination of the foregoing, but is not limited thereto. According to some embodiments, the organic material may include epoxy resins, silicone resins, acrylic resins (e.g., polymethyl methacrylate (PMMA)), benzocyclobutene (BCB), polyimide, copolyester, polydimethylsiloxane (PDMS), perfluoroalkoxy alkane (PFA), other suitable materials, or a combination of the foregoing, but is not limited thereto.

[0134] refer to Figure 1M In some embodiments, after forming the second protective layer 132 on the second surface 102S2 of the substrate 102, the substrate 102 is turned upside down (i.e., the first surface 102S1 is facing upward). The second protective layer 132 can be used as a temporary protective film (TPF). In some embodiments, the second protective layer 132 can be used, for example, in the subsequent manufacturing process of the electronic device 100 (see the following Fig.1O ) is removed, but is not limited thereto. The material of the second protective layer 132 can refer to Figure 1H The first protective layer 124 is not described in detail here. In some embodiments, grinding is performed to remove the first protective layer 124, the first seed layer 120 and / or the first conductive structure 122 on the first surface 102S1 to expose the first surface 102S1 and / or the conductive pad layer 114. In some embodiments, the first conductive structure 122 and the second conductive structure 128 can be connected to each other to form a connection structure 148.

[0135] refer to Figure 1NIn some embodiments, a first rewiring structure 134 is disposed or formed on the first surface 102S1 of the substrate 102. The first rewiring structure 134 includes a structure in which multiple circuit layers are stacked in sequence on the first surface 102S1. In some embodiments, the first rewiring structure 134 may include multiple layers of alternately stacked insulating layers, first conductive layers 135, and conductive vias connecting adjacent first conductive layers 135 to each other, but is not limited thereto. In one embodiment, a first conductive layer 135 is formed on the first surface 102S1 of the substrate 102, and the first conductive layer 135 is electrically connected to the electronic component 112. In one embodiment, the electronic component 112 may be electrically connected to the connection structure 148 via the first conductive layer 135. In some embodiments, the material of the first conductive layer 135 may include a metal or alloy material, such as copper, but is not limited thereto. The material of the insulating layer in the above-mentioned first rewiring structure 134 may include an elastic polymer. In some embodiments, the insulating layer in the first redistribution structure 134 may include photosensitive polyimide (PSPI), polyethylene (PE), polyethylene terephthalate (PET), polycarbonate (PC), polytetrafluoroethylene (PTFE), polystyrene (PS), acrylonitrile butadiene styrene (ABS), other suitable materials, or any combination thereof, but not limited thereto.

[0136] refer to Fig.1O In some examples, after the third protection layer 136 is disposed or formed on the first redistribution structure 134 of the first surface 102S1 of the substrate 102, the substrate 102 is turned upside down (i.e., the second surface 102S2 faces upward). The third protection layer 136 can be used as a temporary protection film. In some embodiments, the third protection layer 136 can be used, for example, in the subsequent manufacturing process of the electronic device 100 (see the following Figure 1P ) is removed, but is not limited thereto. The material of the third protective layer 136 can refer to Figure 1H The first protection layer 124 described above will not be described in detail here.

[0137] In some embodiments, a second redistribution structure 138 is disposed or formed on the second surface 102S2 of the substrate 102. The second redistribution structure 138 includes a structure in which multiple wiring layers are sequentially stacked on the second surface 102S2. In some embodiments, the second redistribution structure 138 may include multiple alternately stacked insulating layers, second conductive layers 139, and conductive vias connecting adjacent second conductive layers 139 to each other, but is not limited thereto. In other words, the second conductive layer 139 is formed on the second surface 102S2 of the substrate 102. In one embodiment, the electronic component 112 is electrically connected to the second conductive layer 139 via the first conductive layer 135 and the connecting structure 148. In some embodiments, the material of the second conductive layer 139 may include metal or alloy, such as copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), tantalum (Ta) other suitable metal materials or any combination thereof, but is not limited thereto. The connecting structure 14 may include a seed layer, a metal, or any combination thereof. In some embodiments, examples of metals may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), tantalum (Ta), other suitable metal materials, or any combination of the foregoing, but are not limited thereto.

[0138] refer to Figure 1PIn some embodiments, after the substrate 102 is turned upside down (i.e., the first surface 102S1 is facing upward), the third protective layer 136 on the first surface 102S1 of the substrate 102 is removed. In some embodiments, an insulating layer 140 may be respectively disposed on the first redistribution structure 134 and / or the second redistribution structure 138, and the insulating layer 140 may be used to protect the first redistribution structure 134 and / or the second redistribution structure 138 from moisture. A portion of the first conductive layer 135 and a portion of the second conductive layer 139 are, for example, not covered by the insulating layer 140 and are exposed. In some embodiments, the material of the insulating layer 140 may include a moisture-proof insulating material, such as a photoresist, a solder resist, aluminum nitride (AlNx), silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. In some embodiments, the electronic component 142 is bonded to the first redistribution structure 134 so that the electronic component 142 is electrically connected to the electronic component 112 via the first conductive layer 135. Specifically, the electronic component 142 can be electrically connected to the first conductive layer 135 via the bonding pad CP. In the third direction Z (top view direction), the electronic component 142 can overlap the first hole 104 and at least one second hole 106. In the first direction X, the width of the electronic component 142 is greater than the width of the electronic component 112. In some embodiments, the electronic component 142 and the electronic component 112 are, for example, different types of electronic components. The electronic component 142 may include passive components, active components, or a combination of the above, such as connectors, capacitors, resistors, inductors, varactor diodes, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, etc., but are not limited thereto. The diode may include a light-emitting diode or a non-light-emitting diode. The diode includes a PN junction diode, a PIN diode, or a constant current diode. The electronic component 142 may include a chip (die) or a light emitting diode chip (LED die), and the chip may be made of silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), sapphire (Sapphire) or a glass substrate, but is not limited thereto. In another embodiment, the chip may include a semiconductor package component, such as a ball grid array (BGA) package component, a chip size package (CSP) component, a flip chip or a 2.5D / 3D semiconductor package component, but is not limited thereto.In another embodiment, the chip can be any flip-chip bonding component, such as an integrated circuit, a transistor, a thyristor rectifier, a valve, a capacitor, an inductor, a variable capacitor, a filter, a resistor, a diode, a micro-electromechanical system component (MEMS), a liquid crystal chip, etc., but not limited thereto.

[0139] refer to Figure 1Q In some embodiments, a half-cutting process is performed to form a groove 143 at the edge of the electronic device 100. In some embodiments, the half-cutting process may include a laser cutting process or a cutter wheel cutting process, but is not limited thereto. The substrate 102 may be prevented from being cut by the half-cutting process by adjusting the laser intensity in the laser cutting process or the cutting depth in the cutter wheel cutting process.

[0140] In some embodiments, a filling layer 145 and / or an encapsulation layer 144 are formed above the electronic device 100, and the encapsulation layer 144 may surround at least a portion of the side surface of the electronic component 142, but is not limited thereto. In some embodiments, the encapsulation layer 144 may serve as a structural support or may reduce the impact of water and oxygen in the environment on the electronic component 142, but is not limited thereto. In some embodiments, the encapsulation layer 144 may be formed in the groove 143. In some embodiments, the encapsulation layer 144 may include an insulating material, and the insulating material may include an organic insulating material, and the organic insulating material may include epoxy, epoxy molding compound (EMC), Ajinomoto Build-up Film (ABF), polyimide (PI) or other suitable organic insulating materials, but is not limited thereto. In some embodiments, the encapsulation layer 144 may be formed on the electronic device 100 by a thermal compression molding process, a thermal injection molding process, a vacuum lamination process, a deposition process, or other suitable processes, but is not limited thereto.

[0141] refer to Figure 1RIn some embodiments, a welding structure 146 is formed on the exposed second conductive layer 139 and is in electrical contact with the second conductive layer 139. In some embodiments, a driving component (not shown) may be disposed on the side of the welding structure 146 away from the substrate 102. In some embodiments, the driving component may be, for example, an integrated circuit, a flexible printed circuit (FPC), a printed circuit board (PCB), a chip on board (COB), or a chip on film (COF), but is not limited thereto. The material of the welding structure 146 may include, but is not limited to, solder and flux. In some embodiments, Figure 1Q The composite stacked structure is cut (eg, laser cut) or singulated into individual electronic devices 100 .

[0142] like Figure 1R As shown, in one embodiment, the electronic device 100 includes a substrate 102 having a first hole 104 and a second hole 106, an electronic component 112 disposed in the first hole 104, a connection structure 148 disposed in the second hole 106, and a first conductive layer 135 disposed on a first surface 102S1 of the substrate 102. In one embodiment, the electronic component 112 is electrically connected to the connection structure 148 via the first conductive layer 135. In one embodiment, the electronic device 100 further includes a second conductive layer 139 disposed on a second surface 102S2 (opposite to the first surface 102S1) of the substrate 102, an electronic component 142 disposed on a side of the first conductive layer 135 away from the substrate 102 and electrically connected to the first conductive layer 135, and a soldering structure 146 disposed on a side of the second conductive layer 139 away from the substrate 102 and electrically connected to the second conductive layer 139.

[0143] In some embodiments, in a cross section, in a first direction X, the edge of the first redistribution structure 134 is separated from the edge of the substrate 102 by a first distance D1 (minimum distance), and the edge of the second redistribution structure 138 is separated from the edge of the substrate 102 by a second distance D2 (minimum distance). The first distance D1 may be equal to or unequal to the second distance D2. The warping degree of the electronic device 100 is adjusted by designing the first distance D1 and the second distance D2. In some embodiments, the first distance D1 may be greater than the second distance D2, but is not limited thereto. In some embodiments, in some embodiments, Figure 1QThe groove 143 in the substrate 102 is formed into a groove 150 after singulation. Because the encapsulation layer 144 is disposed in the groove 150, damage caused by external impact on the edge of the substrate 102 can be reduced. In some embodiments, in a cross section, along the third direction Z, the groove 150 may have a depth D (maximum depth), the substrate 102 has a thickness T (the average thickness measured at a location without holes as described above), and the ratio of the depth D to the thickness T is less than 1 and greater than or equal to 0.1 (0.1≤D / T<1), for example, less than 1 and greater than or equal to 0.2 (0.2≤D / T<1) or less than 1 and greater than or equal to 0.5 (0.5≤D / T<1).

[0144] Figure 6 According to some embodiments of the present invention, Figure 1R FIG. 1 is an enlarged cross-sectional view of a local area N of the connection structure 148 of the electronic device 100. Figure 6 As shown, in one embodiment, the connection structure 148 has a first surface 148S1 adjacent to the first surface 102S1 and a second surface 148S2 adjacent to the second surface 102S2. In one embodiment, the first surface 148S1 is a plane, and the second surface 148S2 is a curved surface (eg, a convex curved surface), but is not limited thereto.

[0145] In some embodiments, Figure 6 , the first surface 148S1 of the connection structure 148 and the first surface 102S1 of the substrate 102 may be substantially flush, but not limited thereto, and therefore, the first redistribution structure 134 located between the electronic component 142 and the first surface 148S1 of the connection structure 148 may be designed, for example, with a thinner line width and / or a higher alignment accuracy, but not limited thereto. In some embodiments, the second surface 148S2 of the connection structure 148 may protrude from the second surface 102S2, and the impedance between the driving component (not shown, the driving component is electrically connected, for example, through the welding structure 146) and the second surface 148S2 of the connection structure 148 may be appropriately reduced, but not limited thereto. Figure 6 As shown, in some embodiments, on the cross-section of the electronic device 100, the second surface 148S2 has a protruding thickness T1 (in the third direction Z) relative to the second surface 102S2, and the second surface has a width W1 (in the first direction X), and the protruding thickness T1 and the width W1 meet the following relationship:

[0146] 0.05≤T1 / W1≤0.3, or 0.1≤T1 / W1≤0.25

[0147] When the protrusion thickness T1 satisfies the above conditions, the impedance can be appropriately reduced.

[0148] In some embodiments, in the cross section of the electronic device 100, in the third direction Z, the first surface 148S1 of the connection structure 148 is separated from the first conductive layer 135 by a third distance H1 (maximum distance). In some embodiments, in the cross section of the electronic device 100, in the third direction Z, the second surface 148S2 of the connection structure 148 is separated from the second conductive layer 139 by a fourth distance H2 (maximum distance). In some embodiments, the third distance H1 is greater than the fourth distance H2 (H1>H2), and the ratio of the third distance H1 to the fourth distance H2 may be greater than or equal to 1.3 and less than or equal to 3, but is not limited thereto. In some embodiments, the ratio of the third distance H1 to the fourth distance H2 may be greater than or equal to 1.5 and less than or equal to 2.5, but is not limited thereto.

[0149] In summary, the present invention provides an electronic device and a method for manufacturing the same. According to an embodiment of the present invention, by using the laser track pattern design method of the present invention in a laser process, holes of special shapes (e.g., rectangular, polygonal, etc.) can be produced in a substrate. In addition, through the design of the laser track pattern size, the contour shape of the hole can be more symmetrical, or the contour shape of the hole can be closer to a right angle at the corner. Furthermore, through the design of the laser track pattern shape (e.g., multiple laser tracks sequentially surround or spiral each other), a higher etching efficiency (reduced etching time) or a more vertical hole sidewall can be obtained in the subsequent etching process. One side surface of the connection structure of some embodiments of the present invention has a protruding surface, which can appropriately reduce impedance, or one side surface of the connection structure of some embodiments has a flat surface, which is conducive to the subsequent formation of a redistribution structure having a thinner line width and / or a higher alignment accuracy design.

[0150] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A method for manufacturing an electronic device, characterized in that: include: Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, and the substrate having a pre-formed first hole area; Laser the pre-formed first hole region from the first surface to form a first laser track; Laser treatment is performed on the pre-formed first hole region from the first surface to form a second laser track, wherein the first laser track and the second laser track do not overlap; and The pre-formed first hole region is etched to form a first hole.

2. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: Disposing an electronic component in the first hole; as well as A first conductive layer is formed on the first surface of the substrate, wherein the first conductive layer is electrically connected to the electronic component.

3. The method for manufacturing an electronic device according to claim 2, wherein: Also includes: Laser and etch a pre-formed second hole region from the first surface of the substrate to form a second hole; forming a connecting structure in the second hole; and A second conductive layer is formed on the second surface of the substrate, wherein the electronic component is electrically connected to the second conductive layer via the first conductive layer and the connecting structure.

4. The method for manufacturing an electronic device according to claim 1, wherein: The first laser track surrounds the second laser track, the first laser track includes a plurality of straight line sections, two adjacent straight line sections are not parallel and are separated by a gap, and the second laser track includes a plurality of sections, one of which is adjacent to the gap.

5. The method for manufacturing an electronic device according to claim 4, wherein: The two adjacent ones of the plurality of straight line portions are respectively a first portion and a second portion perpendicular to each other, the notch is located between the first portion and the second portion, an extension line of the first portion and an extension line of the second portion intersect a virtual point, the virtual point is separated from the first portion by a first shortest distance (d1), the virtual point is separated from the second portion by a second shortest distance (d2), at least one of the first shortest distance (d1) and the second shortest distance (d2) is greater than 0, and the shortest distance (d3) between the virtual point and the one of the plurality of portions is between the following relationship:

6. An electronic device, characterized in that: include: A substrate having a first hole and a second hole; An electronic component disposed in the first hole; a connecting structure disposed in the second hole; and A first conductive layer is disposed on a first surface of the substrate, wherein the electronic component is electrically connected to the connection structure via the first conductive layer, a top-view contour of the first hole has a shape different from a top-view contour of the second hole, and the top-view contour of the first hole includes a plurality of straight edges, and two adjacent straight edges are connected via an arc edge.

7. The electronic device according to claim 6, characterized in that The extension lines of two adjacent straight edges of the top-view contour of the first hole intersect a virtual point, and the virtual point is separated from the arc edge by a shortest distance (d). The first hole has a maximum width (w), and the shortest distance (d) and the maximum width (w) meet the following relationship: 0 <d / w≤0.1。 8. The electronic device according to claim 6, characterized in that In a cross section of the electronic device, the substrate has a thickness (T), and a side surface of the second hole is a curved surface with a radius of curvature (a). The thickness (T) and the radius of curvature (a) satisfy the following relationship: T / 2 <a≤10T。 9. The electronic device according to claim 6, wherein: Also includes: a second conductive layer disposed on a second surface of the substrate, the second surface being opposite to the first surface; another electronic component, disposed on a side of the first conductive layer away from the substrate and electrically connected to the first conductive layer; and A welding structure is arranged on a side of the second conductive layer away from the substrate and electrically connected to the second conductive layer, wherein the connection structure has a first surface adjacent to the first surface and a second surface adjacent to the second surface, the first surface is a plane, and the second surface is an arc surface.

10. The electronic device according to claim 9, characterized in that In a cross section of the electronic device, the second surface has a protruding thickness (T1) relative to the second surface, and the second surface has a width (W1). The protruding thickness (T1) and the width (W1) satisfy the following relationship: 0.05≤T1 / W1≤0.3.

Images