Semiconductor memory device

Abstract

The embodiment relates to a semiconductor memory device. A semiconductor memory device according to one embodiment includes: a plurality of first semiconductor layers stacked in a stacking direction; a first via wiring electrically connected to the plurality of first semiconductor layers; a plurality of memory sections electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes facing the plurality of first semiconductor layers; a plurality of first wirings electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers electrically connected to the plurality of first gate electrodes via a plurality of first wirings; a second via wiring electrically connected to the plurality of second semiconductor layers; and a plurality of second gate electrodes facing the plurality of second semiconductor layers. The plurality of second semiconductor layers include a material different from that of the plurality of first semiconductor layers, or the composition ratio of the material included in the plurality of second semiconductor layers is different from the composition ratio of the material included in the plurality of first semiconductor layers.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2023-134511 (filing date: August 22, 2023). The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor memory device. Background Art

[0003] As semiconductor memory devices become more highly integrated, research into making semiconductor memory devices three-dimensional is underway. Summary of the invention

[0004] A semiconductor storage device involved in one embodiment comprises: a substrate; a plurality of first semiconductor layers stacked in a stacking direction intersecting the surface of the substrate; a first via wiring extending in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of storage parts stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes stacked in the stacking direction and opposite to the plurality of first semiconductor layers; a plurality of first wirings stacked in the stacking direction and extending in a first direction intersecting the stacking direction and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers stacked in the stacking direction and electrically connected to the plurality of first gate electrodes via the plurality of first wirings; a second via wiring extending in the stacking direction and electrically connected to the plurality of second semiconductor layers; and a plurality of second gate electrodes stacked in the stacking direction and opposite to the plurality of second semiconductor layers. The plurality of second semiconductor layers include a material different from that of the plurality of first semiconductor layers, or a composition ratio of a material included in the plurality of second semiconductor layers is different from a composition ratio of a material included in the plurality of first semiconductor layers.

[0005] One embodiment provides a semiconductor memory device that operates well. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a schematic circuit diagram showing the structure of the semiconductor memory device according to the first embodiment.

[0007] Figure 2 This is a schematic circuit diagram for explaining the read operation of the semiconductor memory device.

[0008] Figure 3 2 is a schematic graph showing the magnitude relationship between voltages supplied to the word line WL and the layer selection line LL in the read operation.

[0009] Figure 4 This is a schematic perspective view showing a partial structure of the semiconductor memory device according to the first embodiment.

[0010] Figure 5 : is a schematic XY cross-sectional view showing the structure of a part of the memory layer ML.

[0011] Figure 6 : is a schematic XY cross-sectional view showing the structure of a part of the memory layer ML.

[0012] Figure 7 Shows the Figure 6 The structure shown is a cross section cut along line AA′ and observed in the direction of the arrow.

[0013] Figure 8 : is a schematic XY cross-sectional view showing the structure of a part of the memory layer ML.

[0014] Fig. 9 Shows the Figure 8 The structure shown is a cross section cut along line BB′ and observed in the direction of the arrow.

[0015] Fig.10 It is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment.

[0016] Fig.11 It is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor memory device.

[0017] Fig.12 It is a schematic cross-sectional view for explaining the manufacturing method.

[0018] Fig.13 It is a schematic cross-sectional view for explaining the manufacturing method.

[0019] Fig.14 It is a schematic cross-sectional view for explaining the manufacturing method.

[0020] Fig.15 It is a schematic cross-sectional view for explaining the manufacturing method.

[0021] Fig.16 It is a schematic cross-sectional view for explaining the manufacturing method.

[0022] Fig.17 It is a schematic cross-sectional view for explaining the manufacturing method.

[0023] Fig.18 It is a schematic cross-sectional view for explaining the manufacturing method.

[0024] Fig.19 It is a schematic cross-sectional view for explaining the manufacturing method.

[0025] Fig. 20 It is a schematic cross-sectional view for explaining the manufacturing method.

[0026] Fig.21 It is a schematic cross-sectional view for explaining the manufacturing method.

[0027] Fig. 22 It is a schematic cross-sectional view for explaining the manufacturing method.

[0028] Fig.23 It is a schematic cross-sectional view for explaining the manufacturing method.

[0029] Fig.24 It is a schematic cross-sectional view for explaining the manufacturing method.

[0030] Fig.25 It is a schematic cross-sectional view for explaining the manufacturing method.

[0031] Fig.26 It is a schematic cross-sectional view for explaining the manufacturing method.

[0032] Fig. 27 It is a schematic cross-sectional view for explaining the manufacturing method.

[0033] Fig.28 It is a schematic cross-sectional view for explaining the manufacturing method.

[0034] Fig.29 It is a schematic cross-sectional view for explaining the manufacturing method.

[0035] Fig.30 It is a schematic cross-sectional view for explaining the manufacturing method.

[0036] Fig.31 It is a schematic cross-sectional view for explaining the manufacturing method.

[0037] Fig.32 It is a schematic cross-sectional view for explaining the manufacturing method.

[0038] Fig.33 It is a schematic cross-sectional view for explaining the manufacturing method.

[0039] Fig.34 It is a schematic cross-sectional view for explaining the manufacturing method.

[0040] Fig.35 It is a schematic cross-sectional view for explaining the manufacturing method.

[0041] Fig.36 It is a schematic cross-sectional view for explaining the manufacturing method.

[0042] Fig.37 It is a schematic cross-sectional view for explaining the manufacturing method.

[0043] Fig.38 It is a schematic cross-sectional view for explaining the manufacturing method.

[0044] Fig.39 It is a schematic cross-sectional view for explaining the manufacturing method.

[0045] Fig.40 It is a schematic cross-sectional view for explaining the manufacturing method.

[0046] Fig.41 It is a schematic cross-sectional view for explaining the manufacturing method.

[0047] Fig.42 It is a schematic cross-sectional view for explaining the manufacturing method.

[0048] Fig.43 It is a schematic cross-sectional view for explaining the manufacturing method.

[0049] Fig.44 It is a schematic cross-sectional view for explaining the manufacturing method.

[0050] Fig.45 It is a schematic cross-sectional view for explaining the manufacturing method.

[0051] Fig.46 It is a schematic cross-sectional view for explaining the manufacturing method.

[0052] Fig.47 It is a schematic cross-sectional view for explaining the manufacturing method.

[0053] Fig.48 It is a schematic cross-sectional view for explaining the manufacturing method.

[0054] Fig.49 It is a schematic cross-sectional view for explaining the manufacturing method.

[0055] Fig.50 It is a schematic cross-sectional view for explaining the manufacturing method.

[0056] Fig.51 It is a schematic cross-sectional view for explaining the manufacturing method.

[0057] Fig.52 It is a schematic cross-sectional view for explaining the manufacturing method.

[0058] Fig.53 It is a schematic cross-sectional view for explaining the manufacturing method.

[0059] Fig.54 It is a schematic cross-sectional view for explaining the manufacturing method.

[0060] Fig.55 It is a schematic cross-sectional view for explaining the manufacturing method.

[0061] Fig.56 It is a schematic cross-sectional view for explaining the manufacturing method.

[0062] Fig.57 It is a schematic cross-sectional view for explaining the manufacturing method.

[0063] Fig.58 It is a schematic cross-sectional view for explaining the manufacturing method.

[0064] Fig.59 It is a schematic cross-sectional view for explaining the manufacturing method.

[0065] Fig.60 It is a schematic cross-sectional view for explaining the manufacturing method.

[0066] Fig.61 It is a schematic cross-sectional view for explaining the manufacturing method.

[0067] Fig.62 It is a schematic cross-sectional view for explaining the manufacturing method.

[0068] Fig.63 It is a schematic cross-sectional view for explaining the manufacturing method.

[0069] Fig.64 It is a schematic cross-sectional view for explaining the manufacturing method.

[0070] Fig.65 It is a schematic cross-sectional view for explaining the manufacturing method.

[0071] Fig.66 It is a schematic cross-sectional view for explaining the manufacturing method.

[0072] Fig.67 It is a schematic cross-sectional view for explaining the manufacturing method.

[0073] Fig.68 It is a schematic cross-sectional view for explaining the manufacturing method.

[0074] Fig.69 It is a schematic cross-sectional view for explaining the manufacturing method.

[0075] Fig.70 It is a schematic cross-sectional view for explaining the manufacturing method.

[0076] Fig.71 It is a schematic cross-sectional view for explaining the manufacturing method.

[0077] Fig.72 It is a schematic cross-sectional view for explaining the manufacturing method.

[0078] Fig.73 It is a schematic cross-sectional view for explaining the manufacturing method.

[0079] Fig.74 It is a schematic cross-sectional view for explaining the manufacturing method.

[0080] Fig.75 It is a schematic cross-sectional view for explaining the manufacturing method.

[0081] Fig.76 It is a schematic cross-sectional view for explaining the manufacturing method.

[0082] Fig.77 It is a schematic cross-sectional view for explaining the manufacturing method.

[0083] Fig.78 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to the second embodiment.

[0084] Fig.79 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0085] Fig.80 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0086] Fig.81 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0087] Fig.82 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0088] Fig.83 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0089] Fig.84 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0090] Fig.85 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0091] Fig.86 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0092] Fig.87 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the third embodiment.

[0093] Fig.88 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the third embodiment.

[0094] Fig.89 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0095] Fig.90 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0096] Fig.91 It is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the fifth embodiment.

[0097] Fig.92 It is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the fifth embodiment.

[0098] Fig.93 This is a schematic cross-sectional view showing a part of the structure of a semiconductor memory device according to the sixth embodiment.

[0099] Fig.94 This is a schematic circuit diagram showing a part of the structure of a semiconductor storage device according to the seventh embodiment.

[0100] Fig.95 It is a schematic perspective view showing a part of the structure of a semiconductor storage device according to the seventh embodiment.

[0101] Fig.96 It is a schematic XY cross-sectional view showing the structure of a part of the memory layer ML7.

[0102] Fig.97 Shows the Fig.96 The structure shown is a cross section cut along line AA′ and observed in the direction of the arrow.

[0103] Fig.98 Shows the Fig.96 The structure shown is a cross section cut along line BB′ and observed in the direction of the arrow.

[0104] Description of Reference Numerals

[0105] Sub…semiconductor substrate, ML…storage layer, BL…bit line, WL…word line, PL…plate line, TrC, TrL, TrB…transistor, CpC…capacitor, 102…conductive layer, 104…via wiring, 110, 160…transistor structure, 111, 161…semiconductor layer, 112, 162…insulating layer, 113, 163…conductive layer, 120…conductive layer, 130…capacitor structure, 171, 172…wiring. DETAILED DESCRIPTION

[0106] Next, the semiconductor memory device involved in the embodiment is described in detail with reference to the accompanying drawings. In addition, the following embodiment is only an example and is not intended to limit the present invention. In addition, the following drawings are schematic, and for the sake of convenience of description, a part of the structure is sometimes omitted. In addition, sometimes the same figure mark is marked on the parts common to multiple embodiments and the description is omitted.

[0107] In addition, when the term "semiconductor storage device" is used in this specification, it may mean a memory die, a memory chip, a memory card, an SSD (Solid State Drive) or other storage system including a control die. In addition, it may mean the configuration of a host computer such as a smartphone, a tablet terminal or a personal computer.

[0108] In addition, in this specification, when it is expressed that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the cut-off (OFF) state.

[0109] In addition, in this specification, when it is expressed that the first structure is "electrically connected to" the second structure and the third structure "between", it may mean that the first structure, the second structure and the third structure are connected in series and the second structure is electrically connected to the third structure via the first structure.

[0110] In addition, in this specification, when it is stated that a circuit or the like makes two wirings or the like "conduct", it may mean, for example, that the circuit or the like includes a transistor or the like, and the transistor or the like is provided in a current path between the two wirings and the transistor or the like is in a conducting (ON) state.

[0111] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0112] In addition, in this specification, the direction intersecting the surface of the substrate is sometimes referred to as the stacking direction. In addition, the direction along the predetermined surface intersecting the stacking direction is sometimes referred to as the first direction, and the direction along the surface and intersecting the first direction is sometimes referred to as the second direction. The stacking direction may or may not coincide with the Z direction. In addition, the first direction and the second direction may or may not correspond to any of the X direction and the Y direction.

[0113] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the above-mentioned Z direction is called upper, and the direction close to the substrate along the Z direction is called lower. In addition, when a certain structure is expressed as a lower surface or lower end, it means the surface or end of the substrate side of the structure, and when it is expressed as an upper surface or upper end, it means the surface or end of the structure on the opposite side of the substrate. In addition, the surface intersecting the X direction or the Y direction is called a side surface, etc.

[0114] In addition, in this specification, when expressing the "center position" of a certain structure, it may mean, for example, the position of the center of the circumscribed circle of the structure, or the center of gravity of the structure on the image.

[0115] [First embodiment]

[0116] [Circuit Configuration]

[0117] Figure 1 FIG. 1 is a schematic circuit diagram showing the structure of a semiconductor memory device according to the first embodiment. Figure 1 As shown, the semiconductor memory device according to the present embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers MLa to MLc (hereinafter sometimes referred to as "memory layers ML"), a transistor layer TL, a plurality of bit lines BL connected to the plurality of memory layers ML and the transistor layer TL, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL via the transistor layer TL, and plate lines PL connected to the plurality of memory layers ML.

[0118] Each storage layer ML includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of storage cells MC connected to the plurality of word lines WL0 to WL2. Each storage cell MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to the bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. In addition, one electrode and the other electrode of the transistor TrC function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to any one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to the plate line PL.

[0119] Furthermore, each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML.

[0120] In addition, each storage layer ML includes a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b (hereinafter sometimes referred to as "transistor TrL") provided corresponding to a plurality of word lines WL0 to WL2. One electrode of the transistor TrL is connected to any one of the word lines WL0 to WL2. The other electrode of the transistor TrL is connected to the word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, LW2b (hereinafter sometimes referred to as "word line selection line LW"), respectively. In addition, one electrode and the other electrode of the transistor TrL function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrL. The gate electrode of the transistor TrL is connected to the layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, LL2b (hereinafter sometimes referred to as "layer selection line LL"), respectively.

[0121] In addition, the word line selection line LW is connected to a plurality of transistors TrL corresponding to a plurality of storage layers ML. In addition, the layer selection lines LL0a, LL1a, and LL2a are respectively connected to all transistors TrL0a, TrL1a, and TrL2a corresponding to the plurality of storage layers ML. Similarly, the layer selection lines LL0b, LL1b, and LL2b are respectively connected to all transistors TrL0b, TrL1b, and TrL2b corresponding to the storage layers MLa to MLc.

[0122] The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 (hereinafter, sometimes referred to as "bit line selection lines LB") and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. One electrode of the transistor TrB is connected to the global bit line GBL. The other electrode of the transistor TrB is connected to the bit line BL. In addition, one electrode and the other electrode of the transistor TrB function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrB. The gate electrode of the transistor TrB is connected to any one of the bit line selection lines LB0 to LB2.

[0123] In addition, the transistor layer TL includes a plurality of transistors TrTa and TrTb (hereinafter sometimes referred to as "transistors TrT") provided corresponding to the plurality of bit line selection lines LB0 to LB2. One electrode of the transistor TrT is connected to any one of the bit line selection lines LB0 to LB2. The other electrode of the transistor TrT is connected to the word line selection line LW. In addition, one electrode and the other electrode of the transistor TrT function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrT. The gate electrode of the transistor TrT is connected to the wiring LTa and LTb (hereinafter sometimes referred to as "wiring LT"), respectively.

[0124] In addition, the wiring LTa is connected in common to all transistors TrTa. Similarly, the wiring LTb is connected in common to all transistors TrTb.

[0125] [Reading action]

[0126] Figure 2 This is a schematic circuit diagram for explaining a read operation of the semiconductor memory device according to the first embodiment.

[0127] In the read operation, one of the plurality of memory layers MLa to MLc is selected. In the example shown in the figure, the memory layer MLa is selected. When the memory layers MLa to MLc are selected, for example, a voltage V is supplied to the layer selection line LL0a corresponding to the memory layer MLa to be the target of the read operation among the plurality of layer selection lines LL0a, LL1a, and LL2a. ON ', supply voltage V to other layer selection lines LL1a and LL2a OFF '. For example, a voltage V is supplied to the layer selection line LL0b corresponding to the memory layer MLa to be the target of the read operation among the plurality of layer selection lines LL0b, LL1b, and LL2b. OFF ', supply voltage V to other layer selection lines LL1b and LL2b ON '. In addition, a voltage V is supplied to the wiring LTa. ON ', supply voltage V to wiring LTb OFF ′.

[0128] Voltage V ON ' has a magnitude sufficient to turn on the transistors TrL and TrT, for example. OFF ' has a magnitude such that the transistors TrL and TrT are turned off. For example, when the transistors TrL and TrT are NMOS transistors, the voltage V ON 'Ratio voltage V OFF ' is large. In addition, for example, when the transistors TrL and TrT are PMOS transistors, the voltage V ON 'Ratio voltage V OFF 'Small.

[0129] In addition, during the read operation, one of the plurality of word lines WL0 to WL2 is selected. In the example shown in the figure, word line WL0 is selected. When word lines WL0 to WL2 are selected, for example, a voltage V is supplied to a word line selection line LW0a corresponding to the word line WL0 to be read out of the plurality of word line selection lines LW0a, LW1a, and LW2a. ON , supply voltage V to other layer selection lines LW1a, LW2a OFF In addition, for example, a voltage V is supplied to a plurality of word line selection lines LW0b, LW1b, and LW2b. OFF .

[0130] Voltage V ON For example, the voltage V OFF For example, the voltage V is large enough to turn off the transistors TrC and TrB. For example, when the transistors TrC and TrB are NMOS transistors, the voltage V ON Ratio voltage V OFF In addition, for example, when transistors TrC and TrB are PMOS transistors, the voltage V ON Ratio voltage V OFF Small.

[0131] Here, a voltage V is supplied to a word line WL0 (hereinafter referred to as “selected word line WL0”) connected to a memory cell MC to be read (hereinafter referred to as “selected memory cell MC”) via a transistor TrL0a. ON As a result, the transistor TrC in the selected memory cell MC becomes conductive. In addition, the voltage V is supplied to the transistor TrB connected to the selected memory cell MC via the transistor TrTa. ONAs a result, the transistor TrB becomes conductive, and the capacitor CpC in the selected memory cell MC is conductive to the global bit line GBL. As a result, the voltage of the global bit line GBL changes, or a current flows through the global bit line GBL. By detecting the voltage change or current, the data stored in the selected memory cell MC can be read.

[0132] Furthermore, a voltage V is supplied to word lines WL1 and WL2 (hereinafter referred to as “non-selected word lines WL1 and WL2”, etc.) other than the selected word line WL0 corresponding to the same memory layer MLa as the selected memory cell MC via transistor TrL0a. OFF As a result, the transistor TrC in the memory cell MC is turned off. In addition, the voltage V is supplied to the transistor TrB connected to the memory cell MC via the transistor TrTa. OFF As a result, the transistor TrB enters the off state.

[0133] Furthermore, the voltage V is supplied to the unselected word lines WL0, WL1, and WL2 corresponding to the memory layers MLb and MLc different from the selected memory cell MC via the transistors TrL1b and TrL2b. OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0134] [Voltage supplied during read operation]

[0135] Figure 3 This is a schematic graph showing the magnitude relationship of the voltage supplied to the word line WL and the layer selection line LL in the read operation. The horizontal axis represents time and the vertical axis represents the magnitude of the voltage.

[0136] In the read operation, in the memory layer ML including the selected memory cell MC, a plurality of transistors TrL (in Figure 2 In the example, a plurality of transistors TrL0a) are set to an on state. Therefore, the gate-source voltage V GS1 、V GS2 Higher than the threshold voltage of transistor TrL.

[0137] The gate-source voltage V of the transistor TrL connected to the selected word line WL among the plurality of transistors TrL is GS1 The voltage V supplied to the layer selection line LL is lowered due to the voltage rise of the selected word line WL. ON ' minus the voltage V supplied to the word line selection line LW ON The resulting voltage.

[0138] The gate-source voltage V of the transistor TrL connected to the non-selected word line WL among the plurality of transistors TrL is GS2is the voltage V supplied to the layer selection line LL ON ' minus the voltage V supplied to the word line selection line LW OFF The resulting voltage.

[0139] In the read operation, in the memory layer ML including the selected memory cell MC, the plurality of transistors TrL (in Figure 2 In the example, a plurality of transistors TrL0b) are set to the off state. Therefore, the gate-source voltage V GS3 Lower than the threshold voltage of transistor TrL.

[0140] The gate-source voltage V of the transistor TrL connected to the non-selected word line WL among the plurality of transistors TrL is GS3 is the voltage V supplied to the layer selection line LL OFF ' minus the voltage V supplied to the word line selection line LW OFF The voltage obtained is Figure 3 The gate-source voltage V GS3 An example of a negative size.

[0141] [Threshold voltage of transistor TrL]

[0142] In the read operation, in order to quickly transfer the voltage V to the selected word line WL ON It is desired to set the gate-source voltage V GS1 Keeping the voltage V sufficiently higher than the threshold voltage of the transistor TrL, the current flowing through the transistor TrL is increased. ON ’ is set to a large value.

[0143] However, if the voltage V ON ′ is set to a large value, the gate-source voltage V GS2 The gate insulating film of the transistor TrL may be thickened. However, if the gate insulating film of the transistor TrL is thickened, the length of the storage layer ML in the Z direction may be increased, which may hinder the high integration of the semiconductor storage device.

[0144] Therefore, in this embodiment, the threshold voltage of the transistor TrL is set to a lower value (for example, a value lower than the threshold voltage of the transistor TrC). ON ' is set to a large value and transmits the voltage V to the selected word line WL at high speed without hindering the high integration of the semiconductor memory device ON .

[0145] In addition, it is also possible to consider setting not only the threshold voltage of transistor TrL but also the threshold voltage of transistor TrC to a lower value. However, if the threshold voltage of transistor TrC is low, leakage current may occur in transistor TrC, making it difficult to retain data. Therefore, it is preferred not to set the threshold voltage of transistor TrC to a lower value.

[0146] [structure]

[0147] Figure 4 1 is a schematic perspective view showing a part of the structure of the semiconductor storage device according to the present embodiment. Figure 4 , a portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub are shown.

[0148] The semiconductor substrate Sub is, for example, a semiconductor substrate of silicon (Si) or the like containing P-type impurities such as boron (B). An insulating layer and an electrode layer, not shown, are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer, not shown, and the electrode layer constitute a control circuit for controlling the semiconductor storage device involved in the first embodiment. For example, a sensing amplifier circuit is provided in an area directly below the memory cell array MCA. The sensing amplifier circuit is electrically connected to the bit line BL via the global bit line GBL. In a read operation, the sensing amplifier circuit can read the data stored in the selected memory cell MC by detecting the change in the voltage or current of the bit line BL.

[0149] The memory cell array MCA includes a plurality of memory layers ML stacked in the Z direction, a transistor layer TL provided between the memory layer ML and the semiconductor substrate Sub, a wiring layer M0 provided between the transistor layer TL and the semiconductor substrate Sub, and a wiring layer M1 provided between the wiring layer M0 and the semiconductor substrate Sub. In addition, silicon oxide (SiO 2 ) and the like insulating layer 103.

[0150] Figure 5 is a schematic XY cross-sectional view showing the structure of a portion of the storage layer ML. Figure 5 As shown, a memory cell region R is provided in the memory layer ML. MC and transistor area R TrL Although not shown in the figure, the transistor region R TrL The Y direction is arranged in the memory cell region R MC on both sides.

[0151] [Memory cell area R MC Structure of

[0152] Then, except Figure 4 and Figure 5 In addition, refer to Figure 6 , Figure 7 as well as Fig.10 , for the storage cell region R MC The structure of is described below. Figure 6 is a schematic XY cross-sectional view showing the structure of a portion of the memory layer ML, and shows an enlarged Figure 5 part of. Figure 7 Shows the Figure 6 The structure shown is a cross section cut along line AA′ and observed in the direction of the arrow. Fig.10 It is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment.

[0153] like Figure 5 As shown, in the storage unit area R MC A plurality of insulating layers 101 are arranged in the X direction, and a conductive layer 102 is provided between two insulating layers 101 adjacent to each other in the X direction. The insulating layer 101 and the conductive layer 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction (see Figure 4 ).

[0154] The insulating layer 101 contains, for example, silicon oxide (SiO 2 )wait.

[0155] The conductive layer 102 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). In addition, for example, it may also contain a conductive oxide. In addition, the conductive layer 102 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the conductive layer 102 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals. The conductive layer 102 may be used as a plate line PL ( Figure 1 ) to perform its function.

[0156] In this specification, the term "conductive oxide" refers to, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), or other conductive materials containing oxygen.

[0157] A plurality of via wirings 104 are provided in a region between the insulating layer 101 and the conductive layer 102. The plurality of via wirings 104 are arranged in the Y direction and are, for example, Figure 4 As shown, it extends in the Z direction through the plurality of storage layers ML.

[0158] like Figure 7As shown, the via wiring 104 includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b of titanium nitride (TiN) or the like, and a conductive member 104c of tungsten (W) or the like. In addition, the via wiring 104 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide film 104a. In addition, the via wiring 104 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0159] The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 104b.

[0160] The via wiring 104 is, for example, a bit line BL ( Figure 1 ) to function. For example, Figure 1 As shown, a plurality of bit lines BL are provided corresponding to a plurality of transistors TrC included in the memory layer ML.

[0161] The memory layer ML includes a plurality of transistor structures 110 provided corresponding to the plurality of via wirings 104 , a conductive layer 120 provided on the opposite side of the conductive layer 102 with respect to the plurality of transistor structures 110 , and a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102 .

[0162] For example, Figure 6 As shown, the transistor structure 110 includes: a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction, an insulating layer 112 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0163] exist Figure 6 In the XY cross section as illustrated, the side surface of the semiconductor layer 111 on one side in the X direction (on the conductive layer 102 side) may be formed along a circle centered at the center position of the via wiring 104. In addition, the side surfaces of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 on the other side in the X direction (on the conductive layer 120 side) may be formed in a straight line along the side surface of the conductive layer 120. In addition, both side surfaces of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the Y direction may be formed in a straight line along the side surface of the insulating layer 115.

[0164] The semiconductor layer 111 serves as a transistor TrC ( Figure 1 ) in the channel region. The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O), or other oxide semiconductors. The plurality of semiconductor layers 111 arranged in the Z direction are commonly connected to the via wiring 104 extending in the Z direction.

[0165] The insulating layer 112 serves as, for example, a transistor TrC ( Figure 1 ) functions as a gate insulating film. The insulating layer 112 contains, for example, silicon oxide (SiO 2 )wait.

[0166] The conductive layer 113 serves as a transistor TrC ( Figure 1 ) functions as a gate electrode. The conductive layer 113 contains, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). The plurality of conductive layers 113 arranged in the Y direction are connected to a conductive layer 120 extending in the Y direction (see Figure 5 The conductive layer 113 faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112 .

[0167] Silicon oxide (SiO 2 ) etc. The insulating layer 115 extends in the Z direction so as to penetrate the plurality of memory layers ML.

[0168] The conductive layer 120 is, for example, a word line WL ( Figure 1 The conductive layer 120 extends in the Y direction and is connected to the plurality of conductive layers 113 arranged in the Y direction. The conductive layer 120 includes, for example, a barrier conductive film 121 of titanium nitride (TiN) or the like and a conductive film 122 of tungsten (W).

[0169] For example, Figure 6 and Figure 7 As shown, the capacitor structure 130 includes: a conductive layer 131, an insulating layer 132 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the transistor structure 110 side) of the conductive layer 131, and a conductive layer 133 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the transistor structure 110 side) of the insulating layer 132.

[0170] The conductive layer 131 acts as a capacitor CpC ( Figure 1) functions as an electrode on one side. The conductive layer 131 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). In addition, for example, it may also include a conductive oxide. In addition, the conductive layer 131 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the conductive layer 131 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals. The conductive layer 131 is continuous with the conductive layer 102.

[0171] The insulating layer 132 serves as a capacitor CpC ( Figure 1 ) functions as an insulating layer. The insulating layer 132 may be, for example, zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ) or other insulating metal oxides. In addition, the insulating layer 132 may be, for example, a stacked film of a plurality of insulating metal oxides (for example, a stacked film of zirconium oxide and aluminum oxide).

[0172] The conductive layer 133 serves as a capacitor CpC ( Figure 1 ) functions as the other electrode. The conductive layer 133 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to the side surface of the semiconductor layer 111 in the X direction.

[0173] The transistor layer TL is constructed in the same manner as the memory layer ML. Fig.10 In the example, the length of the transistor layer TL in the Z direction is greater than the length of the memory layer ML in the Z direction. In addition, the length of the insulating layer 103 provided between the transistor layer TL and the memory layer ML adjacent to the transistor layer TL in the Z direction is greater than the length of the other insulating layers 103 in the Z direction. The semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the transistor layer TL function as the channel region, the gate insulating film, and the gate electrode of the transistor TrB, respectively. In addition, the conductive layer 120 in the transistor layer TL functions as the bit line selection line LB. In addition, the conductive layer 133 in the transistor layer TL functions as the source electrode or the drain electrode of the transistor TrB.

[0174] The lengths of the insulating layer 112 and the conductive layer 113 in the transistor layer TL in the Z direction are the same as the lengths of the insulating layer 112 and the conductive layer 113 in the memory layer ML in the Z direction. On the other hand, the length of the semiconductor layer 111 in the transistor layer TL in the Z direction is greater than the length of the semiconductor layer 111 in the memory layer ML in the Z direction. According to such a structure, it is possible to suppress the deterioration of the mobility of electrons in the semiconductor layer 111 in the transistor layer TL, increase the current in the on state of the transistor TrB, and transmit the voltage to the bit line BL and the global bit line GBL at a high speed. In addition, such a structure does not need to increase the length of the memory layer ML in the Z direction, and therefore can be implemented without hindering the high integration of the memory cell array MCA in the Z direction.

[0175] like Figure 4 As shown, the wiring layer M1 includes a plurality of global bit lines GBL extending in the Y direction and the X direction. The wiring layer M0 includes a plurality of wirings m0 provided corresponding to the plurality of conductive layers 133 and arranged in the Y direction.

[0176] The wiring m0 is connected to the conductive layer 133 in the transistor layer TL via a via contact electrode V0 extending in the Z direction. The via contact electrode V0 is provided at a position overlapping the conductive layer 133 and the wiring m0 when viewed from the Z direction, and has an upper end connected to the conductive layer 133 and a lower end connected to the wiring m0.

[0177] Furthermore, wiring m0 is electrically connected to global bit line GBL via via contact electrode V1 extending in the Z direction. Via contact electrode V1 is provided at a position overlapping global bit line GBL and wiring m0 when viewed in the Z direction, and has a lower end connected to global bit line GBL and an upper end connected to wiring m0.

[0178] [Transistor region R TrL Structure of

[0179] Then, except Figure 4 and Figure 5 In addition, refer to Figure 8 and Fig. 9 , for transistor area R TrL The structure of is described below.

[0180] Figure 8 is a schematic XY cross-sectional view showing the structure of a portion of the memory layer ML, and shows an enlarged Figure 5 part of.

[0181] Fig. 9 Shows the Figure 8 The structure shown is a cross section cut along line BB′ and observed in the direction of the arrow.

[0182] like Figure 5 As shown, in the transistor region R TrL A plurality of insulating layers 151 are arranged in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 152 is provided between two insulating layers 151 adjacent to each other in the X direction. The insulating layer 151 includes a portion extending in the Y direction and the Z direction and a portion extending in the X direction and the Z direction. The insulating layer 152 extends in the Y direction and the Z direction. The portions of the insulating layer 151 extending in the Y direction and the Z direction and the insulating layer 152 divide the plurality of memory layers ML in the X direction. The portions of the insulating layer 151 extending in the X direction and the Z direction divide the plurality of memory layers ML in the Y direction. The insulating layer 151 and the insulating layer 152 contain, for example, silicon oxide (SiO 2 )wait.

[0183] In addition, in the memory cell region R MC With transistor area R TrL An insulating layer 165 extending in the X direction is provided between two conductive layers 120 adjacent to each other in the X direction. The insulating layer 165 extends in the X direction and the Z direction to divide the plurality of memory layers ML in the Y direction. The insulating layer 165 contains, for example, silicon oxide (SiO 2 )wait.

[0184] In addition, the insulating layer 151 is divided in the Y direction via the insulating layer 153. The insulating layer 153 extends in the Z direction through the plurality of memory layers ML. The insulating layer 153 contains, for example, silicon oxide (SiO 2 )wait.

[0185] A plurality of via wirings 154 are provided in a region between the insulating layer 151 and the insulating layer 152. The plurality of via wirings 154 are arranged in the Y direction and are, for example, Fig. 9 As shown, it extends in the Z direction through the plurality of storage layers ML.

[0186] like Fig. 9 As shown, the via wiring 154 includes, for example, a conductive oxide film 154a containing a conductive oxide, a barrier conductive film 154b of titanium nitride (TiN) or the like, and a conductive member 154c of tungsten (W) or the like. In addition, the via wiring 154 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide film 154a. In addition, the via wiring 154 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0187] The conductive member 154c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 154b has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 154c. The conductive oxide film 154a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 154b.

[0188] The plurality of via wirings 154 arranged in the Y direction serve as, for example, one word line selection line LW ( Figure 1 ) to function. For example, Figure 1 As shown, a plurality of word line selection lines LW are provided corresponding to a plurality of word lines WL included in the memory layer ML.

[0189] The memory layer ML includes a plurality of transistor structures 160 provided corresponding to the plurality of conductive layers 120 , a wiring 171 provided between the transistor structure 160 and the insulating layer 151 , and a wiring 172 provided between the transistor structure 160 and the insulating layer 152 .

[0190] For example, Figure 8 As shown, the transistor structure 160 includes: a semiconductor layer 161 connected to the outer peripheral surface of multiple via wirings 154 and extending in the Y direction along the outer peripheral surface of the multiple via wirings 154, an insulating layer 162 arranged on the upper surface, lower surface, two side surfaces in the Y direction and one side in the X direction (the insulating layer 152 side) of the semiconductor layer 161, and a conductive layer 163 arranged on the upper surface, lower surface, two side surfaces in the Y direction and one side in the X direction (the insulating layer 152 side) of the insulating layer 162.

[0191] exist Figure 8 In the XY cross section as illustrated, the side surface of one side (insulating layer 151 side) of the semiconductor layer 161 in the X direction can be formed along a plurality of overlapping circles centered on a plurality of center positions of a plurality of via wirings 154. In addition, the side surface of the other side (insulating layer 152 side) of the semiconductor layer 161, the insulating layer 162, and the conductive layer 163 in the X direction can be formed in a straight line along the side surface of the wiring 172. In addition, the two side surfaces of the semiconductor layer 161, the insulating layer 162, and the conductive layer 163 in the Y direction can be formed along the reference Figure 5 The insulating layer 165 and the insulating layer 151 described above, the portions extending in the X direction and the Z direction are formed in a linear shape.

[0192] The semiconductor layer 161 serves as, for example, a transistor TrL ( Figure 1) in the channel region. The semiconductor layer 161 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. The plurality of semiconductor layers 161 arranged in the Z direction are commonly connected to the via wiring 154 extending in the Z direction.

[0193] Here, the concentration of indium in the semiconductor layer 161 is greater than the concentration of indium in the semiconductor layer 111. In addition, the concentration of gallium in the semiconductor layer 161 is less than the concentration of gallium in the semiconductor layer 111. Thus, the transistor TrL ( Figure 1 ) has a threshold voltage greater than that of transistor TrC ( Figure 1 ) has a low threshold voltage.

[0194] The insulating layer 162 serves as, for example, a transistor TrL ( Figure 1 ) functions as a gate insulating film. The insulating layer 162 contains, for example, silicon oxide (SiO 2 )wait.

[0195] The conductive layer 163 serves as, for example, a transistor TrL ( Figure 1 ) functions as a gate electrode. The conductive layer 163 contains, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). The side surface of the conductive layer 163 on one side in the X direction (on the insulating layer 152 side) is connected to the wiring 172. The conductive layer 163 is opposite to the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (on the insulating layer 152 side) of the semiconductor layer 161 via the insulating layer 162.

[0196] The wiring 171 is connected to the conductive layer 120 and the semiconductor layer 161, and has the function of connecting the word line WL ( Figure 1 ) and transistor TrL( Figure 1 ) has the function of connecting to the drain electrode of the wiring 171. The wiring 171 contains, for example, a conductive oxide. In addition, the wiring 171 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the wiring 171 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0197] The wiring 171 includes, for example, a portion formed on the lower surface of the insulating layer 103 via a portion of the insulating layer 162, a portion formed on the upper surface of the insulating layer 103 via a portion of the insulating layer 162, a portion formed on the side surface of the conductive layer 120 in the X direction, and a portion formed on the side surface of the semiconductor layer 161 in the X direction. In addition, a semiconductor layer 173 such as silicon (Si) may be provided in the region surrounded by the wiring 171.

[0198] like Figure 5As shown in FIG. 1 , the wiring 172 includes a portion extending in the Y direction and a portion extending in the X direction. The portion extending in the Y direction of the wiring 172 is connected to the conductive layer 163. The wiring 172 is used as a layer selection line LL ( Figure 1 ) to perform the function. Wiring 172 contains, for example, a conductive oxide. In addition, wiring 172 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, wiring 172 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0199] The wiring 172 includes, for example, a portion formed on the lower surface of the insulating layer 103, a portion formed on the upper surface of the insulating layer 103, and a portion formed on the side surface of the conductive layer 163 in the X direction. In addition, silicon oxide (SiO 2 ) and the like insulating layer 174.

[0200] The transistor layer TL is constructed in the same manner as the memory layer ML. However, the semiconductor layer 161, the insulating layer 162, and the conductive layer 163 in the transistor layer TL function as the channel region, the gate insulating film, and the gate electrode of the transistor TrT, respectively. In addition, the wiring 171 in the transistor layer TL functions as the bit line selection line LB. In addition, the wiring 172 in the transistor layer TL functions as the wiring LT.

[0201] [Manufacturing method]

[0202] Figure 11 to Figure 77 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0203] Fig.11 , Fig.14 , Fig.16 , Fig.18 , Fig.21 , Fig.23 , Fig.25 , Fig. 27 , Fig.29 , Fig.31 , Fig.33 , Fig.35 , Fig.37 , Fig.40 , Fig.41 , Fig.43 , Fig.45 , Fig.47 , Fig.49 , Fig.51 , Fig.53 , Fig.55 , Figures 57 to 60 , Fig.65 , Fig.67 , Fig.69 , Figure 71 to Figure 73 as well as Fig.76 Shown with Figure 7 The corresponding cross section.

[0204] Fig.12 , Fig.13 , Fig. 20 as well as Fig.39 Shown with Figure 5 The corresponding cross section.

[0205] Fig.15 , Fig.17 , Fig.19 , Fig. 22 , Fig.24 , Fig.26 , Fig.28 , Fig.30 , Fig.32 , Fig.34 , Fig.36 , Fig.38 , Fig.42 , Fig.44 , Fig.46 , Fig.48 , Fig.50 , Fig.52 , Fig.54 , Fig.56 , Figure 61-64 , Fig.66 , Fig.68 , Fig.70 , Fig.74 , Fig.75 as well as Fig.77 Shown with Fig. 9 The corresponding cross section.

[0206] In the manufacturing method, for example, Fig.11 As shown, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layers MLA contain, for example, silicon nitride (Si 3 N 4 ) etc. This step is performed by, for example, CVD (Chemical Vapor Deposition) or the like.

[0207] Then, for example, Fig.12 As shown, insulating layers 115, 151, and 165 are formed. In this process, for example, openings are formed at positions corresponding to the insulating layers 115, 151, and 165. The openings extend in the Z direction and penetrate through the plurality of insulating layers 103 and the plurality of sacrificial layers MLA stacked in the Z direction. This process is performed, for example, by RIE or the like. After the openings are formed, the insulating layers 115, 151, and 165 are formed. This process is performed, for example, by CVD or the like.

[0208] Then, for example, Figure 13 to Figure 15As shown in FIG. 1 , openings 104A and 154A are formed at positions corresponding to the via wirings 104 and 154. Figure 13 to Figure 15 As shown, the substrate extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA stacked in the Z direction. This step is performed by, for example, RIE or the like.

[0209] Then, for example, Fig.16 and Fig.17 As shown, the exposed surface of the sacrificial layer MLA exposed to the openings 104A and 154A is oxidized to form an oxide film MLB.

[0210] Then, for example, Fig.18 and Fig.19 As shown, sacrificial layers 104B and 154B made of silicon (Si) or the like are formed inside the openings 104A and 154A. This process is performed by, for example, CVD or the like.

[0211] Then, for example, Figure 20 to Figure 22 As shown, openings 101A and 152A are formed at positions corresponding to the insulating layers 101 and 152. The openings 101A and 152A extend in the Y direction and the Z direction and penetrate through the plurality of insulating layers 103 and the plurality of sacrificial layers MLA stacked in the Z direction, dividing these structures in the X direction. This process is performed, for example, by RIE or the like.

[0212] Then, for example, Fig.23 and Fig.24 As shown, openings 120A and 172A are formed at positions corresponding to the conductive layer 120 and the wiring 172. In the openings 120A and 172A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103 and a portion of the side surface of the sacrificial layer MLA in the X direction are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the openings 101A and 152A. This process is performed, for example, by wet etching or the like. In addition, the openings 120A and 172A are not connected to the openings 104A and 154A.

[0213] Then, for example, Fig.25 and Fig.26 As shown, a sacrificial layer 120B made of silicon (Si) or the like is buried in the openings 101A and 120A. Also, a sacrificial layer 172B made of silicon (Si) or the like is buried in the openings 152A and 172A. This process is performed by, for example, CVD or the like.

[0214] Then, for example, Fig. 27 and Fig.28 As shown, the sacrificial layers 104B and 154B are removed. This process is performed by, for example, wet etching.

[0215] Then, for example, Fig.29 and Fig.30 As shown, the oxide film MLB is removed. This step is performed by, for example, wet etching.

[0216] Then, for example, Fig.31 and Fig.32 As shown, openings 111A and 161A are formed at positions corresponding to the semiconductor layers 111 and 161. Inside the openings 111A and 161A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a portion of the side surface of the sacrificial layer MLA in the X direction, and a portion of the side surface of the insulating layers 115, 151, and 165 in the Y direction (see Fig. 20 ), and a part of the side surface of the sacrificial layers 120B and 172B in the X direction is exposed. In this process, for example, a part of the sacrificial layer MLA is selectively removed through the openings 104A and 154A. This process is performed by, for example, wet etching or the like.

[0217] Then, for example, Fig.33 and Fig.34 As shown, the exposed surfaces of the sacrificial layers MLA, 120B, and 172B exposed to the openings 104A and 154A are oxidized to form an oxide film MLB.

[0218] Then, for example, Fig.35 and Fig.36 As shown, conductive layers 113A and 163A are formed inside the openings 111A and 161A. In this process, for example, a conductive film of titanium nitride (TiN) or the like and a sacrificial layer of silicon (Si) or the like are formed inside the openings 104A and 111A and inside the openings 154A and 161A. This process is performed in a manner that the openings 111A and 161A are filled with the sacrificial layer, and the openings 104A and 154A are not filled with the sacrificial layer. Next, a portion of the sacrificial layer is removed inside the openings 104A and 154A to expose a portion of the conductive film (a portion formed on the side of the insulating layer 103). Next, a portion of the conductive film is removed and the conductive film is divided in the Z direction to form conductive layers 113A and 163A. Then, the sacrificial layer is removed.

[0219] Then, for example, Fig.37 and Fig.38 As shown, the openings 104A and 154A are filled with sacrificial layers 104B and 154B made of silicon (Si) or the like. This step is performed by, for example, CVD or the like.

[0220] Then, for example, Fig.39 and Fig.40As shown in FIG. 1 , an opening 102A is formed at a position corresponding to the conductive layer 102. The opening 102A extends in the Y direction and the Z direction and penetrates through the plurality of insulating layers 103 and the plurality of sacrificial layers MLA stacked in the Z direction, and the insulating layer 115, and divides these structures in the X direction. In addition, an opening 153A is formed at a position corresponding to the insulating layer 153. The opening 153A extends in the Z direction and penetrates through the plurality of insulating layers 103 and the plurality of sacrificial layers MLA stacked in the Z direction, and the insulating layer 151. This process is performed, for example, by RIE or the like.

[0221] Then, for example, Fig.41 As shown in FIG. 1 , an opening 131A is formed at a position corresponding to the capacitor structure 130. Fig.42 As shown, an opening 171A is formed at a position corresponding to the wiring 171. In this step, the sacrificial layer MLA is removed through the openings 102A and 153A. This step is performed by, for example, wet etching or the like.

[0222] Then, for example, Fig.43 and Fig.44 As shown in FIG. 1 , a portion of the oxide film MLB is removed through the openings 131A and 171A. This step is performed by, for example, wet etching or the like.

[0223] Then, for example, Fig.45 and Fig.46 As shown in FIG. 1 , conductive layers 113 and 163 are formed. In this step, a portion of conductive layer 113A is removed through opening 131A. In this step, a portion of conductive layer 163A is removed through opening 171A. This step is performed by, for example, wet etching or the like.

[0224] Then, for example, Fig.47 and Fig.48 As shown, the sacrificial layers 104B and 154B are removed. This process is performed by, for example, wet etching.

[0225] Then, for example, Fig.49 As shown in FIG. 1 , an insulating layer 112 is formed inside the openings 111A, 104A, 131A, and 102A. Fig.50 As shown, an insulating layer 162 is formed inside the openings 171A, 161A, and 154A. The insulating layers 112 and 162 are formed on the upper and lower surfaces of the conductive layers 113 and 163, a portion of the upper surface, a portion of the lower surface, and an exposed surface of the insulating layer 103 exposed to the openings 104A and 154A, a portion of the side surface of the sacrificial layer 120B in the X direction, and a portion of the side surface of the insulating layers 115 and 165 in the Y direction.

[0226] Then, for example, Fig.51As shown, silicon nitride (Si 3 N 4 ) etc. In addition, for example, Fig.52 As shown, silicon nitride (Si 3 N 4 ) or the like. The openings 111A and 161A are filled with the sacrificial layers 111B and 161B, and the openings 102A, 104A, 131A, 154A, and 171A are not filled with the sacrificial layers 111B and 161B. This process is performed, for example, by CVD or the like. In addition, although not shown in the figure, after the sacrificial layers 111B and 161B are formed, the upper portions of the openings 104A and 154A are closed by an insulating layer or the like.

[0227] Then, for example, Fig.53 and Fig.54 As shown, through openings 102A, 153A ( Fig.39 ), and a part of the sacrificial layers 111B and 161B is removed. This process is performed by, for example, wet etching.

[0228] Then, for example, Fig.55 As shown, a conductive layer 133A is formed on the side surface of the sacrificial layer 111B on one side in the X direction (the side surface on the opening 102A side), and the upper and lower surfaces of the insulating layer 112 and the side surface on one side in the X direction (the side surface on the opening 102A side), and the side surface in the Y direction. Fig.56 As shown, through opening 153A ( Fig.39 ) and the opening 171A, a conductive layer 171B is formed on the side surface of one side in the X direction of the sacrificial layer 161B (the side surface on the opening 171A side), the upper and lower surfaces of the insulating layer 162, the side surface on one side in the X direction (the side surface on the opening 171A side), and the side surface in the Y direction. This process is performed, for example, by ALD (Atomic Layer Deposition) or the like.

[0229] Then, for example, Fig.57 As shown, a sacrificial layer 131B of silicon (Si) or the like is formed inside the opening 102A. The opening 131A is filled with the sacrificial layer 131B, and the opening 102A is not filled with the sacrificial layer 131B. In addition, although not shown in the figure, a sacrificial layer of silicon (Si) or the like is formed inside the opening 171A. The opening 171A is filled with the sacrificial layer, and the opening 153A ( Fig.39 ) is not buried by a sacrificial layer. This process is performed, for example, by CVD.

[0230] In addition, for example, Fig.58 As shown, the conductive layer 133 is formed. In this process, for example, the portion of the sacrificial layer 131B provided on the side surface of the insulating layer 115 and the insulating layer 103 in the X direction is removed, so that a portion of the conductive layer 133A is exposed. In addition, the portion of the conductive layer 133A provided on the side surface of the insulating layer 115 and the insulating layer 103 in the X direction is removed, and the conductive layer 133A is divided in the Y direction and the Z direction. This process is performed, for example, by wet etching or the like. In addition, although not shown in the figure, in this process, the conductive layer 171B is divided in the Z direction, thereby forming the wiring 171. After the conductive layer 133 is formed, the opening 153A ( Fig.39 ) is closed at the top.

[0231] Then, for example, Fig.59 As shown, the sacrificial layer 131B is removed. This process is performed by, for example, wet etching or the like.

[0232] Then, for example, Fig.60 As shown, through the opening 131A and the opening 102A, the insulating layer 132 and the conductive layer 131 are formed on the upper surface, the lower surface, the side surface on one side in the X direction (the side surface on the opening 102A side), the two side surfaces in the Y direction, the insulating layer 115, and the side surface in the X direction of the insulating layer 103. This process is performed by, for example, CVD.

[0233] Then, for example, Fig.61 As shown, through opening 153A ( Fig.39 ) and the opening 171A, and a semiconductor layer 173 is formed on the upper surface, the lower surface, and the side surfaces in the X direction and the Y direction of the wiring 171. This process is performed by, for example, CVD or the like.

[0234] Then, for example, Fig.61 As shown, the sacrificial layer 172B is removed. This process is performed by, for example, wet etching or the like.

[0235] Then, for example, Fig.62 As shown, the oxide film MLB is removed. This step is performed by, for example, wet etching.

[0236] Then, for example, Fig.63 As shown, wiring 172 is formed. This process is performed, for example, by referring to Figure 55 to Figure 59 The steps described above are performed in the same manner.

[0237] Then, for example, Fig.64 As shown, an insulating layer 174 is formed. This step is performed by, for example, CVD or the like.

[0238] Then, for example, Fig.65 and Fig.66 As shown, the sacrificial layer 120B is removed. This process is performed by, for example, wet etching.

[0239] Then, for example, Fig.67 and Fig.68 As shown in FIG. 1 , the oxide film MLB and a portion of the insulating layer 162 (the exposed portion exposed to the opening 120A) are removed. This step is performed by, for example, wet etching or the like.

[0240] Then, for example, Fig.69 and Fig.70 As shown, a conductive layer 120 is formed. This step is performed by, for example, CVD or the like.

[0241] Then, for example, Fig.71 As shown, the sacrificial layer 111B is removed inside the opening 104A. This process is performed by, for example, wet etching or the like.

[0242] Then, for example, Fig.72 As shown, the semiconductor layer 111 is formed inside the openings 111A and 104A. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. This process is performed by ALD or the like, for example.

[0243] Then, for example, Fig.73 As shown, a resist 104C is formed inside the opening 104A.

[0244] Then, for example, Fig.74 As shown, the sacrificial layer 161B is removed inside the opening 154A. This process is performed by, for example, wet etching or the like.

[0245] Then, for example, Fig.75 As shown, the semiconductor layer 161 is formed inside the openings 161A and 154A. The opening 161A is filled with the semiconductor layer 161. On the other hand, the opening 154A is not filled with the semiconductor layer 161. This process is performed by ALD or the like, for example.

[0246] Then, for example, Fig.76 As shown, the resist 104C is removed.

[0247] Then, for example, Fig.76 As shown in FIG. 1 , a conductive oxide film 104a is formed inside the opening 104A. Fig.77 As shown in FIG. 1 , a conductive oxide film 154 a is formed inside the opening 154A. This step is performed by, for example, ALD or the like.

[0248] Then, for example, Figure 7As shown in FIG. 1 , a barrier conductive film 104b and a conductive member 104c are formed inside the opening 104A. Fig. 9 As shown, a barrier conductive film 154b and a conductive member 154c are formed inside the opening 154A. This process is performed by a method such as CVD. Figures 4 to 10 The structure described.

[0249] [Second embodiment]

[0250] In the first embodiment, the composition ratio of the material included in the semiconductor layer 111 in the transistor layer TL is the same as the composition ratio of the material included in the semiconductor layer 111 in the storage layer ML. However, such a configuration is only an example, and the specific configuration of the transistor layer TL can be adjusted appropriately. For example, the composition ratio of the material included in the semiconductor layer 111 in the transistor layer TL can also be different from the composition ratio of the material included in the semiconductor layer 111 in the storage layer ML. Thus, the threshold voltage of the transistor TrB can also be set to a lower value (for example, a value lower than the threshold voltage of the transistor TrC). Below, such a configuration is exemplified as a semiconductor storage device involved in the second embodiment.

[0251] [constitute]

[0252] Fig.78 This is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the second embodiment. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof will be omitted.

[0253] The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes a transistor layer TL2 instead of the transistor layer TL.

[0254] The transistor layer TL2 is basically configured similarly to the transistor layer TL. However, the transistor layer TL2 includes a transistor structure 210 instead of the transistor structure 110 .

[0255] The transistor structure 210 is basically configured similarly to the transistor structure 110 . However, the transistor structure 210 includes a semiconductor layer 211 instead of the semiconductor layer 111 .

[0256] The semiconductor layer 211 is basically configured similarly to the semiconductor layer 111. However, the concentration of indium in the semiconductor layer 211 is greater than the concentration of indium in the semiconductor layer 111. In addition, the concentration of gallium in the semiconductor layer 211 is less than the concentration of gallium in the semiconductor layer 111. Thus, the transistor TrB ( Figure 1 ) has a threshold voltage greater than that of transistor TrC ( Figure 1) has a low threshold voltage.

[0257] [Manufacturing method]

[0258] Next, a method for manufacturing a semiconductor memory device according to the second embodiment is described. Here, a method for manufacturing a semiconductor memory device according to the second embodiment is described by forming a memory cell array MCA and the like with a semiconductor substrate Sub( Figure 4 ) and the above-mentioned control circuit are formed on different wafers, and these two wafers are bonded together to manufacture an example of a semiconductor storage device involved in the second embodiment.

[0259] Figures 79 to 84 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0260] When manufacturing the semiconductor memory device according to the second embodiment, for example, referring to Figure 11 to Figure 72 However, these steps are performed in such a manner that the upper structure of the memory cell array MCA is arranged below and the lower structure is arranged above the wafer (not shown). Fig.11 In the described process, first, a plurality of sacrificial layers MLA corresponding to the memory layer ML are formed, and then the sacrificial layer MLA corresponding to the transistor layer TL is formed.

[0261] Then, if Fig.79 As shown in FIG. 1 , a sacrificial layer 204A is formed inside the opening 104A. This process is performed by, for example, CVD or the like.

[0262] Then, if Fig.80 As shown, a portion of the sacrificial layer 204A is removed, so that a portion of the semiconductor layer 111 provided at a position corresponding to the transistor layer TL is exposed inside the opening 104A. This step is performed by, for example, wet etching or the like.

[0263] Then, if Fig.81 As shown in FIG. 1 , a portion of the semiconductor layer 111 provided at a position corresponding to the transistor layer TL is removed. This step is performed by, for example, wet etching or the like.

[0264] Then, if Fig.82 As shown, a semiconductor layer 211A is formed inside the openings 111A and 104A and on the upper surface of the sacrificial layer 204A. The opening 111A is filled with the semiconductor layer 211A. On the other hand, the opening 104A is not filled with the semiconductor layer 211A. This process is performed by ALD or the like, for example.

[0265] Then, if Fig.83As shown in FIG. 1 , a portion of the semiconductor layer 211A provided on the upper surface of the sacrificial layer 204A is removed. Thus, the semiconductor layer 211 is formed. This step is performed by, for example, RIE or the like.

[0266] Then, if Fig.84 As shown, the sacrificial layer 204A is removed. This process is performed by, for example, wet etching.

[0267] Next, by executing the manufacturing method according to the first embodiment, referring to Fig.72 The following steps are performed to form the memory cell array MCA of the semiconductor memory device according to the second embodiment. In addition, the wafer on which the memory cell array MCA is formed is turned upside down and the wafer on which the semiconductor substrate Sub ( Figure 4 ) and the above-mentioned control circuit wafer bonding. Thus, the semiconductor storage device involved in the second embodiment is manufactured.

[0268] [Third Embodiment]

[0269] In the first embodiment, as shown in FIG. Figure 71 to Figure 75 As described above, the semiconductor layer 111 and the semiconductor layer 161 having different compositions are formed by different steps. Figures 79 to 84 As described above, the semiconductor layer 111 and the semiconductor layer 211 having different compositions are formed by different processes. However, such a method is only an example, and the method of forming the semiconductor layers having different compositions can be appropriately adjusted, for example, the films can be formed at the same time. Thus, the number of manufacturing processes can be reduced. Hereinafter, such a configuration is exemplified as a semiconductor memory device according to the third embodiment.

[0270] [constitute]

[0271] Fig.85 and Fig.86 This is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the third embodiment. In the following description, the same reference numerals are used to denote the same parts as those in the second embodiment, and the description thereof will be omitted.

[0272] The semiconductor memory device according to the third embodiment has basically the same configuration as the semiconductor memory device according to the second embodiment.

[0273] However, the semiconductor memory device according to the third embodiment includes a memory layer ML3 and a transistor layer TL3 instead of the memory layer ML and the transistor layer TL2 .

[0274] The memory layer ML3 and the transistor layer TL3 are basically configured similarly to the memory layer ML and the transistor layer TL2 . However, the memory layer ML3 includes a transistor structure 360 ​​instead of the transistor structure 160 . In addition, the transistor layer TL3 includes a transistor structure 310 instead of the transistor structure 210 .

[0275] The transistor structure 360 ​​is basically configured similarly to the transistor structure 160 . However, the transistor structure 360 ​​includes a semiconductor layer 361 and an insulating layer 362 instead of the semiconductor layer 161 and the insulating layer 162 .

[0276] The semiconductor layer 361 is basically configured similarly to the semiconductor layer 161. However, the length of the semiconductor layer 161 in the Z direction is equal to the length of the semiconductor layer 111 in the Z direction. On the other hand, the length of the semiconductor layer 361 in the Z direction is greater than the length of the semiconductor layer 111 in the Z direction.

[0277] In addition, focusing on the upper surface and lower surface of the semiconductor layer 361 and the region R near the wiring 171 SL The region R near the center position of the semiconductor layer 361 in the Z direction CL In the case of area R CL The concentration of indium in the region R can be greater than SL In addition, the concentration of indium in region R CL The gallium concentration in region R can be SL In addition, in region R SL With area R CL Indium and gallium have equal concentrations.

[0278] The insulating layer 362 is basically configured similarly to the insulating layer 162. However, the film thickness of the insulating layer 162 (the distance between the semiconductor layer 161 and the conductive layer 163) is equal to the film thickness of the semiconductor layer 111 (the distance between the semiconductor layer 111 and the conductive layer 113). On the other hand, the film thickness of the insulating layer 362 (the distance between the semiconductor layer 361 and the conductive layer 163) is smaller than the film thickness of the semiconductor layer 111.

[0279] The transistor structure 310 is basically configured similarly to the transistor structure 210 . However, the transistor structure 310 includes a semiconductor layer 311 instead of the semiconductor layer 211 .

[0280] The semiconductor layer 311 is basically configured similarly to the semiconductor layer 211. However, focusing on the upper surface and lower surface of the semiconductor layer 311 and the region R near the conductive layer 133, SB The region R near the center position of the semiconductor layer 311 in the Z direction CB In the case of area R CBThe concentration of indium in the region R can be greater than SB In addition, the concentration of indium in region R CB The gallium concentration in region R can be SB In addition, in region R SB With area R CB Indium and gallium have equal concentrations.

[0281] [Manufacturing method]

[0282] Fig.87 and Fig.88 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the third embodiment.

[0283] When manufacturing the semiconductor memory device according to the third embodiment, for example, referring to Figures 11 to 70 The process described.

[0284] Then, if Fig.71 As shown in FIG. 1 , the sacrificial layer 111B is removed from the interior of the opening 104A. Fig.74 As shown, the sacrificial layer 161B is removed inside the opening 154A. This process is performed by, for example, wet etching, etc. Although not shown in the figure, after the sacrificial layers 111B and 161B are removed, the upper part of the opening 104A is closed with an insulating layer or the like.

[0285] Then, if Fig.87 As shown, a part of the insulating layer 112 is removed inside the opening 154A to reduce the thickness of the insulating layer 112, thereby forming the insulating layer 362. This step is performed by, for example, wet etching or the like.

[0286] Next, after removing the insulating layer and the like above the opening 104A, for example, Fig.72 As shown in FIG. 1 , a semiconductor layer 111 is formed inside the openings 111A and 104A. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. Fig.88 As shown, the semiconductor layer 361 is formed inside the openings 161A and 154A. The opening 161A is filled with the semiconductor layer 361. On the other hand, the opening 154A is not filled with the semiconductor layer 361. This process is performed by ALD or the like, for example.

[0287] In this process, the concentration of indium can be increased continuously or in stages from the start of film formation to the end of film formation, and the concentration of gallium can be decreased continuously or in stages.

[0288] Here, after executing the reference Fig.87At the timing after the described process is performed, the length of the opening 161A in the Z direction is greater than that of the opening 111A ( Fig.71 ) in the Z direction. Therefore, when the film is formed simultaneously inside the openings 111A and 161A, the opening 111A is closed first. Therefore, after the opening 111A is closed, the concentration of indium in the semiconductor layer 361 is increased and the concentration of gallium is maintained or reduced, so that the region R as described above can be formed inside the semiconductor layer 361. CL .

[0289] In addition, Fig.86 In the example of FIG. 1 , the length of the semiconductor layer 111 in the transistor layer TL in the Z direction is greater than the length of the semiconductor layer 111 in the memory layer ML in the Z direction. Fig.87 At the timing after the described steps are performed, the length of the opening 111A in the transistor layer TL3 in the Z direction becomes larger than the length of the opening 111A in the memory layer ML3 in the Z direction. Therefore, after the opening 111A in the memory layer ML3 is closed, the concentration of indium in the semiconductor layer 311 is increased and the concentration of gallium is decreased, so that the region R described above can be formed inside the semiconductor layer 311. CB .

[0290] [Fourth embodiment]

[0291] In the first to third embodiments, the semiconductor layers 111, 161, etc. include oxide semiconductors. However, such a configuration is only an example, and the specific configuration can be adjusted appropriately. For example, the semiconductor layers 111, 161, etc. may also include materials other than oxide semiconductors such as silicon (Si) and germanium (Ge). Below, such a configuration is exemplified as a semiconductor memory device involved in the fourth embodiment.

[0292] [constitute]

[0293] Fig.89 and Fig.90 This is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the fourth embodiment. In the following description, the same reference numerals are used to denote the same parts as those in the first embodiment, and the description thereof will be omitted.

[0294] The semiconductor memory device according to the fourth embodiment has basically the same configuration as the semiconductor memory device according to the first embodiment.

[0295] However, the semiconductor memory device according to the fourth embodiment includes via wirings 404 and 454 , a memory layer ML4 , and a transistor layer TL4 instead of the via wirings 104 and 154 , the memory layer ML, and the transistor layer TL.

[0296] The via wirings 404 and 454 are basically configured similarly to the via wirings 104 and 154. However, the via wirings 404 and 454 include semiconductor films 404a and 454a instead of the conductive oxide film 104a ( Figure 7 ) and the conductive oxide film 154a ( Fig. 9 ). The semiconductor films 404a and 454a are basically configured in the same manner as the conductive oxide films 104a and 154a. However, the semiconductor films 404a and 454a have silicon (Si) as a main component and contain N-type impurities such as phosphorus (P) and arsenic (As). In addition, in this specification, when the term "main component" is used, it means the element that contains the most. For example, the element that contains the most in the semiconductor films 404a and 454a is silicon (Si).

[0297] The memory layer ML4 and the transistor layer TL4 are basically configured similarly to the memory layer ML and the transistor layer TL. However, the memory layer ML4 and the transistor layer TL4 include transistor structures 410 and 460 instead of the transistor structures 110 and 160, respectively.

[0298] The transistor structure 410 is basically configured similarly to the transistor structure 110 . However, the transistor structure 410 includes a semiconductor layer 411 instead of the semiconductor layer 111 .

[0299] The semiconductor layer 411 is basically configured similarly to the semiconductor layer 111. However, the semiconductor layer 411 contains silicon (Si) as a main component and contains P-type impurities such as boron (B).

[0300] In the fourth embodiment, the conductive layer 133 contains silicon (Si) as a main component and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0301] The transistor structure 460 is basically configured similarly to the transistor structure 160 . However, the transistor structure 460 includes a semiconductor layer 461 instead of the semiconductor layer 161 .

[0302] The semiconductor layer 461 is basically configured similarly to the semiconductor layer 161. However, the semiconductor layer 461 contains silicon (Si) as a main component and contains P-type impurities such as boron (B).

[0303] In the fourth embodiment, the wiring 171 contains silicon (Si) as a main component and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0304] Here, the concentration of the P-type impurities in the semiconductor layer 461 is lower than the concentration of the P-type impurities in the semiconductor layer 411. Thus, the transistor TrL ( Figure 1 ) has a threshold voltage greater than that of transistor TrC ( Figure 1 ) has a low threshold voltage.

[0305] [Fifth embodiment]

[0306] In the first to third embodiments, the semiconductor layer 161 etc. functioning as the channel region of the transistor TrL, the semiconductor layer 111 etc. functioning as the channel region of the transistor TrB, and the semiconductor layer 111 functioning as the channel region of the transistor TrC include an oxide semiconductor in the same manner. In addition, in the fourth embodiment, the semiconductor layer 461 functioning as the channel region of the transistor TrL and the semiconductor layer 411 functioning as the channel region of the transistor TrB, and the semiconductor layer 411 functioning as the channel region of the transistor TrC, include silicon as a main component and contain P-type impurities such as boron (B) in the same manner.

[0307] However, such a structure is only an example, and the specific structure can be adjusted appropriately. For example, the semiconductor layer 161 etc. that functions as the channel region of the transistor TrL, the semiconductor layer 111 etc. that functions as the channel region of the transistor TrB may also include a material different from the semiconductor layer 111 etc. that functions as the channel region of the transistor TrC. For example, one to three of the semiconductor layer 111 etc. in the storage layer ML, the semiconductor layer 161 etc. in the storage layer ML, the semiconductor layer 111 etc. in the transistor layer TL, and the semiconductor layer 161 etc. in the transistor layer TL may include an oxide semiconductor, and the remaining three to one may include a material other than an oxide semiconductor such as silicon or germanium. Below, such a structure is exemplified as a semiconductor storage device involved in the fifth embodiment.

[0308] [constitute]

[0309] Fig.91 and Fig.92 This is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the fifth embodiment. In the following description, the same reference numerals are used to denote the same parts as those in the second embodiment, and the description thereof will be omitted.

[0310] The semiconductor memory device according to the fifth embodiment has basically the same configuration as the semiconductor memory device according to the second embodiment.

[0311] However, the semiconductor memory device according to the fifth embodiment includes a via wiring 454 , a memory layer ML5 , and a transistor layer TL5 instead of the via wiring 154 , the memory layer ML, and the transistor layer TL2 .

[0312] The memory layer ML5 and the transistor layer TL5 are basically configured similarly to the memory layer ML and the transistor layer TL2 , but each of the memory layer ML5 and the transistor layer TL5 includes a transistor structure 460 instead of the transistor structure 160 .

[0313] In the fifth embodiment, the wiring 171 contains silicon (Si) as a main component and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0314] In the fifth embodiment, the transistor TrL ( Figure 1 ) is also higher than the threshold voltage of transistor TrC ( Figure 1 ) has a low threshold voltage.

[0315] [Sixth embodiment]

[0316] In the first to fifth embodiments, the transistor TrL ( Figure 1 ) is an example of an N-channel field effect transistor. However, such a configuration is only an example, and the specific configuration can be adjusted appropriately. For example, the transistor TrL can also be configured as a P-channel field effect transistor. Below, such a configuration is exemplified as a semiconductor storage device involved in the sixth embodiment.

[0317] [constitute]

[0318] Fig.93 This is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the sixth embodiment. In the following description, the same reference numerals are used to denote the same parts as those in the fourth embodiment, and the description thereof will be omitted.

[0319] The semiconductor memory device according to the sixth embodiment has basically the same configuration as the semiconductor memory device according to the fourth embodiment.

[0320] However, the semiconductor memory device according to the sixth embodiment includes a via wiring 654 , a memory layer ML6 , and a transistor layer TL6 instead of the via wiring 454 , the memory layer ML4 , and the transistor layer TL4 .

[0321] The via wiring 654 is basically configured similarly to the via wiring 454. However, the via wiring 654 includes a semiconductor film 654a instead of the semiconductor film 454a ( Fig.89 The semiconductor film 654a is basically configured similarly to the semiconductor film 454a. However, the semiconductor film 654a contains not only N-type impurities but also P-type impurities such as boron (B).

[0322] The memory layer ML6 and the transistor layer TL6 are basically configured similarly to the memory layer ML4 and the transistor layer TL4 , but each of the memory layer ML6 and the transistor layer TL6 includes a transistor structure 660 instead of the transistor structure 460 .

[0323] The transistor structure 660 is basically configured similarly to the transistor structure 460 . However, the transistor structure 660 includes a semiconductor layer 661 instead of the semiconductor layer 461 .

[0324] The semiconductor layer 661 is basically configured similarly to the semiconductor layer 461. However, the semiconductor layer 661 contains silicon (Si) as a main component and contains N-type impurities such as phosphorus (P) and arsenic (As).

[0325] In the sixth embodiment, the wiring 171 contains silicon (Si) as a main component and contains P-type impurities such as boron (B).

[0326] [Seventh embodiment]

[0327] In the first to sixth embodiments, the bit line BL is implemented by the via wiring 104 extending in the Z direction, and the word line WL is implemented by the plurality of conductive layers 120 arranged in the Z direction. However, such a configuration is only an example, and the specific configuration can be adjusted appropriately. For example, the word line WL can be implemented by the via wiring (via electrode) extending in the Z direction, and the bit line BL can be implemented by the plurality of conductive layers arranged in the Z direction. Hereinafter, such a configuration is exemplified as a semiconductor memory device involved in the seventh embodiment.

[0328] [Circuit Configuration]

[0329] Fig.94 1 is a schematic circuit diagram showing a partial configuration of a semiconductor memory device according to Embodiment 7. In the following description, the same reference numerals are used to denote the same components as those in Embodiment 1, and description thereof will be omitted.

[0330] The semiconductor memory device according to the seventh embodiment includes a memory cell array MCA7. The memory cell array MCA7 includes a plurality of memory layers ML7, a plurality of word lines WL connected to the plurality of memory layers ML7, and plate lines PL connected to the plurality of memory layers ML7.

[0331] The storage layer ML7 includes a plurality of bit lines BL0 to BL2 (hereinafter sometimes referred to as "bit lines BL") and a plurality of storage cells MC7 connected to the plurality of bit lines BL. The storage cells MC7 include a transistor TrC7 and a capacitor CpC. One electrode of the transistor TrC7 is connected to the bit line BL. The other electrode of the transistor TrC7 is connected to the capacitor CpC. In addition, one electrode and the other electrode of the transistor TrC7 function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrC7. The gate electrode of the transistor TrC7 is connected to the word line WL. One electrode of the capacitor CpC is connected to the drain electrode of the transistor TrC7. The other electrode of the capacitor CpC is connected to the plate line PL.

[0332] In addition, each word line WL is connected to a plurality of memory cells MC7 corresponding to a plurality of memory layers ML7 .

[0333] In addition, the storage layer ML7 includes a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, TrL3b respectively provided in correspondence with the plurality of bit lines BL0 to BL2. One electrode of the transistor TrL is connected to any one of the bit lines BL0 to BL2. The other electrode of the transistor TrL is connected to the layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, LL2b, LL3a, LL3b respectively. In addition, one electrode and the other electrode of the transistor TrL function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrL. The gate electrode of the transistor TrL is connected to the bit line selection lines LB0a, LB0b, LB1a, LB1b, LB2a, LB2b (hereinafter sometimes referred to as "bit line selection line LB7") respectively.

[0334] In addition, the bit line selection line LB7 is connected to a plurality of transistors TrL corresponding to a plurality of storage layers ML7. In addition, the layer selection lines LL0a, LL1a, LL2a, and LL3a are respectively commonly connected to all transistors TrL0a, TrL1a, TrL2a, and TrL3a corresponding to a plurality of storage layers ML7. Similarly, the layer selection lines LL0b, LL1b, LL2b, and LL3b are respectively commonly connected to all transistors TrL0b, TrL1b, TrL2b, and TrL3b corresponding to a plurality of storage layers ML7.

[0335] [structure]

[0336] Fig.95 1 is a schematic perspective view showing a part of the structure of the semiconductor storage device according to the present embodiment. Fig.95 , a portion of a semiconductor substrate Sub and a memory cell array MCA7 disposed above the semiconductor substrate Sub are shown.

[0337] The memory cell array MCA7 includes a plurality of memory layers ML7 stacked in the Z direction. In addition, silicon oxide (SiO 2 ) and the like insulating layer 103.

[0338] Fig.96 Schematic XY cross-sectional view showing the structure of a part of the storage layer ML7. Fig.96 As shown, a memory cell region R is provided in the memory layer ML7. MC7 and transistor area R TrL7 Although not shown in the figure, the transistor region R TrL7 The Y direction is arranged in the memory cell region R MC7 on both sides.

[0339] [Memory cell area RMC7 Structure of

[0340] Then, except Fig.95 and Fig.96 In addition, refer to Fig.97 , for the storage cell region R MC7 The structure of is described below. Fig.97 Shows the Fig.96 The structure shown is a cross section cut along line AA′ and observed in the direction of the arrow.

[0341] like Fig.96 As shown, in the storage unit area R MC7 A plurality of insulating layers 101 arranged in the X direction and a conductive layer 102 provided between two insulating layers 101 adjacent to each other in the X direction are provided. The insulating layer 101 and the conductive layer 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML7 in the X direction (see Fig.95 ).

[0342] A plurality of via electrodes 704 are provided in the region between the insulating layer 101 and the conductive layer 102. The plurality of via electrodes 704 are arranged in the Y direction, and are, for example, Fig.95 As shown, it extends in the Z direction while penetrating the plurality of storage layers ML7.

[0343] like Fig.97 As shown, the via electrode 704 includes, for example, a barrier conductive film 704 a made of titanium nitride (TiN) or the like and a conductive member 704 b made of tungsten (W) or the like.

[0344] The conductive member 704b has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 704a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 704b.

[0345] The via electrode 704 serves as a word line WL ( Fig.94 ) to perform its function. For example, Fig.94 As shown, a plurality of word lines WL are provided corresponding to a plurality of transistors TrC7 included in the memory layer ML7.

[0346] The memory layer ML7 includes: a plurality of transistor structures 710 provided corresponding to the plurality of via electrodes 704 , a conductive layer 720 provided on the opposite side of the conductive layer 102 relative to the plurality of transistor structures 710 , and a plurality of capacitor structures 730 provided between the plurality of transistor structures 710 and the conductive layer 102 .

[0347] The transistor structure 710 includes: a roughly disk-shaped conductive layer 711 continuous with the conductive component 704b, a blocking conductive film 712 continuous with the blocking conductive film 704a and arranged on the upper surface, lower surface, both side surfaces in the Y direction and both side surfaces in the X direction of the conductive layer 711, an insulating layer 713 arranged on the upper surface, lower surface, both side surfaces in the Y direction and both side surfaces in the X direction of the blocking conductive film 712, and a semiconductor layer 714 arranged on the upper surface, lower surface, both side surfaces in the Y direction and both side surfaces in the X direction of the insulating layer 713.

[0348] exist Fig.96 In the XY cross section as illustrated, the side surfaces of the semiconductor layer 714 on both sides in the X direction may be formed along a circle centered at the center position of the via electrode 704. In addition, the side surfaces of the semiconductor layer 714 on both sides in the Y direction may be formed in a straight line along the side surfaces of the insulating layer 115. In addition, the outer peripheral surfaces of the barrier conductive film 712 and the insulating layer 713 may be formed along a circle centered at the center position of the via electrode 704.

[0349] The conductive layer 711 and the blocking conductive film 712 serve as, for example, a transistor TrC7 ( Fig.94 ) functions as a gate electrode. The conductive layer 711 includes a conductive member such as tungsten (W). The barrier conductive film 712 includes, for example, titanium nitride (TiN).

[0350] The insulating layer 713 serves as, for example, a transistor TrC7 ( Fig.94 ) functions as a gate insulating film. The insulating layer 713 contains, for example, silicon oxide (SiO 2 )wait.

[0351] The semiconductor layer 714 serves as, for example, a transistor TrC7 ( Fig.94 ) in the channel region. The semiconductor layer 714 can be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O), or other oxide semiconductors. The plurality of semiconductor layers 714 arranged in the Y direction are commonly connected to the conductive layer 720 extending in the Y direction. The semiconductor layer 714 is opposite to the upper surface, the lower surface, the two side surfaces in the Y direction, and the two side surfaces in the X direction of the blocking conductive film 712 through the insulating layer 713.

[0352] Silicon oxide (SiO 2 ) etc. The insulating layer 115 extends in the Z direction penetrating through the plurality of memory layers ML7.

[0353] The conductive layer 720 serves as a bit line BL ( Fig.94) functions. The conductive layer 720 extends in the Y direction and is connected to a plurality of semiconductor layers 714 arranged in the Y direction. The conductive layer 720, for example, includes a conductive oxide film 723 containing a conductive oxide, a barrier conductive film 722 of titanium nitride (TiN) or the like, and a conductive film 721 of tungsten (W). In addition, the conductive layer 720 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide film 723. In addition, the conductive layer 720 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0354] For example Fig.97 As shown, the capacitor structure 730 includes: a conductive layer 731, a blocking conductive film 732 provided on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the transistor structure 710 side) of the conductive layer 731, an insulating layer 733 provided on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the transistor structure 710 side) of the blocking conductive film 732, and an insulating layer 733 provided on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the transistor structure 710 side) of the insulating layer 733. A conductive layer 734 is provided on the side (transistor structure 710 side), an insulating layer 735 is provided on the upper surface, the lower surface and the two side surfaces in the Y direction of the conductive layer 734 and the side surface in the X direction of the insulating layer 103, a blocking conductive film 736 is provided on the upper surface, the lower surface and the two side surfaces in the Y direction of the insulating layer 735 and the side surface in the X direction of the insulating layer 103, and a conductive layer 737 is provided on the upper surface, the lower surface, the two side surfaces in the Y direction and the side surface of one side in the X direction (transistor structure 710 side) of the blocking conductive film 736.

[0355] The conductive layers 731, 737 and the barrier conductive films 732, 736 serve as a capacitor CpC ( Fig.94 ) functions as an electrode on one side. The conductive layers 731 and 737 include a conductive member such as tungsten (W). The barrier conductive films 732 and 736 include, for example, titanium nitride (TiN). The conductive layers 731 and 737 and the barrier conductive films 732 and 736 are continuous with the conductive layer 102.

[0356] The insulating layers 733 and 735 serve as capacitors CpC ( Fig.94 ) function as an insulating layer. The insulating layers 733 and 735 may be, for example, zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ) or other insulating metal oxides. In addition, the insulating layers 733 and 735 may be, for example, a stacked film of a plurality of insulating metal oxides (for example, a stacked film of zirconium oxide and aluminum oxide).

[0357] The conductive layer 734 serves as a capacitor CpC ( Fig.94 ) functions as the other electrode. The conductive layer 734 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 734 is insulated from the barrier conductive films 732 and 736 via the insulating layers 733 and 735. The conductive layer 734 is connected to the side surface of the semiconductor layer 714 in the X direction.

[0358] [Transistor region R TrL7 Structure of

[0359] Then, except Fig.95 and Fig.96 In addition, refer to Fig.98 , for transistor area R TrL7 The structure of is described below. Fig.98 Shows the Fig.96 The structure shown is a cross section cut along line BB′ and observed in the direction of the arrow.

[0360] like Fig.96 As shown, in the transistor region R TrL7 There are provided a plurality of insulating layers 151 arranged in the X direction corresponding to the plurality of insulating layers 101 , and an insulating layer 152 provided between two insulating layers 151 adjacent to each other in the X direction.

[0361] In addition, in the memory cell region R MC7 With transistor area R TrL7 An insulating layer 165 extending in the X direction is provided between two conductive layers 720 adjacent to each other in the X direction.

[0362] A plurality of via electrodes 754 are provided in the region between the insulating layer 151 and the insulating layer 152. The plurality of via electrodes 754 are arranged in the Y direction, and are, for example, Fig.98 As shown, it extends in the Z direction through the plurality of storage layers ML7.

[0363] like Fig.98 As shown, the via electrode 754 includes, for example, a barrier conductive film 754 a made of titanium nitride (TiN) or the like and a conductive member 754 b made of tungsten (W) or the like.

[0364] The conductive member 754b has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 754a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 754b.

[0365] The plurality of via electrodes 754 arranged in the Y direction serve as, for example, one bit line selection line LB7 ( Fig.94 ) to perform its function. For example, Fig.94As shown, a plurality of bit line selection lines LB7 are provided corresponding to a plurality of bit lines BL included in the memory layer ML7.

[0366] The memory layer ML7 includes a plurality of transistor structures 760 provided corresponding to the plurality of conductive layers 720 , a wiring 171 provided between the transistor structure 760 and the insulating layer 151 , and a wiring 772 provided between the transistor structure 760 and the insulating layer 152 .

[0367] The transistor structure 760 includes: a conductive layer 761 continuous with the outer peripheral surface of a plurality of via electrodes 754, a blocking conductive film 762 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the two side surfaces in the X direction of the conductive layer 761, an insulating layer 763 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the two side surfaces in the X direction of the blocking conductive film 762, and a semiconductor layer 764 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the two side surfaces in the X direction of the insulating layer 763.

[0368] exist Fig.96 In the XY cross section as illustrated, the side surfaces of the semiconductor layer 764 on both sides in the X direction may be formed along a plurality of overlapping circles centered on the plurality of center positions of the plurality of via electrodes 754. In addition, the outer peripheral surfaces of the blocking conductive film 762 and the insulating layer 763 may be formed along a plurality of mutually separated circles centered on the plurality of center positions of the plurality of via electrodes 754.

[0369] The conductive layer 761 and the blocking conductive film 762 serve as, for example, a transistor TrL7 ( Fig.94 ) functions as a gate electrode. The conductive layer 761 includes a conductive member such as tungsten (W). The barrier conductive film 762 includes, for example, titanium nitride (TiN).

[0370] The insulating layer 763 serves as, for example, a transistor TrL7 ( Fig.94 ) functions as a gate insulating film. The insulating layer 763 contains, for example, silicon oxide (SiO 2 )wait.

[0371] The semiconductor layer 764 serves as, for example, a transistor TrL7 ( Fig.94 ) in the channel region. The semiconductor layer 764 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or another oxide semiconductor. The semiconductor layer 764 is electrically connected to the wirings 171 and 772.

[0372] Here, the concentration of indium in the semiconductor layer 764 is greater than the concentration of indium in the semiconductor layer 714. In addition, the concentration of gallium in the semiconductor layer 764 is less than the concentration of gallium in the semiconductor layer 714. As a result, the transistor TrL ( Fig.94 ) has a threshold voltage higher than that of transistor TrC7 ( Fig.94 ) has a low threshold voltage.

[0373] like Fig.96 As shown in FIG. 1 , the wiring 772 includes a portion extending in the Y direction and a portion extending in the X direction. The portion extending in the Y direction of the wiring 772 is connected to the semiconductor layer 764. The wiring 772 has a structure that connects the transistor TrL ( Fig.94 ) is connected to the source electrode of the control circuit. The wiring 772 contains, for example, a conductive oxide. In addition, the wiring 772 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the wiring 772 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0374] [Other embodiments]

[0375] The semiconductor memory devices according to the first to seventh embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and specific configurations and the like can be appropriately adjusted.

[0376] For example, in the semiconductor memory devices according to the fourth to sixth embodiments, the concentration of the P-type impurities in the semiconductor layers 411 and 111 in the transistor layers TL4, TL5, and TL6 may be made smaller than the concentration of the P-type impurities in the semiconductor layers 411 and 111 in the memory layers ML4, ML5, and ML6. Figure 1 ) has a threshold voltage greater than that of transistor TrC ( Figure 1 ) has a low threshold voltage.

[0377] In addition, for example, in the semiconductor memory devices according to the second to fourth embodiments, only the transistor TrB ( Figure 1 ) threshold voltage, without adjusting transistor TrL( Figure 1 ) threshold voltage. For example, in the second and third embodiments, the concentration of indium and the concentration of gallium in the semiconductor layers 161 and 361 may be respectively equal to the concentration of indium and the concentration of gallium in the semiconductor layer 111. In addition, in the fourth embodiment, the concentration of the P-type impurity in the semiconductor layer 461 may be equal to the concentration of the P-type impurity in the semiconductor layer 411.

[0378] In addition, for example, when manufacturing the semiconductor memory device according to the fourth embodiment, the semiconductor layers 411 and 461 may be formed at once by the method described in the third embodiment. In this case, the reference electrode may be provided in the semiconductor layer 461. Fig.85 The region R as described above SL , R CL , Region R CL The concentration of P-type impurities in region R SL The concentration of P-type impurities in is small.

[0379] In addition, for example, when manufacturing the semiconductor memory device according to any of the embodiments, the region R may be formed by the method exemplified in the third embodiment. CL Contains area R SL Different materials. Similarly, it is also possible to make area R CB Contains area R SB Different materials.

[0380] In addition, for example, in the semiconductor memory device according to the seventh embodiment, the semiconductor layers 714 and 764 may also contain silicon (Si) as a main component and contain P-type impurities such as boron (B). In this case, the concentration of the P-type impurities in the semiconductor layer 764 may be lower than the concentration of the P-type impurities in the semiconductor layer 714. In addition, the semiconductor layer 764 may also contain a material different from that of the semiconductor layer 714.

[0381] In the semiconductor memory devices according to the first to third embodiments, the via wirings 104, 154, etc. functioning as bit lines include conductive oxides such as indium tin oxide (ITO). However, such conductive oxides may be included in the transistor structures 110, 160, etc. instead of the via wirings 104, 154, etc. extending in the Z direction. In addition, the via wirings 104, 154, etc. and the transistor structures 110, 160 may include other materials, etc.

[0382] In the semiconductor memory devices according to the fourth and sixth embodiments, the via wirings 404, 454, etc. functioning as bit lines include semiconductor films 404a, 454a, etc. However, such semiconductor films 404a, 454a, etc. may not be included in the via wirings 404, 454, etc. extending in the Z direction, but may be included in the transistor structures 410, 460, etc. In addition, the via wirings 404, 454, etc. and the transistor structures 410, 460 may include other materials, etc.

[0383] In the semiconductor memory devices according to the first to sixth embodiments, the conductive layer 113 functioning as the gate electrode of the transistor TrC may face only one of the upper and lower surfaces of the semiconductor layer 111 functioning as the channel region of the transistor TrC.

[0384] In addition, in the above description, an example of using a capacitor CpC as a storage unit connected to the transistor structure 110 is described. However, the storage unit may not be the capacitor CpC. For example, the storage unit may include a ferroelectric, a ferromagnetic, a chalcogenide material such as GeSbTe, or other materials, and the characteristics of these materials may be used to record data. For example, in any of the structures described above, any of these materials may be included in the insulating layer between the electrodes forming the capacitor CpC.

[0385] The methods for manufacturing the semiconductor memory device according to the first to sixth embodiments can also be adjusted as appropriate. For example, the order of any two of the above steps may be switched or any two of the above steps may be performed simultaneously.

[0386] [other]

[0387] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and / or their variations are included in the scope and purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor storage device comprising: substrate; a plurality of first semiconductor layers stacked in a stacking direction intersecting with the surface of the substrate; a first via wiring extending in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of storage parts stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes stacked in the stacking direction and facing the plurality of first semiconductor layers; a plurality of first wirings stacked in the stacking direction and extending in a first direction intersecting the stacking direction and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers stacked in the stacking direction and electrically connected to the plurality of first gate electrodes via the plurality of first wirings; a second via wiring extending in the stacking direction and electrically connected to the plurality of second semiconductor layers; as well as a plurality of second gate electrodes stacked in the stacking direction and facing the plurality of second semiconductor layers, The plurality of second semiconductor layers include a material different from that of the plurality of first semiconductor layers, or a composition ratio of a material included in the plurality of second semiconductor layers is different from a composition ratio of a material included in the plurality of first semiconductor layers.

2. The semiconductor memory device according to claim 1, The first semiconductor layer and the second semiconductor layer each contain at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), The concentration of indium in the second semiconductor layer is greater than the concentration of indium in the first semiconductor layer.

3. The semiconductor memory device according to claim 1, The first semiconductor layer and the second semiconductor layer each contain silicon (Si) as a main component.

4. The semiconductor memory device according to claim 3, The first semiconductor layer and the second semiconductor layer each contain a P-type impurity. The concentration of the P-type impurity in the second semiconductor layer is lower than the concentration of the P-type impurity in the first semiconductor layer.

5. The semiconductor memory device according to claim 3, The first semiconductor layer contains P-type impurities, The second semiconductor layer contains N-type impurities.

6. The semiconductor memory device according to claim 1, The length of the second semiconductor layer in the stacking direction is greater than the length of the first semiconductor layer in the stacking direction.

7. The semiconductor memory device according to claim 1, The second semiconductor layer comprises: A first region and a second region arranged in the stacking direction; and a third area disposed between the first area and the second area, The third region includes a material different from that of the first region and the second region, or a composition ratio of a material included in the third region is different from a composition ratio of a material included in the first region and the second region.

8. The semiconductor memory device according to claim 1, comprising: a second wiring provided on one side of the plurality of first semiconductor layers in the stacking direction and extending in a second direction intersecting the stacking direction and the first direction; a third semiconductor layer disposed between the plurality of first semiconductor layers and the second wiring and electrically connected to the first via wiring and the second wiring; as well as a third gate electrode, which is opposite to the third semiconductor layer, The third semiconductor layer includes a material different from that of the plurality of first semiconductor layers, or a composition ratio of a material included in the third semiconductor layer is different from a composition ratio of a material included in the plurality of first semiconductor layers.

9. The semiconductor memory device according to claim 1, The storage unit is a capacitor.

10. The semiconductor memory device according to claim 1, The first gate electrode faces one or both of the surface on one side and the surface on the other side of the first semiconductor layer in the stacking direction. The storage unit is provided on one side of the first semiconductor layer in a second direction intersecting the stacking direction and the first direction. The first wiring is provided on the other side of the first semiconductor layer in the second direction.

11. A semiconductor storage device comprising: substrate; a plurality of semiconductor layers stacked in a stacking direction intersecting with a surface of the substrate; A via wiring extending in the stacking direction and electrically connected to the plurality of semiconductor layers; a plurality of storage sections stacked in the stacking direction and electrically connected to the plurality of semiconductor layers; a plurality of gate electrodes stacked in the stacking direction and opposite to the plurality of semiconductor layers; a plurality of first wirings stacked in the stacking direction and extending in a first direction intersecting the stacking direction and electrically connected to the plurality of gate electrodes; a second wiring provided on one side of the plurality of semiconductor layers in the stacking direction and extending in a second direction intersecting the stacking direction and the first direction; Another semiconductor layer, which is provided between the plurality of semiconductor layers and the second wiring and is electrically connected to the via wiring and the second wiring; as well as another gate electrode, which is opposite to the other semiconductor layer, The other semiconductor layer includes a material different from that of the plurality of semiconductor layers, or a composition ratio of a material included in the other semiconductor layer is different from a composition ratio of a material included in the plurality of semiconductor layers.

12. The semiconductor memory device according to claim 11, The semiconductor layer and the other semiconductor layer each contain at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O), The concentration of indium in the other semiconductor layer is greater than the concentration of indium in the semiconductor layer.

13. The semiconductor memory device according to claim 11, The semiconductor layer and the other semiconductor layer each contain silicon (Si) as a main component.

14. The semiconductor memory device according to claim 13, The semiconductor layer and the other semiconductor layer each contain P-type impurities, The concentration of the P-type impurities in the other semiconductor layers is lower than the concentration of the P-type impurities in the semiconductor layer.

15. The semiconductor memory device according to claim 13, The semiconductor layer contains P-type impurities, The other semiconductor layer contains N-type impurities.

16. The semiconductor memory device according to claim 11, The length of the other semiconductor layer in the stacking direction is greater than the length of the semiconductor layer in the stacking direction.

17. The semiconductor memory device according to claim 11, The other semiconductor layers include: A first region and a second region arranged in the stacking direction; and a third area disposed between the first area and the second area, The third region includes a material different from that of the first region and the second region, or a composition ratio of a material included in the third region is different from a composition ratio of a material included in the first region and the second region.

18. The semiconductor memory device according to claim 11, The storage unit is a capacitor.

19. The semiconductor memory device according to claim 11, The gate electrode faces one or both of the surface on one side and the surface on the other side in the stacking direction of the semiconductor layer. The storage unit is provided on one side in the second direction relative to the semiconductor layer. The first wiring is provided on the other side of the semiconductor layer in the second direction.

20. A semiconductor storage device comprising: substrate; a plurality of first semiconductor layers stacked in a stacking direction intersecting with the surface of the substrate; a first via electrode extending in the stacking direction and facing the plurality of first semiconductor layers; a plurality of storage parts stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers; a plurality of wirings stacked in the stacking direction and extending in a first direction intersecting the stacking direction, and electrically connected to the plurality of first semiconductor layers; a plurality of second semiconductor layers stacked in the stacking direction and electrically connected to the plurality of first semiconductor layers via the plurality of wirings; as well as a second via electrode extending in the stacking direction and facing the plurality of second semiconductor layers, The plurality of second semiconductor layers include a material different from that of the plurality of first semiconductor layers, or a composition ratio of a material included in the plurality of second semiconductor layers is different from a composition ratio of a material included in the plurality of first semiconductor layers.

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