Semiconductor device including stacked data lines

Abstract

The invention relates to a semiconductor device including stacked data lines. Some embodiments include devices and methods of forming the devices. One of the devices includes: a conductive contact; a conductive portion formed over the conductive contact; and data lines positioned over and separated from the first conductive portion by a dielectric material, the data lines being formed from respective levels of conductive material; and a conductive structure on one side of the level of conductive material. The levels of conductive material are stacked together in a first direction in different levels of the device. The conductive structure includes a first portion and a second portion. The first portion extends in the first direction and is coupled to one of the levels of conductive material. The second portion extends in a second direction and is coupled to the conductive portion.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 63 / 535,936, filed on August 31, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device including stacked data lines. Background Art

[0004] Semiconductor devices such as memory devices are widely used in computers and many other electronic objects to store information. Memory devices typically include memory cells and data lines to carry information (in the form of signals) to and from the memory cells. As the demand for memory cell density for a given device area increases, the number of data lines may also increase to keep pace with the increase in memory cell density. However, due to area limitations in some conventional memory devices, increasing the number of data lines in such conventional memory devices may pose a challenge. Summary of the invention

[0005] In one aspect, the present disclosure provides a device comprising: a conductive contact; a conductive portion formed above the conductive contact; a data line located above the conductive portion and separated from a first conductive portion by a dielectric material, the data line being formed by corresponding conductive material levels stacked on each other in a first direction in different levels of the device; and a conductive structure located on one side of the conductive material levels, the conductive structure comprising a first portion and a second portion, the first portion extending in the first direction and coupled to one of the conductive material levels, and the second portion extending in a second direction and coupled to the conductive portion.

[0006] In another aspect, the present disclosure provides a device comprising: a first conductive part; a second conductive part; conductive material levels stacked on each other and located above the first conductive part and the second conductive part; a dielectric material level interleaved with the conductive material level in a first direction, the conductive material level and the dielectric material level forming a material stack; a first conductive structure located on a first side of the material stack and contacting the first conductive part, wherein the first conductive structure contacts the first conductive material level in the conductive material level, and the first conductive structure includes a portion extending in a second direction and contacting the first conductive part; and a second conductive structure located on a second side of the material stack and contacting the second conductive part, wherein the second conductive structure contacts the second conductive material level in the conductive material level, and the second conductive structure includes a portion extending in the second direction and contacting the second conductive part.

[0007] In another aspect, the present disclosure provides a method comprising: forming a first dielectric material level and a second dielectric material level interleaved with the first dielectric material level, the first dielectric material level and the second dielectric material level being formed over conductive contacts of pillars of a memory cell string; forming a mask structure over the first dielectric material level and the second dielectric material level; removing a first portion of the first dielectric material level and a first portion of the second dielectric material level to form a first stepped structure and a second stepped structure in a remaining portion of the first dielectric material level and a remaining portion of the second dielectric material level, wherein the remaining portion of the second dielectric material level includes the conductive contacts under the mask structure; a first dielectric material level and a second dielectric material level; converting an exposed portion of the second dielectric material level not under the mask structure into a converted material different from the second dielectric material level; forming a material stack so that each of the material stacks includes the first dielectric material level and the second dielectric material level under the mask structure and a portion of the converted material; removing the portion of the converted material in the material stack and at least a portion of the second dielectric material level in the material stack; and forming a conductive material in the space where the portion of the converted material in the material stack and at least a portion of the second dielectric material level in the material stack are removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A portion of a schematic diagram of an apparatus in the form of a memory device having a set of data lines is shown in accordance with an embodiment of the invention.

[0009] Figure 2 Demonstrate the present invention according to an embodiment of the Figure 1Schematic diagram of a portion of a memory device of , including an example in which the memory device includes eight data lines in each data line set.

[0010] Figure 3A Demonstrating some embodiments described herein Figure 2 A side view (eg, a cross section relative to the ZY direction) of a structure of a portion of a memory device including Figure 2 The structure of the data line set of the memory device and the structure of the memory cell string.

[0011] Figure 3B Demonstrating some embodiments described herein Figure 3A A top view (eg, a cross section relative to the XY plane) of a portion of a pillar of a memory cell string.

[0012] Figure 3C Demonstrating some embodiments described herein Figure 3A A top view (eg, a cross section relative to the XY plane) of conductive contacts of a column of a memory cell string.

[0013] Figure 4 A top view showing the structure of a memory device according to some embodiments described herein, comprising Figure 2 A data line of a memory device and a conductive contact (eg, a drain contact) of a corresponding memory cell string.

[0014] Figure 5 Demonstrating some embodiments described herein Figure 4 An isometric view of a portion of the structure of a memory device, including a memory cell region and a data line stack of the memory device.

[0015] Figure 6 Demonstrating some embodiments described herein Figure 1 and Figure 2 A top view of the structure of a memory device including a memory cell block and a data line stack of the memory device.

[0016] Figure 7 to Figure 52C Different views of elements during a process of forming a memory device, including forming a data line stack of the memory device, are shown according to some embodiments described herein. DETAILED DESCRIPTION

[0017] The technology described herein includes a memory device with stacked data lines, where the data lines are stacked on top of each other in different levels (vertical levels) of the memory device. The stacked structure of the data lines described herein can increase the density of data lines in a given area. This can allow more memory cells to be coupled to the data lines. This can increase the density of memory cells in a given area of ​​the described memory device. Figure 1 to Figure 52C Other improvements and benefits of the described techniques are discussed.

[0018] Figure 1 A portion of a schematic diagram of an apparatus in the form of a memory device 100 having a set of data lines according to an embodiment of the present invention is shown. The memory device 100 may include a nonvolatile (e.g., a NAND flash memory device) or other type of memory device. Figure 1 As shown, the memory device 100 may include a memory cell region (eg, a memory array region) 101 (which has memory cells 110, 111, 112, and 113) and data lines (data line sets) 1701 to 170 N , data line (data line set) 1711 to 171 N and data line (data line set) 1721 to 172 N Data lines 1701 to 170 N , 1711 to 171 N and 1721 to 172 N Bit lines (eg, local bit lines) of the memory device 100 may be included (or may be a part thereof).

[0019] Memory device 100 may include an equal number of data lines in a set (eg, stack) of data lines. Figure 1 In the figure, the label "N" (the number of data lines in each data line set) can be any integer at least equal to two (N can be equal to two (N=2) or N can be greater than two (N>2)).

[0020] like Figure 1 As shown, data lines 1701 to 170 N The signals (eg, bit line signals) BL01 to BL0 may be respectively carried. N . Data lines 1711 to 171 N can carry signals (eg, bit line signals) BL11 to BL12, respectively. N Data lines 1721 to 172 N can carry signals (eg, bit line signals) BL21 to BL2, respectively. N .

[0021] Figure 1Directions X, Y, and Z are shown that may be relative to physical directions (e.g., dimensions) of the structure of memory device 100. For example, the Z direction may be a direction perpendicular to a substrate (e.g., a semiconductor substrate) of memory device 100 (e.g., a vertical direction relative to the substrate). The Z direction is perpendicular to the X direction and the Y direction (e.g., the Z direction is perpendicular to an XY plane of memory device 100).

[0022] In the physical structure of the memory device 100, data lines 1701 to 170 N , data line 1711 to 171 N and data lines 1721 to 172 N The data lines 1701 to 1702 may be configured as conductive lines and have respective lengths extending in the Y direction. As described in more detail below, the same data line set (eg, data lines 1701 to 1702) may be configured as conductive lines and have respective lengths extending in the Y direction. N ) within the data line (e.g., data lines 1701 to 170 N ) may be formed into a stacked structure. In the stacked structure, the data lines in the same set may be positioned relative to each other (e.g., stacked on each other) in different levels (e.g., layers) in the Z direction above the memory cell region 101 of the memory device 100. For example, in the physical structure of the memory device 100, the data lines 1701 to 170 N , data line 1711 to 171 N and data lines 1721 to 172 N The data lines 1701 to 1702 may be formed in a corresponding stack (eg, a side-by-side stack in the X direction) above the memory cell region 101. N The data lines 1711 to 1712 may be formed as a stack (eg, a first data line stack). N Another stack (eg, a second data line stack adjacent to the first stack) may be formed, and the data lines 1721 to 172 N It can be formed as a stack (eg, a third data line stack adjacent to a second stack).

[0023] Figure 1 The display includes three data line sets (for example, data line sets 1701 to 170 N , data line set 1711 to 171 N and data line set 1721 to 172 N ) is an example of a memory device 100. However, the memory device 100 may include many data line sets.

[0024] like Figure 1 As shown, memory cells 110, 111, 112, and 113 may be organized into blocks (memory cell blocks). Figure 1The memory device 100 including two blocks 191 and 192 is shown as an example. However, the memory device 100 may include many blocks. The blocks (e.g., blocks 191 and 192) of the memory device 100 may share data lines (e.g., data lines 1701 to 1702). N , 1711 to 171 N and 1721 to 172 N ) to carry information (in the form of a signal) read from or to be stored in a memory cell in a selected memory cell of the memory device 100 (eg, a selected memory cell in block 191 or 192).

[0025] like Figure 1 As shown, memory cells 110, 111, 112, and 113 may be included in (e.g., may be formed into) corresponding memory cell strings in each of the blocks (e.g., blocks 191 and 192) of the memory device 100. For example, in block 191, the memory device 100 may include memory cell strings 1301 to 1302. N , memory cell strings 1311 to 131 N and memory cell strings 1321 to 132 N In another example, in block 192, the memory device 100 may include memory cell strings 130'1 to 130' N , memory cell strings 131'1 to 131' N and memory cell strings 132'1 to 132' N .

[0026] In each block (eg, block 191 or 192 ) of the memory device 100 , the number of memory strings in the X direction coupled to the data line set may be equal to the number of data lines (eg, N) in the data line set.

[0027] like Figure 1 As shown, each memory cell string (e.g., memory cell string 1301) of the memory device 100 may have memory cells connected in series (e.g., four memory cells connected in series), wherein the memory cells connected in series may include one of the memory cells 110, one of the memory cells 111, one of the memory cells 112, and one of the memory cells 113. In the physical structure of the memory device 100, the memory cells 110, 111, 112, and 113 may be in different levels (e.g., four different layers) in the Z direction of the memory device 100 and may be connected to the data lines 1701 to 1702. N , 1711 to 171 N and 1721 to 172 NThe stacked structure is formed below (eg, formed vertically). Figure 1 An example of four memory cells in each memory cell string is shown, such as memory cells 110, 111, 112, and 113 in memory cell string 1301. However, the number of memory cells in each memory cell string of memory device 100 may vary.

[0028] like Figure 1 As shown, memory device 100 may include control gates 150, 151, 152, and 153, which may carry corresponding signals WL0, WL1, WL2, and WL3. Control gates 150, 151, 152, and 153 may include (or may be a portion of) access lines (e.g., word lines) of memory device 100. Each of control gates 150, 151, 152, and 153 may be part of a structure (e.g., a level) of conductive material (e.g., a layer of conductive material) located in a single level of memory device 100. Memory device 100 may use signals WL0, WL1, WL2, and WL3 to control access to memory cells 110, 111, 112, and 113 of block 191, respectively, during an operation (e.g., a read, write, or erase operation). For example, during a read operation, the memory device 100 may use the signals WL0, WL1, WL2, and WL3 to control access to the memory cells 110, 111, 112, and 113 of the block 191 to read (e.g., sense) information (e.g., previously stored information) from the memory cells 110, 111, 112, and 113 of the block 191. In another example, during a write operation, the memory device 100 may use the signals WL0, WL1, WL2, and WL3 to control access to the memory cells 110, 111, 112, and 113 of the block 191 to store information in the memory cells 110, 111, 112, and 113 of the block 191.

[0029] Memory device 100 may include similar control gates in block 192. For example, the memory device may include control gates 150', 151', 152', and 153' that may carry corresponding signals WL0', WL1', WL2', and WL3'. Each of control gates 150', 151', 152', and 153' may be part of a structure (e.g., a level) of conductive material (e.g., a conductive material layer) located in a single level of memory device 100. Control gates 150', 151', 152', and 153' may be located in the same level as control gates 150, 151, 152, and 153, respectively. Figure 1As shown, control gates 150', 151', 152' and 153' may be electrically separated from control gates 150, 151, 152 and 153. Thus, an access line including control gates 150, 151, 152 and 153 may be electrically separated from an access line including control gates 150', 151', 152' and 153'.

[0030] The memory device 100 may use the signals WL0′, WL1′, WL2′, and WL3′ to control access to the memory cells 110, 111, 112, and 113 of the block 192, respectively, during an operation (e.g., a read, write, or erase operation). For example, during a read operation, the memory device 100 may use the signals WL0′, WL1′, WL2′, and WL3′ to control access to the memory cells 110, 111, 112, and 113 of the block 192 to read (e.g., sense) information (e.g., previously stored information) from the memory cells 110, 111, 112, and 113 of the block 192. In another example, during a write operation, memory device 100 may control access to memory cells 110 , 111 , 112 , and 113 of block 192 using signals WL0 ′, WL1 ′, WL2 ′, and WL3 ′ to store information in memory cells 110 , 111 , 112 , and 113 of block 192 .

[0031] like Figure 1 As shown, memory cells in different memory cell strings in the same block can share the same control gate (e.g., share the same physical control gate) in the block. For example, in block 191, memory cells 110 can share control gate 150, memory cells 111 can share control gate 151, memory cells 112 can share control gate 152, and memory cells 113 can share control gate 153. In block 192, memory cells 110 can share control gate 150', memory cells 111 can share control gate 151', memory cells 112 can share control gate 152', and memory cells 113 can share control gate 153'.

[0032] Figure 1 Four control gates in each block of memory device 100 (eg, control gates 150, 151, 152, and 153 in block 191) are shown as an example. The number of control gates in each block of memory device 100 may vary (eg, may be greater than four).

[0033] like Figure 1As shown, the memory device 100 may include a line (e.g., a source line or a source plate) 198 that may carry a signal (e.g., a source line signal) SRC. The line 198 may be configured as a conductive line or a conductive plate of the memory device 100. The line 198 may be a common conductive line (e.g., a common source line or a common source plate) of the blocks 191 and 192. The line 198 may be coupled to a ground connection of the memory device 100.

[0034] The memory device 100 may include select gates (eg, drain select gates) 1811 to 181 N and transistors (eg, drain select transistors) 1611 to 161 N . Transistor 1611 can share the same select gate 1811. Transistor 161 N can share the same select gate 181 N . Select gate 1811 to 181 N Can carry signals SGD1 to SGD respectively N .

[0035] Transistor 1611 to 161 N The signals SGD1 to SGD N During a memory operation (eg, a read or write operation) of the memory device 100, the transistors 1611 to 1612 may be turned on. N (For example, by activating the corresponding signals SGD1 to SGD N ) to couple the memory cell strings of block 191 to corresponding data line sets 1701 to 170 N , 1711 to 171 N and 1721 to 172 N . Transistors 1611 to 161 can be turned off N (For example, by deactivating the corresponding signals SGD1 to SGD N ) to connect the memory cell strings of block 191 to the corresponding data line sets 1701 to 170 N , 1711 to 171 N and 1721 to 172 N Decoupling.

[0036] The memory device 100 may include transistors (e.g., source select transistors) 160, each of which may be coupled between the line 198 and the memory cells in the corresponding memory cell string of the block 191. The transistors 160 may share the same select gate (e.g., source select gate) 180 of the memory device 100. The transistors 160 may be controlled (e.g., turned on or off) by the same signal, such as an SGS signal (e.g., source select gate signal) provided on the select gate 180. During a memory operation (e.g., a read or write operation) of the memory device 100, the transistors 160 may be turned on (e.g., by activating the SGS signal) to couple the memory cell string of the block 191 to the line 198. The transistors 160 may be turned off (e.g., by deactivating the SGS signal) to decouple the memory cell string of the block 191 from the line 198.

[0037] The memory device 100 may include similar select gates and transistors in block 192. For example, the memory device 100 may include select gates (eg, drain select gates) 181'1 to 181' N and transistors (eg, drain selection transistors) 161'1 to 161' N The transistors 161'1 can share the same select gate 181'1. The transistors 161' N can share the same selection gate 181' N . Select gates 181'1 to 181' N can carry signals SGD'1 to SGD' respectively N .

[0038] Transistors 161'1 to 161' N The signals SGD'1 to SGD' N During a memory operation (eg, a read or write operation) of the memory device 100, the transistors 161'1 to 161' may be turned on. N (For example, by activating the corresponding signals SGD'1 to SGD' N ) to couple the memory cell strings of block 192 to corresponding data line sets 1701 to 170 N , 1711 to 171 N and 1721 to 172 N . Transistors 161'1 to 161' can be turned off N (For example, by deactivating the corresponding signals SGD'1 to SGD' N ) to connect the memory cell strings of block 192 to the corresponding data line sets 1701 to 170 N , 1711 to 171 N and 1721 to 172N Decoupling.

[0039] The memory device 100 may include transistors (e.g., source select transistors) 160', each of which may be coupled between the line 198 and the memory cells in the corresponding memory cell string of the block 192. The transistors 160' may share the same select gate (e.g., source select gate) 180' of the memory device 100. The transistors 160' may be controlled (e.g., turned on or off) by the same signal, such as the SGS' signal (e.g., source select gate signal) provided on the select gate 180'. During a memory operation (e.g., a read or write operation) of the memory device 100, the transistors 160' may be turned on (e.g., by activating the SGS' signal) to couple the memory cell string of the block 192 to the line 198. The transistors 160' may be turned off (e.g., by deactivating the SGS' signal) to decouple the memory cell string of the block 192 from the line 198.

[0040] The memory device 100 includes other components, which are Figure 1 The example embodiments described herein are not shown in order to avoid obscuring the example embodiments described herein. Figures 2 to 6 1 and 10. Some structures of the memory device 100 are described. At least a portion of the memory device 100 (eg, the memory cell region 101 and the data line sets 1701 to 170 N , 1711 to 171 N and 1721 to 172 N part of) may include references to Figure 7 to Figure 52C Any memory devices described may have similar (or identical) structures.

[0041] Figure 2 Demonstrate the present invention according to an embodiment of the Figure 1 Schematic diagram of a portion of a memory device 100 of FIG. 1 , including an example in which the memory device 100 includes eight data lines (eg, N=8) in each data line set. Figure 1 and Figure 2 In the present invention, similar or identical elements are given the same reference numerals. Figure 2 As shown, the memory device 100 may include a set of eight data lines 1701 to 1708 ( 1701 , 1702 , 1703 , 1704 , 1705 , 1706 , 1707 , and 1708 ), a set of eight data lines 1711 to 1718 , and a set of eight data lines 1721 to 1728 .

[0042] As described above, the number of memory strings in the X direction coupled to the data line set may be equal to the number of data lines in the data line set (eg, N). Figure 2In the example of FIG. 1 , each of blocks 191 and 192 may include eight memory strings in the X direction coupled to a corresponding set of data lines. For example, in block 191, memory device 100 may include eight memory cell strings 1301 to 1308 (1301, 1302, 1303, 1304, 1305, 1306, 1307, and 1308) coupled to data lines 1701 to 1708, respectively; eight memory cell strings 1311 to 1318 coupled to data lines 1711 to 1718, respectively; and eight memory cell strings 1321 to 1328 coupled to data lines 1721 to 1728, respectively.

[0043] In a similar manner, in block 192, the memory device 100 may include eight memory cell strings 130'1 to 130'8 coupled to data lines 1701 to 1708, respectively; eight memory cell strings 131'1 to 131'8 coupled to data lines 1711 to 1718, respectively; and eight memory cell strings 132'1 to 132'8 coupled to data lines 1721 to 1728, respectively.

[0044] like Figure 2 As shown, memory cell strings 1301 to 1308 may be coupled to data lines 1701 to 1708, respectively, through conductive connections 1401 to 1408. Memory cell strings 130'1 to 130'8 may be coupled to data lines 1701 to 1708, respectively, through conductive connections 140'1 to 140'8.

[0045] In similar connection, memory cell strings 1311 to 1318 may be coupled to data lines 1711 to 1718, respectively, through conductive connections 1411 to 1418. Memory cell strings 131'1 to 131'8 may be coupled to data lines 1711 to 1718, respectively, through conductive connections 141'1 to 141'8.

[0046] Memory cell strings 1321 to 1328 may be coupled to data lines 1721 to 1728, respectively, through conductive connections 1421 to 1428. Memory cell strings 132'1 to 132'8 may be coupled to data lines 1721 to 1728, respectively, through conductive connections 142'1 to 142'8.

[0047] The memory cell strings in the X direction in one block (e.g., block 191) can be coupled to a specific set of data lines in the same manner as the memory cell strings in the X direction in another block (e.g., block 191) are coupled to the specific set of data lines. Figure 2As shown, memory cell strings 1301 to 1308 in block 191 may be coupled (e.g., coupled in sequential order) to data lines 1701 to 1708 in the same manner as memory cell strings 130'1 to 130'8 in block 192 are coupled (e.g., coupled in sequential order) to data lines 1701 to 1708. Thus, in the physical structure of memory device 100, conductive connections 1401 to 1408 may have a similar (or identical) structure to conductive connections 1411 to 1418.

[0048] Figure 2 An example connection (e.g., sequential connection) between the memory cell strings in the X direction (e.g., memory cell strings 131'1 to 131'8) and the corresponding data line sets (data lines 1711 to 1718) is shown. However, the connection between the memory cell strings in the X direction and the corresponding data line sets may be different from Figure 2 The example connections shown are sufficient as long as one memory cell string in the X direction can be coupled to a corresponding data line in the data line set. Figure 2 Memory cell strings 1301, 1302, 1303, 1304, 1305, 1306, 1307, and 1308 are shown coupled to data lines 1701, 1702, 1703, 1704, 1705, 1706, 1707, and 1708, respectively. However, memory cell strings 1301-1308 may be coupled in a different manner (e.g., not in Figure 2 1701 to 1708) as long as the memory cell strings 1301 to 1308 and the data lines 1701 to 1708 can be coupled to each other in a one-to-one connection (e.g., the memory cell strings 1301 to 1308 do not share the data lines 1701 to 1708).

[0049] Figure 3A Demonstrating some embodiments described herein Figure 2 A side view (e.g., a cross section relative to the ZY direction) of the structure of a portion of the memory device 100 of the present invention includes the structure of the data lines 1701 to 1708 of the memory device 100 and the structure of the memory cell string 130. For simplicity, the detailed description of the same elements is not repeated from figure to figure. Also for simplicity, cross-sectional lines (e.g., hatching) are omitted from most of the elements shown in the drawings described herein. Some elements of the memory device 100 and other memory devices (e.g., memory device 700) described herein may be omitted from specific figures in the drawings to avoid confusing the description of an element (or multiple elements) described in the specific figure. The sizes (e.g., physical structures) of the elements shown in the drawings described herein are not adjusted to scale.

[0050] exist Figure 3A, the structure of the memory cell string 130 may be the structure of one of the memory cell strings 1301 to 1308 of the block 191 of the memory device 100. The other memory cell strings ( Figure 1 and Figure 2 ) may have a structure similar to (or the same as) that of the memory cell string 130.

[0051] like Figure 3A As shown, the data lines 1701 to 1708 may have respective lengths extending in the Y direction. Each of the data lines 1701 to 1708 may have a thickness in the Z direction (less than the length). The data lines 1701 to 1708 are respectively located in different levels (e.g., layers) 301 to 308 of the memory device 100 (e.g., stacked on top of each other). Figure 3A As shown, the levels 301-308 are located in a portion of the memory device 100 that is located above the memory cell region 101 (with respect to the Z direction). The memory cell region 101 is located above the substrate 390 of the memory device 100. As described above with reference to Figure 1 As depicted, memory cell region 101 is where memory cell strings (one of which is shown as memory cell string 130) of memory device 100 may be formed.

[0052] exist Figure 3A , the conductive structure 314 may be the conductive connectors 1401 to 1408 ( Figure 2 ). Conductive structure 314 may include (e.g., may be formed of) a conductive material (e.g., metal, conductively doped polysilicon, or other conductive material). Conductive structure 314 may have a material structure (e.g., a vertical structure) extending through levels 301 to 308 in the Z direction. Conductive structure 314 may be electrically coupled to (e.g., may contact) one of data lines 1701 to 1708 and electrically separated from (e.g., not in contact with) the rest of data lines 1701 to 1708. For example, as Figure 3A As shown, conductive structure 314 can be electrically coupled to data line 1705 at a portion (eg, bridge) 370 of data line 1705 . Figure 3A A separation (eg, a gap) between the conductive structure 314 and each of the data lines 1701 - 1704 and the data lines 1706 - 1708 (except for the data line 1705 ) is shown to indicate that the conductive structure 314 is electrically separated from the data lines 1701 - 1704 and the data lines 1706 - 1708 .

[0053] Figure 3AConductive structure 314 is shown coupled to data line 1705 as an example. However, conductive structure 314 may be coupled to different ones of data lines 1701 and 1708 as long as conductive structure 314 is electrically coupled to at most one (only one) data line in the set of data lines (e.g., coupled to only one of data lines 1701 to 1708).

[0054] like Figure 3A As shown, the memory cell string 130 may include a pillar (eg, a vertical pillar) 330. The pillar 330 may include (eg, may be formed of) a conductive material (eg, conductively doped polysilicon). Figure 3A As shown, pillar 330 may have a length extending in the Z direction (eg, extending vertically relative to substrate 390). Figure 1 The memory cell strings 130 to 1308 in FIG. 1 may include corresponding pillars, each of which may be similar to (or the same as) pillar 330.

[0055] The memory cell string 130 may include a conductive contact 340, which may be a portion of a pillar 330 of the memory cell string 130. The conductive contact 340 may be formed of a metal or other conductive material. The pillar 330 may include a portion 344. The conductive contact 340 and the portion 344 of the pillar 330 may include the same conductive material or different conductive materials.

[0056] Conductive structure 314 and pillar 330 may be part of a circuit path (eg, a conductive channel of memory cell string 130) between data line 1705 and conductive region 398 (associated with signal SRC). Conductive region 398 may be Figure 1 A portion of a line (e.g., a source line or source plate) 198 in the. Figure 3A In the embodiment, during a memory operation (eg, a read or write operation) of the memory device 100 , a circuit path (eg, a current path) may be formed between the data line 1705 and the conductive region 398 through the conductive structure 314 and the pillar 330 .

[0057] like Figure 3A As shown, the conductive contact 340 can be located on one side (e.g., the drain side) of the memory cell string 130 that is closer to the data line (e.g., the data line 1701 to 1708) than the other side (e.g., the source side close to the conductive region 398). Figure 3A The conductive contact 340 in may be referred to as a drain contact of the memory cell string 130 .

[0058] The substrate 390 of the memory device 100 may include a semiconductor substrate (eg, a silicon-based substrate). For example, the substrate 390 may include a p-type silicon substrate or an n-type silicon substrate. Figure 3A As shown, memory cells 110, 111, 112, and 113 of memory cell string 130 may be positioned in different levels of memory device 100 along corresponding portions of pillar 330 in the Z direction. For example, memory cells 110, 111, 112, and 113 may be located above each other (e.g., formed vertically) in levels 350, 351, 352, and 353, respectively.

[0059] Control gates 150, 151, 152, and 153 may be positioned along respective portions of pillar 330 (in the Z direction) in the same levels (e.g., levels 350, 351, 352, and 353, respectively) as memory cells 110, 111, 112, and 113. Control gates 150, 151, 152, and 153 may include (e.g., may be formed of) a conductive material (e.g., metal, doped polysilicon, other conductive materials).

[0060] exist Figure 3A In the embodiment, the select gate 180 and Figure 1 The select gates 180 shown are identical. Figure 3A The selection gate 181 in the embodiment may be the selection gate 1811 to 181 N ( Figure 1 ) is one of the following. Transistor 161 may be Figure 1 Transistors 1611 to 161 N One of them. Figure 3A As shown, transistors 160 and 161 may be positioned in the Z direction along corresponding portions of pillar 330. The material of select gates 180 and 181 may include a conductive material (eg, conductively doped polysilicon, metal, other conductive materials).

[0061] Memory cell string 130 may include materials 323, 324, 325 located between portion 344 of pillar 330 and corresponding ones of control gates 150, 151, 152, and 153. Material 325 may also be located between pillar 330 and each of select gates 180 and 181. Figure 3A As shown, materials 323, 324, 325 may be separated between memory cells 110, 111, 112, and 113. Materials 323, 324, 325 located at a particular memory cell (of memory cells 110, 111, 112, and 113) may be a portion (e.g., a memory element) of that particular memory cell.

[0062] Material 323 may include a charge blocking material (or multiple charge blocking materials), such as a dielectric material (eg, silicon dioxide) that is capable of blocking the tunneling of charges.

[0063] Material 324 may include a charge storage material (or multiple charge storage materials) that can provide a charge storage function to represent the value of the information stored in memory cells 310, 311, 312, and 313. For example, material 324 may include polysilicon (e.g., conductively doped polysilicon), which may be p-type polysilicon or n-type polysilicon. The polysilicon may be configured to function as a floating gate (e.g., to store charge) in a memory cell (e.g., memory cell 110, 111, 112, or 113). In another example, material 324 may include a dielectric material (e.g., a silicon nitride-based material or other dielectric material) that can trap charge in a memory cell (e.g., memory cell 110, 111, 112, or 113).

[0064] Material 325 may include a tunnel dielectric material (or multiple tunnel dielectric materials), such as silicon oxynitride, which can allow tunneling of charges (eg, electrons).

[0065] like Figure 3A As shown, the memory device 100 may include a circuit system 395 located below (e.g., formed on) the memory cell region 101 (e.g., it is located directly below the memory cell string 130). The circuit system 395 may include a circuit element (e.g., a transistor T) coupled to other circuit elements of the memory device 100 (e.g., coupled to the data lines 1701 to 1708). The circuit element (e.g., transistor T) of the circuit system 395 may be configured to perform a portion of the function of the memory device (e.g., memory device 100). For example, the circuit system 395 may include a decoder circuit, a driver circuit, a buffer, a sense amplifier, a charge pump, and other circuit systems of the memory device 100.

[0066] Figure 3B and Figure 3C Different views of column 330 along lines 3B-3B and 3C-3C are shown, respectively. Figure 3B Portion 344 of column 330 is shown along Figure 3A A top view of line 3B-3B (e.g., a cross section relative to the XY plane). Figure 3C The conductive contacts 340 of the display column 330 are arranged along Figure 3A A top view of line 3C-3C (e.g., a cross section relative to the XY plane).

[0067] like Figure 3BAs shown, portion 344 may include material 344A and material 344B surrounded by material 344A. Material 344A may be (or may include) a portion of a conductive structure (e.g., a conductive path) of pillar 330. Material 344B may include a dielectric material. In an alternative structure of pillar 330, material 344B may be omitted from pillar 330, such that the entire portion 344 of pillar 330 may include material 344A (without material 344B).

[0068] like Figure 3C As shown, the shape of the conductive contact 340 (eg, in a top view) can be relatively circular. Figure 3B , the shape of portion 344 (eg, in a top view) may be relatively circular. Figure 1 and Figure 2 Other conductive contacts (eg, drain contacts) shown in FIG. 4A and 4B may have shapes similar to those of conductive contact 340 (as viewed from a top plan view).

[0069] Figure 4 A top view of the structure of a memory device 100 according to some embodiments described herein is shown, including data lines 1701-1708, 1711-1718, and 1721-1728 of the memory device 100 and conductive contacts (e.g., drain contacts) 3401-3408 of corresponding memory cell strings 1301-1308. The conductive contacts 3401-3408 are located below the corresponding stacks of data lines 1701-1708 (in the Z direction). Figure 4 As shown, data lines 1701 to 1708, data lines 1711 to 1718, and data lines 1721 to 1728 may have a length extending in the Y direction. For simplicity, other conductive contacts (and memory cell strings) associated with data lines 1711 to 1718 and 1721 to 1728 are not labeled. Figure 4 As shown, the shape of each of the conductive contacts 3401 to 3408 (as viewed from a top view) may be similar to Figure 3A , Figure 3B and Figure 3C The conductive contacts 340 of the pillars 330 of the memory cell string 130 in FIG. 3401 to 3408 may be positioned along the length of the stack of data lines 1701 to 1708 (in the Y direction) and on both sides of the stack (in the X direction).

[0070] Figure 4 Also shown are conductive structures 3141-3148 and other conductive structures (not labeled) of memory device 100. Figure 4As shown, the conductive structures 3141 to 3148 may alternatively be formed on respective sides (eg, left and right sides in the X direction) of the stack of data lines 1711 to 1718 .

[0071] Each of the conductive structures (e.g., conductive structures 3141 to 3148) can contact (e.g., be electrically coupled to) a corresponding conductive contact. For example, conductive structure 3141 can contact conductive contact 3401, conductive structure 3142 can contact conductive contact 3402, and so on.

[0072] like Figure 4 As shown, each of the conductive structures (e.g., conductive structures 3141 to 3148) may also contact (e.g., be electrically coupled to) a corresponding data line at a portion (e.g., a bridge) of the corresponding data line in the data line stack. Such a portion may be a protruding portion of the corresponding data line. For example, Figure 5 As shown, the conductive structure 3147 can contact the data line 1707 at the portion 507, which can be a protruding portion (eg, an integral portion) of the data line 1707.

[0073] As mentioned above Figure 2 3, the memory device 100 may have eight data lines (eg, N=8) in each data line set. Figure 4 and Figure 5 As shown, the set of data lines 1701 to 1708 (associated with signals BL01 to BL08) may be formed as a stack of eight data lines that are stacked on top of each other in the Z direction. Figure 4 and Figure 5 As shown, data line 1708 may be the topmost data line, and data lines 1701 to 1707 may be located below data line 1708 (below in the Z direction). Figure 4 , data lines 1701 to 1707 are hidden under data line 1708.

[0074] In a similar fashion, the set of data lines 1711 to 1718 (associated with signals BL11 to BL18) may be formed as a stack of eight data lines stacked one on top of the other in the Z direction. Figure 4 As shown, data line 1718 may be the topmost data line, and data lines 1711 to 1717 (which are hidden below data line 1718 ) may be located below data line 1718 (below in the Z direction).

[0075] The set of data lines 1721 to 1728 (associated with signals BL21 to BL28) may be formed as a stack of eight data lines that are stacked on top of each other in the Z direction. Figure 4 As shown, data line 1728 may be the topmost data line, and data lines 1721 to 1727 (which are hidden below data line 1728 ) may be located below data line 1728 (below in the Z direction).

[0076] Figure 5 Demonstrating some embodiments described herein Figure 4 An isometric view of a portion of the structure of the memory device 100 of FIG. 1 , including the memory cell region 101 and the stack of data lines 1701 to 1708, 1711 to 1718, and 1721 to 1728. Figure 5 As shown, the set of data lines 1701 to 1708 can be formed as a stack of eight data lines. The set of data lines 1711 to 1718 can be formed as another stack of eight data lines (e.g., close to the stack of data lines 1701 to 1708). The set of data lines 1721 to 1728 can be formed as another stack of eight data lines (e.g., close to the stack of data lines 1711 to 1718). The stacks of data lines 1701 to 1708, 1711 to 1718, and 1721 to 1728 can be positioned side by side with each other (in the X direction) and located on the same level of the memory device 100.

[0077] like Figure 5 As shown, each of the data lines 1701 to 1708 may include (e.g., may be formed of) a conductive material structure (e.g., a sheet (e.g., a layer)). Thus, the set of data lines 1701 to 1708 may include eight separate material structures (e.g., sheets) stacked on top of each other above the memory cell region 101. In a similar formation, the set of data lines 1711 to 1718 may be formed as another stack of eight conductive material structures (e.g., sheets (e.g., layers)) (e.g., a stack adjacent to the data lines 1701 to 1708). The set of data lines 1721 to 1728 may be formed as another stack of eight conductive material structures (e.g., sheets (e.g., layers)) (e.g., a stack adjacent to the data lines 1711 to 1718). Example materials for the data lines 1701 to 1708, 1711 to 1718, and 1721 to 1728 include metal, conductively doped polysilicon, or other conductive materials.

[0078] Figure 5Also shown are some conductive contacts (e.g., conductive contacts 3402, 3403, 3406, and 3407) and corresponding conductive structures of the memory device 100 (e.g., conductive structures 3142, 3143, 3146, and 3147) coupled to the conductive contacts. The conductive structures 3142, 3143, 3146, and 3147 and the conductive portion 555 can be parts of the conductive connections 1401, 1403, 1405, 1407, and 1408 of the memory device 100, which are respectively Figure 2 As shown schematically in Figure 5 As shown, conductive structures 3142, 3143, 3146, and 3147 may be located on one side of the stack of data lines 1701 to 1708. Conductive structures 3141, 3144, 3145, and 3148 may be located on the other side of the stack of data lines 1701 to 1708. For simplicity, Figure 5 Conductive contacts and conductive structures associated with the stack of data lines 1711 to 1718 and the stack of data lines 1721 to 1728 are omitted.

[0079] like Figure 5 As shown, conductive structures 3142, 3143, 3146, and 3147 can be coupled to corresponding data lines 1702, 1703, 1706, and 1707 at conductive portions (e.g., bridges) 502, 503, 506, and 507, respectively. Conductive portions 502, 503, 506, and 507 can be parts (e.g., integral parts) of data lines 1702, 1703, 1706, and 1707, respectively. Therefore, the material of conductive portions 502, 503, 506, and 507 can be the same as the material of conductive structures 3142, 3143, 3146, and 3147, respectively. Figure 5 In the embodiment, each of the conductive portions 502, 503, 506 and 507 may be a protruding portion of a corresponding data line, wherein the protruding portion may protrude from one side of the corresponding data line in a direction perpendicular to the length of the corresponding data line (eg, X direction).

[0080] Each of the conductive structures (eg, conductive structures 3142, 3143, 3146, and 3147) may include a portion (eg, a vertical conductive portion) 561 and a portion (eg, a horizontal conductive portion) 562. Figure 5 As shown, portion 561 and portion 562 of a corresponding conductive structure (e.g., conductive structure 3147) can form an L-shape. Portion 555 can extend (in the Z-direction) through portion 562 such that portion 562 can contact and surround at least a portion of conductive portion 555 where conductive portion 555 contacts portion 562.

[0081] In the conductive structure (e.g., conductive structure 3147), portion 561, portion 562, and a portion (one of portions 502, 503, 506, and 507) coupling portion 561 to a corresponding data line (e.g., data line 1707) may have (e.g., may be formed of) the same conductive material (or multiple conductive materials) as the data line. In an example, the materials of portion 561 and portion 562, portion 507, and data line 1707 of conductive structure 3147 may be formed in the same process (e.g., formed in the same material deposition process), so that the materials of portion 561 and portion 562, portion 507, and data line 1707 of conductive structure 3147 have the same conductive material (or multiple conductive materials) as the data line. Fig.51A and Fig.51B The same conductive material (or multiple conductive materials) is formed in a process similar to the process in the above method.

[0082] like Figure 5 As shown, the conductive structures 3142 , 3143 , 3146 , and 3147 may be coupled to the corresponding conductive contacts 3402 , 3403 , 3406 , and 3407 via the conductive portion (vertical portion) 555 .

[0083] like Figure 5 As shown, the memory device 100 can include spacers (eg, vertical dielectric spacers) 345. The spacers 345 can form dielectric structures that electrically separate the corresponding conductive structures 3141-3148 from the stack of data lines 1701-1708.

[0084] As mentioned above Figures 1 to 5 As described, data lines (eg, data lines 1701 to 1708) may be in blocks (eg, Figure 1 and Figure 2 Therefore, Figure 5 The stack of data lines 1701 to 1708 in can extend across (e.g., be formed above) a block of the memory device 100 and can be coupled to corresponding conductive contacts (e.g., drain contacts) of corresponding memory cell strings in each of the blocks.

[0085] Figure 6 A top view of the structure of memory device 100 is shown, including blocks 191 and 192 and a stack of data lines 1701 - 1708 , 1711 - 1718 , and 1721 - 1728 , according to some embodiments described herein. Figure 6 Also shown are the stack of data lines 6701 to 6708 and the conductive contacts (not labeled) along the stack of data lines 6701 to 6708. For simplicity, Figure 6Other data line stacks and conductive contacts between the stack of data lines 1721 to 1728 and the stack of data lines 6701 to 6708 are omitted. Figure 6 Only some conductive structures are marked (e.g., conductive structures 3142, 3143, 3146, 3147, and 3148). Figure 6 As shown, the stack of data lines 1701 to 1708, 1711 to 1718, 1721 to 1728, and 6701 to 6708 may extend in the Y direction across blocks 191 and 192.

[0086] The memory device 100 and other memory devices (eg, as described below) Figure 7 to Figure 52C The stacked structure of the data lines of the memory device 700 described herein allows the memory device described herein to have improvements and benefits over some conventional memory devices. For example, the described stacked data lines (e.g., data lines 1701 to 1708, 1711 to 1718, 1721 to 1728 ( Figures 1 to 6 ) and Figure 7 to Figure 52C The stacking of data lines in a memory device (e.g., memory devices 100 and 700) can increase the density of data lines for a given device area of ​​a memory device (e.g., memory devices 100 and 700). This can allow a given device area to have more memory cells (e.g., more memory cell strings) coupled to the stacked data lines, thereby increasing the memory cell density for a given area of ​​the memory device.

[0087] In addition, some conventional memory devices may have spacing (e.g., horizontal spacing) constraints that limit the number of columns of memory cell strings to be coupled to data lines in such conventional memory devices. Therefore, some memory cell strings in such conventional memory devices may be unused (e.g., wasted). The stacked data lines described herein can remove such constraints and allow a relatively high number of memory cell strings to be coupled to the stacked data lines. This can also increase the memory cell density of a given area of ​​the described memory device compared to some conventional memory devices.

[0088] In addition, some applications may require a relatively high number of memory cells to be included for a particular device area. To accommodate such requirements, the column density (e.g., memory cell string density) of a particular device area of ​​a memory device may be increased. Thus, the number of data lines may also be increased. The stacked data lines described herein may allow the data line density to keep pace with such column density (e.g., memory cell string density), thereby allowing the memory devices described herein to be suitable for such applications.

[0089] Figure 7 to Figure 52CDifferent views of elements during a process of forming a memory device 700 according to some embodiments described herein are shown. Some or all of the processes for forming the memory device 700 may be used to form the memory device 700 described above. Figures 1 to 6 A memory device 100 is described.

[0090] Figure 7 1 to 314'8, which have been formed during some of the processes of forming the memory device 700. The conductive structures 314'1 to 314'8 may correspond to the conductive structures 3141 to 3148 ( Figure 4 ). For simplicity, Figure 7 Labeling of other conductive structures of the memory device 700 (which are similar to the conductive structures 314'1 to 314'8) is omitted.

[0091] Figure 7 Also shown are conductive contacts 7401-7408 (which are coupled to respective conductive structures 314'1-314'8) and other conductive contacts 727, 737, 747, 757, 728, 738, 748, and 758 that have also been formed during some of the processes of forming memory device 700. For simplicity, Figure 7 Omitted Figure 7 Labels for other conductive contacts of memory device 700 are shown.

[0092] Figure 7 Also shown is material 1703 (which is in Fig.17 is formed in Fig.31A and Fig.43A 1703). Each material 1703 may be formed to have a length extending in the Y direction and a width extending in the X direction. Material 1703 may be part of a mask structure. Material 1703 may include other polysilicon materials that may not be affected by processes (e.g., trimming and etching processes) performed on other materials (e.g., silicon dioxide and silicon nitride) during formation of the data line stack of memory device 700.

[0093] Formation and Figure 7 The process of the associated memory device 700 also forms other materials below the material 1703 (in Figure 8 (shown in the). Figure 7 Lines 792A and 792B in show the location of memory device 700, with different views (eg, cross-sections) of memory device 700 being shown in subsequent figures.

[0094] Figure 7Also shown is a location 717 (eg, the area indicated by the dashed rectangle) that may span a portion of the memory device 700. As described below (eg, with reference to Fig. 27 and Fig.28 ), the process of forming the data line stack of the memory device 700 may include forming a resist structure (eg, Fig. 27 and Fig.28 The resist structure 2701 in the embodiment of the present invention is used to cover a portion of the memory device 700 (eg, Figure 7 The resist structure 2701 at the position 717 shown ( Fig.28 ) below. Fig.28 The described process can selectively remove the unoccupied positions 717 ( Figure 7 ) at the resist structure (e.g., Fig.28 Such a process is to form a portion of a stepped structure in the material used to form the data line stack of the memory device 700.

[0095] Figure 8 A portion of memory device 700 (eg, conductive contacts 7405, 728, 738, 748, and 758) is shown after forming conductive contacts of memory device 700. Figure 7 792A in FIG. 79). The conductive contacts 7405 may correspond to Figure 4 Conductive contacts 3405. Figure 8 Also shown is a dielectric material (eg, silicon dioxide) 801 formed over the conductive contacts 7405, 728, 738, 748, and 758. The memory cell strings coupled to the conductive contacts 7405, 728, 738, 748, and 758 are not in Figure 8 Displayed in.

[0096] exist Fig. 9 In the embodiment, a dielectric material (eg, silicon nitride) 903 is formed over the dielectric material 801.

[0097] exist Fig.10 In the embodiment, a dielectric material (eg, silicon dioxide) 1001 is formed over the dielectric material 903.

[0098] exist Fig.11 , a portion of each of the dielectric materials 801 , 903 , and 1001 is removed (eg, patterned and etched) to form an opening (eg, hole) 1110 , thereby exposing the conductive contacts 7405 , 728 , 738 , 748 , and 758 at the corresponding opening 1110 .

[0099] exist Fig.12In the embodiment of the present invention, the dielectric material (eg, silicon nitride) 903 (eg, silicon nitride) is removed (eg, etched) Fig. 9 A cavity (e.g., a groove) 1210 is formed by forming at least a portion of each of the plurality of electrodes (e.g., formed in the cavity).

[0100] exist Fig.13 In the embodiment of the present invention, a material 1304 is formed in the cavity 1210. The material 1304 may be a sacrificial material that will be removed in a subsequent process of forming the memory device 700. In a subsequent process (eg, Fig.48A , Fig.48B , Fig.49A and Fig.49B ), material adjacent to material 1304 (e.g., silicon nitride) is moved (e.g., stripped) without removing material 1304 during such subsequent processes. Thus, material 1304 can be selected so that it can withstand such subsequent processes (e.g., silicon nitride stripping processes). In addition, material 1304 can be selected so that it can be relatively conductive relative to silicon dioxide (e.g., materials 1681 to 1687 (e.g., oxide layers)) and other conductive materials (e.g., Fig.14 The material of the conductive portion 1405 formed in Fig.50A and Fig.50B Examples of material 1304 may include glass (eg, borophosphosilicate glass BPSG), carbon nitride, or other suitable materials.

[0101] exist Fig.14 In the embodiment, the conductive portion 1405 is formed in the opening 1110 (in Fig.11 ) and contact conductive contacts 7405, 728, 738, 748 and 758. Conductive portion 1405 may correspond to Figure 5 The conductive portion 555 of the memory device 100 of FIG. 1405 may include tungsten (W) or a combination (eg, layer) of conductive materials (eg, Ti / TiN / W). Fig.14 The associated process may include a material removal process (eg, a chemical mechanical planarization (CMP) process) for removing a portion (eg, a top portion) of material 1001 and conductive portion 1405 .

[0102] exist Fig.15 In the embodiment, a dielectric material (eg, silicon dioxide) 1501 is formed over the dielectric material 1001 and the conductive portion 1405 .

[0103] exist Fig.16 In the example, materials of different levels (eg, layers) are formed in corresponding levels (eg, layers) of the memory device 700 above the dielectric material 1501. Fig.16The materials of different levels formed by the associated processes include materials 1671 to 1678 and materials 1681 to 1687. Materials 1671 to 1678 may include silicon nitride. Materials 1681 to 1687 may include silicon dioxide. Materials 1671 to 1678 and materials 1681 to 1687 may be layered one material after another in a sequential manner over dielectric material 1501. For example, Fig.16 The process used in may include forming (e.g., depositing) material 1671 over dielectric material 1501, forming material 1681 over material 1671, forming (e.g., depositing) material 1672 over material 1681, forming (e.g., depositing) material 1682 over material 1672, etc., until material 1678 is formed. Materials 1671 to 1678 may be referred to as nitride layers. Materials 1681 to 1687 may be referred to as oxide layers.

[0104] exist Fig.17 In the embodiment of the present invention, dielectric material (eg, silicon dioxide) 1701, material 1703, and dielectric material (eg, silicon dioxide) 1705 are formed. Material 1703 may be a sacrificial material to be removed in a subsequent process of forming memory device 700. Examples of material 1703 include polysilicon.

[0105] exist Fig.18A In the process, a material (eg, pattern) 1801 is formed. The material 1801 can be used in a process (eg, an etching process) for removing a material that is not below the material 1801. Fig.18B yes Fig.18A A top view of a memory device. Fig.18B In, marked as Fig.18A The line is Fig.18A The location of a cross section of memory device 700 is shown.

[0106] exist Fig.19A , a portion of each of dielectric material (eg, silicon dioxide) 1701 , material (eg, polysilicon) 1703 , and dielectric material (eg, silicon dioxide) 1705 are removed from location 1910 to expose material 1678 .

[0107] Fig.19B exhibit Fig.19A A top view of a memory device 700 is shown. Fig.19B In, marked as Fig.19A The line is Fig.19A The location of the cross section of the memory device 700 is shown. Fig.19AIn the embodiment, material (eg, polysilicon) 1705 may be part of a mask structure (eg, a hard mask structure). In a subsequent process (eg, an etching process), materials 1671 to 1678 and materials 1681 to 1687 under the mask structure (eg, under material 1705) are not removed.

[0108] exist Fig. 20A , material (eg, pattern) 1801 is removed. Fig. 20B yes Fig. 20A A top view of a memory device. Fig. 20B In, marked as Fig. 20A The line is Fig. 20A The location of the cross section of the memory device 700 is shown. Fig. 20B In, marked as Fig. 20C The line is Fig. 20C The location of a cross section of memory device 700 is shown.

[0109] exist Fig.21 In the process, a resist structure 2101 is formed. Fig.21 exhibit Fig. 20C Same view of memory device 700.

[0110] In with Figures 22 to 29B In the associated following process, different portions of materials 1671 to 1678 and materials 1681 to 1687 are selectively removed (e.g., removed by using an etching process) in different steps (e.g., different etching processes). When other portions of materials 1671 to 1678 and materials 1681 to 1687 (e.g., portions not under material 1705) are removed, material 1705 ( Fig. 20B ) below (e.g., remain unchanged).

[0111] exist Fig. 22 , a portion of the resist structure 2101 at the location 2210 is removed. A portion of the materials 1671 to 1678 and the materials 1681 to 1687 at the location 2210 are removed (eg, removed using an etching process). Fig. 22 The remaining portion (eg, the first remaining portion) of materials 1671 to 1678 and materials 1681 to 1687 is displayed.

[0112] exist Fig.23 , a portion of the resist structure 2201 at locations 2310A and 2310B is removed (eg, trimmed). A portion of the materials 1671 to 1678 and the materials 1681 to 1687 at locations 2210, 2310A, and 2310B is removed (eg, removed using an etching process). Fig.23The remaining portion (eg, the second remaining portion) of materials 1671 to 1678 and materials 1681 to 1687 is displayed.

[0113] exist Fig.24 , a portion of the resist structure 2201 at locations 2410A and 2410B is removed (e.g., trimmed). A portion of the materials 1671 to 1678 and the materials 1681 to 1687 at locations 2210, 2310A, 2310B, 2410A, and 2410B is removed (e.g., removed using an etching process). Fig.24 The remaining portion (eg, the third remaining portion) of materials 1671 to 1678 and materials 1681 to 1687 is displayed.

[0114] exist Fig.25 , a portion of the resist structure 2201 at locations 2510A and 2510B is removed (e.g., trimmed). A portion of the materials 1671-1678 and the materials 1681-1687 at locations 2210, 2310A, 2310B, 2410A, 2410B, 2510A, and 2510B is removed (e.g., removed using an etching process). Fig.25 The remaining portion (eg, the fourth remaining portion) of materials 1671 to 1678 and materials 1681 to 1687 is displayed.

[0115] exist Fig.26 , remove the resist structure 2101 ( Fig.25 ).

[0116] Fig. 27 The memory device 700 is shown after forming the resist structure 2701. Fig. 27 As shown, resist structure 2701 may be formed over a portion (eg, right portion) of the remaining portion (eg, fourth remaining portion) of materials 1671 to 1678 and materials 1681 to 1687. Fig. 27 In the embodiment, the portion of the memory device 700 below the resist structure 2701 is the portion of the memory device 700 below the resist structure 2701. Figure 7 A portion of the portion at position 717 in. Fig. 27 In Fig.28 The associated process removes portions 2711, 2712, and 2713 (which are not covered by the resist structure 2701). Fig. 27 As shown, each of portions 2711 , 2712 , and 2713 may include one of materials 1671 - 1678 and one of materials 1681 - 1687 .

[0117] exist Fig.28 , remove Fig. 27Portions 2711, 2712, and 2713 in FIG. 2 are removed (eg, by using an etching process). Fig.28 Shown in the removed portions 2711, 2712 and 2713 ( Fig. 27 )after, Fig. 27 A portion of memory device 700 that includes materials 1671-1678 and a remaining portion (e.g., a fifth remaining portion) of materials 1681-1687.

[0118] exist Fig.29A , remove the resist structure 2701 ( Fig.28 ). Fig.29B yes Fig.29A A top view of a memory device 700 is shown. Fig.29B In, marked as Fig.29A The line is Fig.29A The location of a cross section of memory device 700 is shown.

[0119] like Fig.29A As shown, a memory device 700 ( Figures 7 to 29A ) includes forming step structures 2911 and 2912 that are opposite to each other (e.g., the steps of step structure 2211 face the steps of step structure 2912 in the Y direction). The steps of step structure 2911 are at a non-level level with the steps of step structure 2912, so that the top portions of step structure 2911 of the remaining portions of materials 1671 to 1678 exposed at positions 2901, 2903, 2905, 2907, and 2909 (e.g., the tops of the steps) are at a non-level level (in the Z direction) with the top portions of step structure 2912 of the remaining portions of materials 1671 to 1678 exposed at positions 2902, 2904, 2906, and 2908 (e.g., the tops of the steps).

[0120] exist Fig. 30A , materials 3001, 3003, 3005, 3007, and 3009 are formed at corresponding positions 2901, 2903, 2905, 2907, and 2909 of the step structure 2911. Materials 3002, 3004, 3006, and 3008 are formed at corresponding positions 2902, 2904, 2906, and 2908 of the step structure 2912. Fig. 30B yes Fig. 30A A top view of a memory device. Fig. 30B In, marked as Fig. 30A The line is Fig. 30A The location of a cross section of memory device 700 is shown.

[0121] exist Fig. 30AIn the embodiment of the present invention, materials 3001-3009 can include introducing a material (or multiple materials) into the exposed portions of materials 1671-1678 to convert the exposed portions of materials 1671-1678 into a different material (e.g., a converted material). For example, carbon can be introduced (e.g., implanted) into the exposed portions of materials 1671-1678 to form a material including carbon (e.g., silicon carbonitride). Forming materials 3001-3009 can improve the process of forming memory device 700 relative to the process of forming similar devices. For example, forming materials 3001-3009 and associated processes allow for lower process step counts and mostly self-aligned stacked data lines (e.g., Fig.51C 8, data lines 171'1 to 171'8, data lines 172'1 to 172'8, data lines 173'1 to 173'8, and data lines 174'1 to 174'8). Forming materials 3001 to 3009 may allow for a relatively dense interconnection scheme in memory device 700. Forming materials 3001 to 3009 may allow for improved interconnection from data lines to lower conductive contacts (e.g., Fig.52A In addition, forming materials 3001 to 3009 allows for improved (e.g., optimized) spacing of dielectric spacers in stacked data lines, which can result in reduced capacitance and increased metal thickness, thereby reducing resistance to improve associated RC (resistance-capacitance) conditions in memory device 700. Fig. 30B In, marked as Fig.31A , Fig.31B The lines can correspond to Figure 7 Lines 792A and 792B.

[0122] Fig.31A and Fig.31B exhibit Fig. 30B The memory device 700 is respectively arranged along the lines marked Fig.31A , Fig.31B Different views of the line. Fig.31A As shown, it can be seen that material 3005 spans corresponding positions in the X direction on the same level of memory device 700. Fig.31B As shown, material 3003 can be seen spanning corresponding locations in the X direction on the same level of memory device 700.

[0123] exist Fig.32A and Fig.32B In the embodiment, a dielectric material (eg, silicon dioxide) 3201' is formed over the material.

[0124] exist Fig.33A and Fig.33B, forming spacers (dielectric spacers) 3201 and openings (eg, trenches) 3301 to 3306. Forming spacers 3201 and openings 3301 to 3306 may include removing (eg, etching) a portion (eg, a top portion) of dielectric material 3201′ (eg, a portion of the top portion) of dielectric material 3201′. Fig.32A and Fig.32B ) and openings 3301 to 3306 ( Fig.33A and Fig.33B ) at a corresponding portion (eg, a horizontal portion) at a position of ). Dielectric material (eg, silicon dioxide) 3201 ' (at Fig.32A and Fig.32B formed in Fig.33A and Fig.33B The remaining portion (further processed in the process) forms a spacer 3201. The spacer 3201 may correspond to Figure 5 The spacer 345 of the memory device 100 is shown in FIG.

[0125] exist Fig.34A and Fig.34B , forming openings (eg, trenches) 3401 to 3406. Forming openings 3401 to 3406 may include removing (eg, etching) materials 3001 to 3009 and materials 1671 to 1678 and materials 1681 to 1687 in openings 3301 to 3306 ( Fig.33A and Fig.33B ) at the corresponding part of the position. Fig.34A and Fig.34B As shown, openings 3401 - 3406 may include trenches having bottoms located at (eg, formed by) dielectric material 1501 .

[0126] exist Fig.35A and Fig.35B , a portion of the exposed dielectric material 1671 to 1678 at location 3510 at opening 3401 is removed (eg, etched). Fig.35A and Fig.35B As shown, materials 3005 and 3003 are not removed. Similarly, materials 3001, 3002, 3004, and 3006-3009 (not shown) are also not removed. As described above, examples of materials 3001-3009 include silicon carbonitride that is different from dielectric materials (e.g., silicon nitride) 1671-1678 to allow materials 3001-3009 to be removed during the process of removing exposed dielectric materials 1671-1678 ( Fig.35A and Fig.35B ) during the period of time in the memory device 700. However, materials 3001 to 3009 may be materials other than silicon carbonitride, as long as such materials can give etching selectivity and when in contact with Fig.35A and Fig.35BThe dielectric materials (eg, silicon nitride) 1671 to 1678 may be removed without being removed in the associated process.

[0127] exist Fig.36A and Fig.36B In the corresponding position 3510( Fig.35A and Fig.35B ) is formed at a dielectric material (e.g., silicon dioxide) 3601.

[0128] exist Fig.37A and Fig.37B In the embodiment, a material removal process (eg, a stamp etching process) is performed to remove a portion of each of the dielectric materials 1501 , 1001 , and 903 , thereby exposing the material (eg, sacrificial material) 1304 at the openings 3401 to 3406 .

[0129] exist Fig.38A and Fig.38B In the embodiment of the present invention, a spacer (eg, a dielectric spacer) 3803 is formed. The spacer 3803 may include a plurality of openings 3401 to 3406 ( Fig.37A and Fig.37B ) and removing a portion of the dielectric material to form openings 3801 to 3806. The remaining portion of the dielectric material at the openings 3601 to 3606 (eg, Fig.38A and Fig.38B As shown) a spacer 3803 is formed.

[0130] exist Fig.39A and Fig.39B In the embodiment, a resist structure (eg, a resist pattern) 3905 is formed over corresponding portions of the memory device 700. As shown in FIG. Fig.39C yes Fig.39A and Fig.39B A top view of a memory device 700 is shown. Fig.39C In, marked as Fig.39A and Fig.39B The lines are Fig.39A and Fig.39B The location of the cross section of the memory device 700 is shown. Fig.39A , Fig.39B and Fig.39C As shown, some of the spacers (eg, silicon nitride) 3803 are covered by the resist structure 3905. Some other spacers 3803 are exposed (not covered by the resist structure 3905).

[0131] exist Fig.40A and Fig.40B , removing (eg, etching) some of the spacers (eg, silicon nitride) 3803 (which are in Fig.39A , Fig.39B and Fig.39C exposed in the middle). Fig.40C yes Fig.40A and Fig.40B A top view of a memory device 700 is shown. Fig.40C In, marked as Fig.40A and Fig.40B The lines are Fig.40A and Fig.40B The location of a cross section of memory device 700 is shown.

[0132] exist Fig.41A and Fig.41B , remove the resist structure 3905. Fig.41C yes Fig.41A and Fig.41B A top view of a memory device 700 is shown. Fig.41C In, marked as Fig.41A and Fig.41B The lines are Fig.41A and Fig.41B The location of the cross section of the memory device 700 is shown. Fig.41A , 41B and Fig.41C As shown, openings 4101 to 4106 are also formed.

[0133] exist Fig.42A and Fig.42B In the openings 4101 to 4106 (in Fig.41A , 41B and Fig.41C Marked in) and Fig.42A and Fig.42B A dielectric material (eg, silicon dioxide) 4201 is formed over the other materials of the memory device 700 as shown.

[0134] exist Fig.43A and Fig.43B In the embodiment, a portion (eg, the top portion) of the dielectric material 4201 is removed. A process (eg, a CMP process) may also be performed such that the material (eg, the sacrificial material) 1703 is exposed, such as Fig.43A and Fig.43B shown.

[0135] exist Fig.44A and Fig.44B , material 1703 is removed (eg, etched).

[0136] exist Fig.45A and Fig.45B In the removed material 1703 ( Fig.44A and Fig.44B ) is formed in the position of a dielectric material (e.g., silicon dioxide) 4501. Fig.45A and Fig.45BAs shown, a dielectric material 4501 is also formed over the other materials of the memory device 700 .

[0137] exist Fig.46A and Fig.46B , removing a portion (eg, a top portion) of dielectric material 4501 (eg, using a CMP process). Fig.46A and Fig.46B An associated process is performed to expose the spacers (eg, silicon nitride) 3808 .

[0138] exist Fig.47A and Fig.47B , removing (eg, stripping) the spacer (eg, silicon nitride) 3808, leaving an opening (eg, a gap) 4710 ( Fig.47A ) and 4720( Fig.47B ).like Fig.47A and Fig.47B As shown, corresponding portions of materials 3005 and 3003 are exposed at openings 4710 and 4720, respectively. Corresponding portions of material 1304 are also exposed at openings 4710 and 4720, respectively.

[0139] exist Fig.48A and Fig.48B , corresponding portions of materials 3005 and 3003 (exposed at openings 4810 and 4820, respectively) are removed (eg, stripped).

[0140] exist Fig.49A and Fig.49B In the Fig.16 The corresponding portion (formed in ) is removed (e.g., peeled off) from the structure (e.g., stacked structure) 4970. Fig.49A and Fig.49B In the case of materials 3003 and 3005 (and other parts of materials 3001, 3002, 3004 and 3306 to 3009 (in Fig. 30A formed in Fig.49A and Fig.49B 3001 to 3009 (not shown in FIG. 3001 ) may remain in memory device 700 (eg, remain in the final structure of memory device 700). However, in an alternative process, materials 3001 to 3009 (in FIG. 3001 ) may be formed. Fig. 30A ), so that materials 3001 to 3009 can also be removed from the structure of memory device 700. Fig.49A and Fig.49B In an associated alternative process, materials 3001 to 3009 may be removed when respective portions of materials 1671 to 1678 are removed (eg, stripped) from structure (eg, stacked structure) 4970 .

[0141] exist Fig.50A and Fig.50B , removing (e.g., exposing) corresponding portions of material 1304 (in Fig.47A and Fig.47B (marked in).

[0142] exist Fig.51A , Fig.51B and Fig.51C In the embodiment, conductive structures 314'1 to 314'8 are formed. The conductive structures 314'1 to 314'8 are coupled to (eg, electrically contact) corresponding conductive portions 1405. Fig.51C yes Fig.51A and Fig.51B A top view of a memory device. Fig.51C In, marked as Fig.51A and Fig.51B The lines are Fig.51A and Fig.51B The location of a cross section of memory device 700 is shown.

[0143] Each of the conductive structures 314'1 to 314'8 may include a portion (eg, a vertical portion) 5161 and a portion (eg, a horizontal portion) 5162 that may form an L-shape. For simplicity, only some of the portions 5161 and 5162 are labeled. Fig.51A and Fig.51B As shown, the conductive structure 314'5 ( Fig.51A ) and conductive structure 314'3( Fig.51B ) may include a portion (eg, a vertical portion) 5161 and a portion (eg, a horizontal portion) 5162 that may form an L-shape. The portions 5161 and 5162 may correspond to Figure 5 Portions 561 and 562 of the corresponding conductive structures.

[0144] like Fig.51A , Fig.51B and Fig.51C As shown, memory device 700 may include stacks 5170 to 5174. Fig.51C As shown, each of the stacks 5170 to 5174 can include data lines (e.g., eight data lines) stacked on top of each other (in the Z direction). For example, stack 5170 can include data lines (e.g., eight data lines) 170'1 to 170'8 and associated conductive structures 314'1 to 314'8. Other stacks include corresponding data lines 171'1 to 171'8, data lines 172'1 to 172'8, data lines 173'1 to 173'8, and data lines 174'1 to 174'8.

[0145] The conductive structures 314'1 to 314'8 may contact the data lines 170'1 to 170'8 at respective conductive portions 5101, 5102, 5103, 5104, 5105, 5106, 5107, and 5108, which may be protruding portions (e.g., integral portions) of the stacked respective data lines 170'1 to 170'8. For simplicity, only some of the conductive portions 5101 to 5108 are labeled. The conductive portions 5102, 5103, 5106, and 5107 may correspond to Figure 5 Conductive portions 502, 503, 506 and 507.

[0146] Fig.51D An exploded view of a stack 5170 including data lines (eg, eight data lines) 170'1 to 170'8 and associated conductive structures 314'1 to 314'8 and conductive portions 5101 to 5108 and materials 3001 to 3008 is shown. Fig.51D As shown, each of the conductive structures 314'1 to 314'8 may be adjacent to one side (in the X direction) of a level of conductive material of a corresponding data line, the level having a second side (in the X direction) adjacent to a corresponding one of the materials (eg, silicon carbonitride) 3001 to 3008.

[0147] exist Fig.52A and Fig.52B In the embodiment, a dielectric material (e.g., silicon dioxide) 5201 is formed over the stack 5170 to 5174 (in Fig.51A and Fig.51B (marked in). Fig.52C yes Fig.52A and Fig.52B A top view of a memory device. Fig.52C middle, Fig.52A and Fig.52B The marked lines are Fig.52A and Fig.52B The location of a cross section of memory device 700 is shown.

[0148] The process of forming the memory device 700 may include additional processes omitted from the description herein. For example, additional processes may be performed to form interconnections between the data lines and other components of the memory device 700 and to form conductive paths.

[0149] In the above description, memory devices 100 and 700 show conductive contacts (eg, Figure 4 The conductive contacts 3401 to 3408 and Figure 7 B) are located on the data lines (e.g., Figure 4 and Figure 51701 to 1708 in FIG. 1704 . However, the conductive contacts (e.g., Figure 4 conductive contacts 3401 to 3408 in the memory cell string (eg, Figure 4 1 to 1308) or both the conductive contacts and the memory cell strings of the memory device 100 or 700 may be located in a pattern that is not directly below the material of the data line. Figure 4 In the embodiment, the conductive contacts 3402, 3403, 3406 and 3407 may be located at respective locations offset from the center of the material of the data lines 1701 to 1708 (eg, located at the center of the data lines 1701 to 1708). Figure 4 In this example, the conductive contacts 3401, 3404, 3405, and 3408 may be located at respective locations offset from the center of the material of the data lines 1701 to 1708 (e.g., located at the left side of the data lines 1701 to 1708). Figure 4 on the right side in the X direction).

[0150] The description of the apparatus (e.g., memory devices 100 and 700) and methods (e.g., methods of forming memory device 700) is intended to provide a general understanding of the structure of various embodiments and is not intended to provide a complete description of all elements and features of the apparatus that may be used with the structure described herein. The apparatus herein refers to, for example, an apparatus (e.g., memory devices 100 and 700) or a system including the apparatus (e.g., memory devices 100 and 700). Although the stacked structure of the data lines described herein may be included in a memory device (e.g., memory devices 100 and 700), the stacked structure of the data lines described herein may also be included in other semiconductor devices. Example semiconductor devices include processors (e.g., general-purpose processors), application-specific integrated circuits (ASICs), memory controllers, and other semiconductor devices.

[0151] References Figure 1 to Figure 52CAny of the described components may be implemented in a number of ways, including via software simulation. Thus, a portion of each of the apparatus (e.g., memory devices 100 and 700) or memory devices and systems described above may all be characterized herein as "modules" (or "a module"). Such modules may include hardware circuitry, single and / or multi-processor circuits, memory circuits, software program modules and objects, and / or firmware, and combinations thereof, as required and / or appropriate for the particular implementation of the various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware for operating or simulating the operation of the various potential embodiments.

[0152] The memory devices described herein (e.g., memory devices 100 and 700) may be included in devices (e.g., electronic circuit systems), such as high-speed computers, communication and signal processing circuit systems, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multi-layer, multi-chip modules. These devices may further be included as subcomponents within a variety of other devices (e.g., electronic systems) (e.g., televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.).

[0153] References Figure 1 to Figure 52C The described embodiments include devices and methods of forming the devices. One of the devices includes: a conductive contact; a conductive portion formed above the conductive contact; and a data line positioned above the first conductive portion and separated from the first conductive portion by a dielectric material, the data line being formed by corresponding conductive material levels; and a conductive structure located on one side of the conductive material levels. The conductive material levels are stacked on top of each other in a first direction in different levels of the device. The conductive structure includes a first portion and a second portion. The first portion extends in the first direction and is coupled to one of the conductive material levels. The second portion extends in the second direction and is coupled to the conductive portion. Other embodiments including additional devices and methods are described.

[0154] In the detailed description and claims, the term "on..." used with respect to two or more elements (e.g., materials), such as one "on the other," means at least some contact between the elements (e.g., between the materials). The term "above" means that the elements (e.g., materials) are in close proximity, but there may be one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Unless so stated, neither "on..." nor "over..." implies any directionality as used herein.

[0155] In the detailed description and claims, a list of items joined by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0156] In the detailed description and claims, a list of items joined by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (not including B) or only B (not including A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0157] The above description and drawings illustrate some embodiments of the subject matter of the present invention to enable those skilled in the art to practice the embodiments of the subject matter of the present invention. Other embodiments may have structural, logical, electrical, process and other changes. Examples represent possible variations only. Portions and features of some embodiments may be included in those portions and features of other embodiments, or replace those portions and features. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art.

Claims

1. A device comprising: Conductive contacts; a conductive portion formed over the conductive contact; a data line located above the conductive portion and separated from the first conductive portion by a dielectric material, the data line being formed by respective levels of conductive material stacked on top of each other in a first direction in different levels of the device; as well as A conductive structure is located on one side of the conductive material levels, the conductive structure including a first portion and a second portion, the first portion extending in the first direction and coupled to one of the conductive material levels, and the second portion extending in a second direction and coupled to the conductive portion. 2 . The device of claim 1 , wherein the first portion and the second portion of the conductive structure form an L-shape. 3 . The apparatus of claim 1 , wherein the second portion of the conductive structure surrounds at least a portion of the conductive portion.

4. The apparatus of claim 1, wherein the first portion of the conductive structure is adjacent to a first side of the conductive material level, and the conductive material level includes a second side, and wherein a portion of the second side is adjacent to a material including carbon. 5 . The apparatus of claim 1 , wherein the first portion of the conductive structure, the second portion of the conductive structure, and the conductive material level are formed of the same conductive material.

6. The apparatus of claim 1, wherein the first portion, the second portion, and the conductive contact are in electrical contact with a pillar of a memory cell string.

7. A device comprising: a first conductive portion; a second conductive portion; levels of conductive material stacked on top of each other and over the first conductive portion and the second conductive portion; Dielectric material levels interleaved with the conductive material levels in a first direction, the conductive material levels and the dielectric material levels forming a material stack; a first conductive structure located on a first side of the material stack and contacting the first conductive portion, wherein the first conductive structure contacts a first conductive material level of the conductive material levels, and the first conductive structure includes a portion extending in a second direction and contacting the first conductive portion; as well as a second conductive structure located on a second side of the material stack and contacting the second conductive portion, wherein the second conductive structure contacts a second conductive material level in the conductive material levels and includes a portion extending in the second direction and contacting the second conductive portion.

8. The apparatus of claim 7, further comprising: a first conductive post located below the first conductive portion and contacting the first conductive contact; as well as A second conductive pillar is located under the second conductive portion and contacts the second conductive contact.

9. The apparatus of claim 7, wherein the level of conductive material includes a third level of conductive material between the first level of conductive material and the second level of conductive material.

10. The apparatus of claim 7, further comprising a dielectric structure located on the first side of the material stack and separating the first conductive structure from the conductive material levels other than the first conductive material level.

11. The apparatus of claim 10, further comprising an additional dielectric structure located on the second side of the material stack and separating the second conductive structure from the conductive material levels other than the second conductive material level.

12. The apparatus of claim 7, further comprising: a third conductive portion; a fourth conductive portion, wherein the conductive material level is located above the third conductive portion and the fourth conductive portion; a third conductive structure located on the first side of the material stack and contacting the third conductive portion, wherein the third conductive structure contacts a third conductive material level of the conductive material levels, and the third conductive structure includes a portion extending in the second direction and contacting the third conductive portion; as well as A fourth conductive structure is located on the second side of the material stack and contacts the fourth conductive portion, wherein the fourth conductive structure contacts a fourth conductive material level in the conductive material levels, and the fourth conductive structure includes a portion extending in the second direction and contacting the fourth conductive portion.

13. The apparatus of claim 12, wherein the first conductive material level, the second conductive material level, the third conductive material level, and the fourth conductive material level are adjacent to respective silicon carbonitride material levels.

14. A method comprising: forming a first level of dielectric material and a second level of dielectric material interleaved with the first level of dielectric material, the first level of dielectric material and the second level of dielectric material formed over conductive contacts of pillars of a string of memory cells; forming a mask structure over the first dielectric material level and the second dielectric material level; removing a first portion of the first dielectric material level and a first portion of the second dielectric material level to form a first stepped structure and a second stepped structure in a remaining portion of the first dielectric material level and a remaining portion of the second dielectric material level, wherein the remaining portion of the second dielectric material level includes the first dielectric material level and the second dielectric material level below the mask structure; converting exposed portions of the second dielectric material level not beneath the mask structure into a converted material different from the second dielectric material level; forming material stacks such that each of the material stacks includes the first and second dielectric material levels and a portion of the converted material beneath the mask structure; removing the portion of the converted material in the material stack and at least a portion of a second dielectric material level in the material stack; as well as Conductive material is formed in the space where the portion of the converted material in the material stack and at least a portion of the second dielectric material level in the material stack were removed.

15. The method of claim 14, wherein the first dielectric material level comprises silicon dioxide and the second dielectric material level comprises silicon nitride.

16. The method of claim 14, converting the exposed portion of the second dielectric material level comprises introducing carbon into the exposed portion of the second dielectric material level.

17. The method of claim 14, further comprising: An opening is formed adjacent to each of the material stacks prior to forming the conductive material, wherein forming the conductive material includes forming the conductive material in the openings so that the conductive material in the openings contacts the conductive material in the space in which one of the second dielectric material levels in the material stack was removed. The method according to claim 14 , wherein the second stepped structure is opposite to the first stepped structure.

19. The method of claim 14, wherein a top exposed portion of the remaining portion of the second dielectric material level of the first stepped structure is at a non-level level with a top exposed portion of the remaining portion of the second dielectric material level of the second stepped structure.

20. The method of claim 14, wherein the mask structure comprises polysilicon.

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