Semiconductor structure and preparation method thereof, storage device and storage system

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, a storage device and a storage system. The semiconductor structure comprises a first chip which comprises a first peripheral circuit, a second peripheral circuit and a two-dimensional storage array, and the second peripheral circuit is respectively connected with the first peripheral circuit and the two-dimensional storage array; the second chip is located on one side of the first chip in the first direction, and the second chip comprises a three-dimensional storage array connected with the first peripheral circuit. The storage device comprises a plurality of semiconductor structures, the plurality of semiconductor structures are sequentially stacked along a first direction, and first chips of two adjacent semiconductor structures are connected with each other.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular, to semiconductor structures and methods for preparing the same, storage devices, and storage systems. Background Art

[0002] All NAND chips in QLC storage devices share one DRAM chip. The DRAM chip and NAND chip are independently packaged and connected to the control chip through transmission lines.

[0003] At present, how to further improve the performance of QLC storage devices is one of the technical problems that technical personnel in this field need to solve urgently. Summary of the invention

[0004] The semiconductor structure and its manufacturing method, storage device and storage system provided in the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] The semiconductor structure provided according to the first aspect of the present application includes:

[0006] A first chip includes a first peripheral circuit, a second peripheral circuit and a two-dimensional storage array, wherein the second peripheral circuit is connected to the first peripheral circuit and the two-dimensional storage array respectively; and

[0007] The second chip is located at one side of the first chip along the first direction, and the second chip includes a three-dimensional storage array connected to the first peripheral circuit.

[0008] The storage device provided according to the second aspect of the present application comprises a plurality of semiconductor structures as described in the first aspect of the present application, wherein the plurality of semiconductor structures are stacked in sequence along a first direction, and the first chips of two adjacent semiconductor structures are connected to each other.

[0009] A storage system provided according to a third aspect of the present application includes a controller and the storage device described in the second aspect of the present application, wherein the controller is coupled to the storage device and is used to control the storage device to store data.

[0010] The method for preparing a semiconductor structure according to the fourth aspect of the present application includes:

[0011] forming a first chip including a first peripheral circuit, a two-dimensional memory array, and a second peripheral circuit, wherein the second peripheral circuit is connected to the first peripheral circuit and the two-dimensional memory array respectively;

[0012] forming a second chip including a three-dimensional memory array; and

[0013] The first peripheral circuit of the first chip is bonded to the second chip along a first direction.

[0014] The semiconductor structure provided in the embodiment of the present application disassembles the three-dimensional storage array and the first peripheral circuit corresponding to the three-dimensional storage array, integrates the first peripheral circuit, the second peripheral circuit and the two-dimensional storage array with similar process steps on the same chip, i.e., the first chip, and manufactures the three-dimensional storage array on the second chip. Not only can the first peripheral circuit be connected to the three-dimensional storage array to realize the operations such as logic control of the three-dimensional storage array and reading of stored data by the first peripheral circuit, but also the first peripheral circuit, the second peripheral circuit and the two-dimensional storage array are integrated on the same chip, and the second peripheral circuit can be directly contacted and connected with the first peripheral circuit and the two-dimensional storage array respectively, so that the second peripheral circuit can realize the operations such as logic control of the two-dimensional storage array and reading of stored data by the second peripheral circuit, and the data transmission line between the first peripheral circuit and the second peripheral circuit can be omitted, thereby reducing data transmission loss, thereby improving data interaction speed and transmission bandwidth utilization.

[0015] The storage device provided in the embodiments of the present application can reduce the footprint of the entire storage device by stacking multiple semiconductor structures together along a first direction, and can also reduce subsequent packaging costs.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. The drawings are used to better understand the present solution and do not constitute a limitation of the present application. In the drawings:

[0018] Figure 1 is a schematic diagram of an electronic device according to one embodiment of the present application;

[0019] Figure 2 is a schematic top view of a solid state drive according to an embodiment of the present application;

[0020] Figure 3 is a schematic structural diagram of a solid state drive according to an embodiment of the present application;

[0021] Figure 4 is a three-dimensional schematic diagram of a semiconductor structure according to one embodiment of the present application;

[0022] Figure 5 is a three-dimensional schematic diagram of a semiconductor structure according to another embodiment of the present application;

[0023] Figure 6 is a schematic structural diagram of a storage device according to an embodiment of the present application; and

[0024] Figure 7 is a flow chart of a method for preparing a semiconductor structure according to one embodiment of the present application.

[0025] Reference numerals:

[0026] 100. semiconductor structure; 110. first chip; 111. first peripheral circuit;

[0027] 112. second peripheral circuit; 113. two-dimensional storage array; 114. first bonding layer;

[0028] 115. first bonding contact; 120. second chip; 121. three-dimensional storage array;

[0029] 122, second bonding layer; 123, second bonding contact; 200, packaging substrate;

[0030] 300, plastic package; 410, first wire; 420, second wire; 500, solder ball;

[0031] 600, electronic device; 610, host; 620, storage system; 621, control chip;

[0032] 622, cache chip; 623, flash memory chip; 630, solid state drive;

[0033] 631, DRAM chip; 632, NAND chip; 633, circuit board;

[0034] 634. Connector. DETAILED DESCRIPTION

[0035] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature region, but do not represent any limitation on the features, and especially do not represent any order of precedence.

[0037] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0038] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0039] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0040] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0041] In addition, in the present application, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. In addition, in the present application, when "connected" or "coupled" is used, it may indicate direct contact or indirect contact between corresponding parts, unless otherwise clearly defined or inferred from the context.

[0042] Figure 1Schematic diagram of an electronic device 600 of one embodiment of the present application is shown. The electronic device 600 may be, but is not limited to, a mobile phone, a desktop computer, a tablet computer, a laptop computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or other devices with a memory. Figure 1 As shown, the electronic device 600 includes a host 610 and a storage system 620. The host 610 may be a processor of the electronic device 600, such as a central processing unit (CPU) or a system-on-a-Chip (SoC). The storage system 620 includes a plurality of storage chips and a control chip 621. The control chip 621 is coupled to the storage chip and the host 610. The host 610 is configured to send data to the storage chip or receive data from the storage chip. The control chip 621 is configured to manage the data stored in the storage chip and communicate with the host 610. Among them, at least one storage chip among the plurality of storage chips may be a cache chip 622, and at least one storage chip may be a flash memory chip 623. Among them, the control chip 621 may be designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In addition, the control chip 621 can also be designed to operate in a high duty cycle environment SSD (Solid State Drives) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptops, and enterprise storage arrays. Figure 2 and Figure 3 As shown, the control chip 621, the cache chip 622 and the flash memory chip 623 are integrated on the circuit board 633 of the SSD. The control chip 621 is used to reasonably allocate the load of data on each flash memory chip 623 and transfer all data. The cache chip 622 is used to assist the control chip 621 in data processing, and the flash memory chip 623 is used to store data. Among them, the cache chip 622 generally adopts a dynamic random access memory chip (Dynamic Random Access Memory, DRAM), and the flash memory chip 623 generally adopts a NAND chip 632. In addition, the SSD may also include a connector 634 that couples the SSD with the host 610.

[0043] like Figure 3As shown, the control chip 621, DRAM chip 631 and NAND chip 632 are each independently packaged and connected to the circuit board 633 of the SSD through solder balls, and the DRAM chip 631 and the NAND chip 632 are connected to the control chip 621 through the transmission line of the circuit board 633. This connection method makes it impossible for the DRAM chip 631 and the NAND chip 632 to directly transmit data, and the data transmission path between the DRAM chip 631 and the NAND chip 632 is too long, resulting in a large data transmission delay, which affects the utilization of the transmission bandwidth, resulting in a limited data exchange speed, and thus causing the performance of the SSD to be unable to be fully utilized.

[0044] Based on this, in order to solve at least some of the above problems, such as Figures 4 to 6 As shown, an embodiment of the present application provides a semiconductor structure 100, which includes a first chip 110 and a second chip 120 located on one side of the first chip 110 along a first direction (z direction), the first chip 110 includes a first peripheral circuit 111, a second peripheral circuit 112 and a two-dimensional storage array 113, the second peripheral circuit 112 is respectively connected to the first peripheral circuit 111 and the two-dimensional storage array 113, and the second chip 120 includes a three-dimensional storage array 121 connected to the first peripheral circuit 111.

[0045] Since the first peripheral circuit 111 and the second peripheral circuit 112 are both peripheral circuits, and their process technology is usually similar, the first peripheral circuit 111 and the second peripheral circuit 112 can be formed on the same chip. The process technology of the two-dimensional memory array 113 and the three-dimensional memory array 121 is quite different, and it is difficult to form them on the same chip, but the two-dimensional memory array 113 is usually a multi-layer film structure, and its process technology is compatible with the process technology of the peripheral circuit. Based on this, in the embodiment of the present application, the three-dimensional storage array 121 and the first peripheral circuit 111 corresponding to the three-dimensional storage array 121 are disassembled, and the first peripheral circuit 111, the second peripheral circuit 112 and the two-dimensional storage array 113 with similar process steps are integrated on the same chip, namely, the first chip 110, and the three-dimensional storage array 121 is manufactured on the second chip 120. Not only can the first peripheral circuit 111 be connected to the three-dimensional storage array 121 to realize the operations such as logic control of the three-dimensional storage array 121 and reading of stored data by the first peripheral circuit 111, but also the first peripheral circuit 111, the second peripheral circuit 112 and the two-dimensional storage array 113 are integrated on the same chip, and the second peripheral circuit 112 can be directly contacted and connected with the first peripheral circuit 111 and the two-dimensional storage array 113 respectively, so that the second peripheral circuit 112 can realize the operations such as logic control of the two-dimensional storage array 113 and reading of stored data by the two-dimensional storage array 113, and the data transmission line between the first peripheral circuit 111 and the second peripheral circuit 112 can be omitted, thereby reducing data transmission loss, thereby improving data interaction speed and transmission bandwidth utilization.

[0046] In addition, in the related art, QLC storage devices require two-step writing, and the data during this period is usually stored in DRAM chips. Although DRAM chips have a fast writing speed, they consume a lot of power, and DRAM chips are volatile storage chips, and power failure cannot protect data, which not only increases the power consumption of QLC storage devices, but also increases the design difficulty, complexity and cost in order to increase power failure protection. In the related art, a hybrid mode of SLC+QLC is usually used for control. Although the hybrid mode can give full play to the high-speed read and write performance advantages of the SLC mode and obtain the high storage capacity of the QLC mode, it will also cause a significant reduction in bandwidth, and requires software and hardware to work together, which is difficult to implement. In order to solve the above problems, the two-dimensional storage array 113 in the embodiment of the present application can adopt a non-volatile storage array. For example, the two-dimensional storage array 113 may include a magnetic random access storage array, i.e., an MRAM storage array, a resistive random access storage array, i.e., an RRAM storage array, or a phase change random access storage array, i.e., a PRAM storage array. In addition, the three-dimensional storage array 121 in the embodiment of the present application may also be a non-volatile storage array, and the three-dimensional storage array 121 includes a three-dimensional NAND storage array, a PROM (Programmable Read-Only memory) storage array or a NOR storage array. The embodiment of the present application replaces DRAM with a non-volatile two-dimensional storage array 113, which not only reduces power consumption and improves the performance of the semiconductor structure 100, but also eliminates the design of power-off protection, reduces the number of capacitors, and reduces costs. Compared with the hybrid mode of SLC+QLC, the embodiment of the present application can reduce the NVB requirement from 1.12 to 1.03, while improving the write performance of the semiconductor structure 100 from 3060MB / s to 3600MB / s.

[0047] like Figure 4 and Figure 5 As shown, the first chip 110 is bonded to the second chip 120. The first chip 110 can be directly bonded to the second chip 120, or can be bonded based on a bonding layer. Compared with other methods, the direct bonding method can make the first chip 110 and the second chip 120 have a lower degree of deformation, a smaller connection spacing and less residual stress. Figure 5As shown, below, taking bonding based on bonding layer as an example, the first peripheral circuit 111, the second peripheral circuit 112 and the two-dimensional storage array 113 are integrated on the same chip, namely the first chip 110, and the second peripheral circuit 112 can be directly contacted and connected with the first peripheral circuit 111 and the two-dimensional storage array 113 respectively. The first chip 110 also includes a first interconnection structure (not shown) connected to the first peripheral circuit 111, and a first bonding layer 114 is formed on the side of the first chip 110 facing the second chip 120, and a first bonding contact 115 penetrating the first bonding layer 114 is formed in the first bonding layer 114, and the first bonding contact 115 is connected to the first interconnection structure. The second chip 120 also includes a second interconnection structure (not shown) connected to the three-dimensional storage array 121, and a second bonding layer 122 is formed on the side of the second chip 120 facing the first chip 110, and a second bonding contact 123 penetrating the second bonding layer 122 is formed in the second bonding layer 122, and the second bonding contact 123 is connected to the second interconnection structure. Among them, the materials of the first bonding layer 114 and the second bonding layer 122 may include but are not limited to insulating materials such as silicon oxide, silicon nitride and / or silicon oxynitride, the materials of the first bonding contact 115, the second bonding contact 123, the first interconnection structure and the second interconnection structure may include but are not limited to at least one of tungsten, cobalt, copper, aluminum and silicide, and the first interconnection structure and the second interconnection structure may include but are not limited to a vertical wire bonding structure and a TSV (Through Silicon Via, conductive through-silicon via) structure. In practical applications, the shape, material and preparation process of the first interconnection structure and the second interconnection structure can be determined according to the requirements of the semiconductor structure 100. As an example, the first bonding layer 114 can be connected to the second bonding layer 122 by an Xtacking bonding process. Among them, the Xtacking bonding process refers to the alignment bonding of the bonding structures between different devices in the same process step, thereby realizing the electrical connection of the two devices. After the first bonding layer 114 and the second bonding layer 122 are connected, the first bonding surface of the first bonding layer 114 overlaps with the second bonding surface of the second bonding layer 122, and the first bonding contact 115 contacts the second bonding contact 123. The first bonding surface is the surface of the first bonding layer 114 away from the first chip 110, and the second bonding surface is the surface of the second bonding layer 122 away from the second chip 120.

[0048] As an example, the three-dimensional storage array 121 may be a NAND storage array, the two-dimensional storage array 113 may be an MRAM storage array, the first peripheral circuit 111 may be a NAND CMOS, and the second peripheral circuit 112 may be an MRAM CMOS. Since the NAND CMOS, the MRAM CMOS, and the MRAM storage array may be integrated on the same chip, i.e., the first chip 110, the MRAM CMOS may be directly connected to the NAND CMOS and the MRAM storage array, respectively. The second chip 120 may realize the connection between the NAND storage array and the NAND CMOS by bonding with the first chip 110. It can be seen that the embodiment of the present application splits the traditional NAND chip and the MRAM chip, and makes the NAND CMOS, MRAM CMOS and MRAM storage array with similar process on the same chip, namely the first chip 110, and makes the NAND storage array with a large difference in process from the above structure on the second chip 120. Not only can the connection between the NAND storage array and the NAND CMOS be realized through the bonding of the first chip 110 and the second chip 120, but also the direct communication of data between the MRAM CMOS and the NAND CMOS can be realized through the direct connection between the MRAM CMOS and the NAND CMOS, thereby eliminating the data transmission line between the MRAM CMOS and the NAND CMOS, shortening the data transmission path between the MRAM and the NAND, reducing data delay, and reducing data transmission loss. In addition, compared with volatile storage arrays such as DRAM storage arrays, the MRAM storage array is a non-volatile storage array, which can not only reduce power consumption and improve the performance of the semiconductor structure 100, but also eliminate the design of power-off protection, reduce the number of capacitors, and reduce costs. In addition, compared with the prior art in which the MRAM chip and the NAND chip are packaged separately, the first chip 110 and the second chip 120 are bonded together in the embodiment of the present application, which can reduce the occupied area of ​​the entire semiconductor structure 100 and improve the integration.

[0049] like Figure 4As shown, on a plane perpendicular to the first direction (z direction), the projection of the first chip 110 falls into the projection of the second chip 120. In other words, the area of ​​the second chip 120 is not less than the area of ​​the first chip 110. The first peripheral circuit 111 and the second peripheral circuit 112 are arranged in sequence along the second direction (x direction) perpendicular to the first direction. The two-dimensional storage array 113 can be located on one side of the second peripheral circuit 112 along the first direction (z direction), or can be located on one side of the second peripheral circuit 112 along the second direction (x direction). Compared with the latter, the former can further reduce the occupied area of ​​the semiconductor structure 100 and improve the integration. For example, the two-dimensional storage array 113 is located on the side of the second peripheral circuit 112 away from the second chip 120. For another example, along the second direction, the second peripheral circuit 112 is located between the first peripheral circuit 111 and the two-dimensional storage array 113. Among them, the first peripheral circuit 111 and the second peripheral circuit 112 can include but are not limited to at least one of a high-voltage device, a low-voltage device and an ultra-low-voltage device. The high voltage device may include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver; the low voltage device may include, but is not limited to, a page buffer or a logic device; and the ultra low voltage device may include, but is not limited to, an I / O circuit. The operating voltage of the high voltage device is generally greater than 3.3V, such as 5V to 30V. As an example, the operating voltage of the high voltage device may be 5V, 10V, 15V, 20V, 25V, or 30V; the operating voltage of the low voltage device is generally between 1.3V and 3.3V. As an example, the operating voltage of the low voltage device may be 1.3V, 1.8V, 2.3V, 2.8V, or 3.3V; the operating voltage of the ultra low voltage device is generally lower than 1.3V, such as 0.9V to 1.2V; as an example, the operating voltage of the ultra low voltage device may be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, or 1.2V. It should be noted that the operating voltage of the high-voltage device, the low-voltage device or the ultra-low-voltage device may also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage range of the high-voltage device, the low-voltage device and the ultra-low-voltage device above is for a better understanding of the present solution and does not constitute a limitation on the present application.

[0050] In some embodiments, the three-dimensional storage array 121 may be a NAND storage array, and the three-dimensional storage array 121 may include a stacking structure and a plurality of channel structures that penetrate the stacking structure along a first direction (z direction), and the stacking structure includes a connection area and a core area formed with a plurality of channel structures, and the connection area is located at least on one side of the core area along a second direction. Among them, the connection area may be a step structure or a non-step structure. For example, under the SCT (Staircase Contact, step area contact) architecture, the connection area does not need to be in a step shape. The stacking structure includes gate layers and insulating layers that are alternately stacked along the stacking direction, that is, the first direction. The gate layers and insulating layers may be arranged in pairs or may be arranged in non-pairs. As an example, the stacking structure may include, but is not limited to, 64 pairs, 128 pairs, or more than 128 pairs of gate layers and insulating layers, which is not limited in this application. The higher the number of stacked layers of the gate layers and insulating layers, the higher the integration of the three-dimensional storage array 121. In other words, the unit storage density of the three-dimensional storage array 121 is higher. The channel structure includes a functional layer and a channel layer, and both the functional layer and the channel layer can be formed by a thin film deposition process, and the thin film deposition process can be but not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. Further, the functional layer may include a blocking layer, a charge capture layer, and a tunneling layer arranged in sequence along the second direction (x direction). Among them, the material of the blocking layer and the tunneling layer may be but not limited to silicon oxide, and the material of the charge capture layer may be but not limited to silicon nitride. In other words, the functional layer may have an ONO structure. Among them, the material of the channel layer may be but not limited to semiconductor materials such as amorphous silicon, polycrystalline silicon or single crystal silicon.

[0051] Among them, the functional layer of the channel structure and the portion of the channel layer corresponding to the gate layer of the stacked structure and a portion of the gate layer together constitute a storage unit, and multiple storage units are connected in series along the stacking direction of the stacked structure, that is, the first direction (z direction) to form a storage string, and the storage units located in the same row, that is, distributed along the second direction, can be connected to the same word line, and the remaining portion of the gate layer can be used as the word line of multiple storage units in the corresponding storage string, and each storage string, that is, the storage units in the same column, can be connected to the same bit line. Under the voltage control of the corresponding word line, the carriers in the channel layer of the storage unit enter the charge capture layer of the functional layer, or the carriers in the charge capture layer of the functional layer retreat to the channel layer, thereby realizing the programming or erasing of the storage unit. In the case where the first peripheral circuit 111 includes a page buffer, a word line driver, and an I / O circuit, the page buffer is connected to the bit line to apply a bit line voltage to the bit line, and the bit line voltage corresponds to the data DATA to be programmed, and the data DATA may include multi-bit data. In a read operation, the page buffer can sense the data DATA stored in the selected storage unit through the bit line, and output the sensed data DATA to the I / O circuit. The word line driver is connected to the word line through the word line contact to apply a word line voltage to the word line, thereby performing an erase operation on the memory cell corresponding to the word line.

[0052] In some embodiments, the two-dimensional storage array 113 may be an MRAM storage array, and the two-dimensional storage array 113 may include a metal layer, a free layer, a barrier layer, and a reference layer stacked in sequence along a first direction (z direction), and the reference layer, the barrier layer, and the free layer constitute a magnetic tunnel junction (MTJ), and the resistance of the MTJ may depend on the magnetization state of the reference layer and the free layer. When the magnetization states of the reference layer and the free layer are parallel, in other words, when the magnetization directions of the two are the same, the resistance of the MTJ is relatively low; when the magnetization states of the reference layer and the free layer are antiparallel, in other words, when the magnetization directions of the two are opposite, the resistance of the MTJ is relatively high. The MTJ in a low resistance state may indicate data "1", and in a high resistance state may indicate data "0". Among them, the barrier layer may include a non-magnetic or weakly magnetic electrically insulating material, the free layer and the reference layer may include a ferromagnetic material, the magnetization direction of the reference layer may be fixed, and the magnetization direction of the free layer may be switched under the influence of external factors such as a current flowing in the metal layer. When the current flows through the metal layer in the second direction, the metal layer generates a corresponding spin current, which accumulates at the boundary of the metal layer. The free layer is in contact with the metal layer, so under the action of spin-orbit, the magnetization state of the free layer is affected by the spin current at the interface of the metal layer, and the direction of the spin current depends on the direction of the current flowing through the metal layer.

[0053] In some embodiments, the first peripheral circuit 111 or the second peripheral circuit 112 includes at least one of a high voltage device, a low voltage device, and an ultra-low voltage device. Further, the high voltage device, the low voltage device, and the ultra-low voltage device may include, but are not limited to, at least one of a transistor, a diode, a resistor, an inductor, and a capacitor. As an example, the first peripheral circuit 111 or the second peripheral circuit 112 includes a substrate and a transistor and a trench isolation structure at least partially located in the substrate, the trench isolation structure surrounds the active area of ​​the transistor, and the trench isolation structure can achieve electrical isolation between the transistor and other devices. The transistor may include a source, a drain, and a gate structure, the source and the drain are formed in the substrate, the gate structure is located on one side of the substrate and is arranged between the drain and the source, the gate structure includes a gate insulating layer and a gate conductive layer, and the gate conductive layer is located on the side of the gate insulating layer away from the substrate. If the transistor is an N-type transistor, N-type dopants such as phosphorus (P), arsenic (As) and antimony (Sb) can be used to form a drain and a source in the substrate; if the transistor is a P-type transistor, P-type dopants such as boron (B) are used to form a drain and a source in the substrate. Wherein, the material of the gate insulating layer includes insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, and the material of the gate conductive layer includes polysilicon, a conductive metal or a conductive alloy. As an example, the material of the gate conductive layer includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). Wherein, the gate insulating layer and the gate conductive layer can be formed on one side of the substrate by a thin film deposition process. In addition, the trench isolation structure can be formed in the substrate by an etching process and a filling process. For example, a dry etching process, a combination of dry and wet etching processes, or a patterning process can be used to form a trench on one side of the substrate, and then a thin film deposition process can be used to deposit an insulating material on one side of the substrate to fill the trench. Among them, the insulating material can be but not limited to silicon dioxide, silicon nitride or silicon oxynitride. Since the insulating material will cover one side of the substrate during the actual deposition process, after the deposition process is completed, the chemical mechanical polishing (CMP) process can be used to remove the insulating material covering other areas of the substrate outside the groove. Among them, the substrate can be a single-layer structure or a multi-layer structure. For example, the substrate is a single-layer structure prepared from semiconductor materials. Among them, the semiconductor material can be but not limited to single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or gallium arsenide and other III-V compounds. For another example, the substrate is a multi-layer structure and at least two layers are made of different materials, and the substrate can be prepared by a thin film deposition process.Among them, the above-mentioned thin film deposition process can be but is not limited to a physical vapor deposition (Physical Vapor Deposition, referred to as PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) process, an atomic layer deposition (Atomic Layer Deposition, referred to as ALD) process or a combination of any of the above processes.

[0054] like Figure 7 As shown, the embodiment of the present application also provides a method 1000 for preparing a semiconductor structure, the method comprising:

[0055] S100, forming a first chip 110 including a first peripheral circuit 111, a two-dimensional storage array 113, and a second peripheral circuit 112, wherein the second peripheral circuit 112 is connected to the first peripheral circuit 111 and the two-dimensional storage array 113 respectively;

[0056] S200, forming a second chip 120 including a three-dimensional memory array 121;

[0057] S300 , bonding the first peripheral circuit 111 of the first chip 110 and the second chip 120 along a first direction, so that the first peripheral circuit 111 is connected to the three-dimensional memory array 121 .

[0058] It should be noted that step S100 and step S200 may be executed in parallel, sequentially, or in any other order, and this application does not limit this.

[0059] In some embodiments, step S100 may include: forming a first peripheral circuit 111; forming a second peripheral circuit 112 on one side of the first peripheral circuit 111 along a second direction, the second direction being perpendicular to the first direction; and forming a two-dimensional storage array 113 on one side of the second peripheral circuit 112 along the first direction. As an example, forming the first peripheral circuit 111 may include: forming a plurality of transistors on a substrate, at least part of the transistors being located in the substrate; forming a plurality of trench isolation structures surrounding active regions of the transistors on the substrate; forming a first interconnect layer on the substrate, the first interconnect layer covering a side of the substrate where the transistors are formed and a side of the transistors away from the substrate; forming a first interconnect structure penetrating the first interconnect layer in the first interconnect layer, the first interconnect structure being connected to the transistors of the first peripheral circuit 111.

[0060] In some embodiments, the transistors of the first peripheral circuit 111 and / or the second peripheral circuit 112 may be formed by the following steps: forming a well region in the substrate; for example, if the transistor is an N-type transistor, an ion implantation or diffusion process may be used to form a P-type doped well, i.e., a P-well, in the substrate, and the dopant may be a P-type dopant with a relatively low concentration, such as boron (B); if the transistor is a P-type transistor, an ion implantation or diffusion process may be used to form an N-type doped well, i.e., an N-well, in the substrate, and the dopant may be a N-type dopant with a relatively low concentration, such as phosphorus (P), arsenic (As), and antimony (Sb). Forming a drain and a source in the well region, for example, if the transistor is an N-type transistor, an N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb) may be used to form the source and the drain in the substrate; if the transistor is a P-type transistor, an P-type dopant such as boron (B) may be used to form the source and the drain in the substrate. A gate structure including a gate insulating layer and a gate conductive layer is formed on one side of the substrate. For example, a gate insulating layer can be formed on one side of the substrate by a thin film deposition process, and a portion of the gate insulating layer is removed by an etching process so that the remaining gate insulating layer is located between the source and the drain; a gate conductive layer is formed on the side of the gate insulating layer facing away from the substrate by a thin film deposition process, and a portion of the gate conductive layer is removed by an etching process so that the remaining gate conductive layer is located between the source and the drain and covers the gate insulating layer. Wherein, the material of the gate insulating layer includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide, and the material of the gate conductive layer includes polysilicon, conductive metal or conductive alloy. As an example, the material of the gate conductive layer includes at least one of tungsten (W), titanium nitride (TiN), copper (Cu) and silver (Ag). It should be noted that the source and drain of the above-mentioned transistor can also be directly formed in the substrate. In other words, the above steps may not include the step of forming a well region.

[0061] In some embodiments, step S200 may include: forming a stacked structure, the stacked structure including an insulating layer and a sacrificial layer stacked in sequence along a first direction; forming a channel structure penetrating the stacked structure in the stacked structure; replacing the sacrificial layer of the stacked structure with a gate layer to form a stacked structure; forming a second interconnect layer on one side of the stacked structure; forming a second interconnect structure penetrating the second interconnect layer in the second interconnect layer, the second interconnect structure being connected to the gate layer of the stacked structure.

[0062] In addition, if Figure 6As shown, the embodiment of the present application further provides a storage device, which includes a plurality of the above-mentioned semiconductor structures 100, wherein the plurality of semiconductor structures 100 are stacked in sequence along a first direction (z direction), and the first chips 110 of two adjacent semiconductor structures 100 are connected to each other. By stacking the plurality of semiconductor structures 100 together along the first direction, the embodiment of the present application can reduce the footprint of the entire storage device, and can also reduce the subsequent packaging cost.

[0063] In some embodiments, the storage device may further include a packaging substrate 200 and a plastic package 300, wherein the plastic package 300 packages the plurality of semiconductor structures 100 on the packaging substrate 200, and the first peripheral circuit 111 closest to the packaging substrate 200 is connected to the packaging substrate 200 via a second wire 420. The material of the plastic package 300 may include at least one of polyimide, silica gel, and EMC (Epoxy Molding Compound), and the material of the second wire 420 may include, but is not limited to, at least one of gold, silver, and copper.

[0064] In order to facilitate the connection of adjacent first peripheral circuits 111, two adjacent semiconductor structures 100 are staggered in sequence along a second direction (x direction) perpendicular to the first direction. In other words, on a plane perpendicular to the first direction, the projections of the two adjacent semiconductor structures 100 partially overlap to expose a portion of the first peripheral circuit 111 of one of the semiconductor structures 100. The first peripheral circuits 111 of the two adjacent semiconductor structures 100 are connected via the first wire 410. As an example, Figure 6 As shown, the first chip 110 of the semiconductor structure 100 is farther away from the packaging substrate 200 in the first direction than the second chip 120, and the two adjacent semiconductor structures 100 are staggered in sequence along the second direction so that part of the first peripheral circuit 111 of the two adjacent first chips 110 that is relatively close to the packaging substrate 200 is exposed, and the exposed parts of the two adjacent first peripheral circuits 111 are connected by a first wire 410, and the material of the first wire 410 can be but is not limited to at least one of gold, silver and copper.

[0065] In addition, an embodiment of the present application further provides a storage system, which includes a controller and the above-mentioned storage device, wherein the controller is coupled to the storage device and is used to control the storage device to store data.

[0066] In some embodiments, the storage system further includes a circuit board, the controller and the storage device electrical connection structure are connected to the circuit board, the controller and the storage device are placed on the circuit board, and the electrical connection structure is located between the circuit board and the controller and the storage device. The electrical connection structure may be, but is not limited to, at least one of a solder ball 500, a metal bump, and a conductive adhesive.

[0067] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. As an example, the steps recorded in the disclosure of the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present application can be achieved, and this document does not limit this.

[0068] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of this application should be included in the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that: include: A first chip includes a first peripheral circuit, a second peripheral circuit and a two-dimensional storage array, wherein the second peripheral circuit is connected to the first peripheral circuit and the two-dimensional storage array respectively; as well as The second chip is located at one side of the first chip along the first direction, and the second chip includes a three-dimensional storage array connected to the first peripheral circuit.

2. The semiconductor structure according to claim 1, wherein: The first peripheral circuit and the second peripheral circuit are sequentially arranged along a second direction perpendicular to the first direction.

3. The semiconductor structure according to claim 1, wherein: The two-dimensional memory array is located at one side of the second peripheral circuit along the first direction.

4. The semiconductor structure according to claim 3, wherein: The two-dimensional storage array is located at a side of the second peripheral circuit away from the second chip.

5. The semiconductor structure according to any one of claims 1 to 4, wherein: Both the two-dimensional storage array and the three-dimensional storage array are non-volatile storage arrays.

6. The semiconductor structure according to claim 5, wherein: The two-dimensional storage array includes a magnetic random access storage array, a resistive random access storage array or a phase change random access storage array, and the three-dimensional storage array includes a three-dimensional NAND storage array.

7. The semiconductor structure according to any one of claims 1 to 4, wherein: On a plane perpendicular to the first direction, the projection of the first chip falls within the projection of the second chip.

8. The semiconductor structure according to any one of claims 1 to 4, wherein: The first chip is bonded to the second chip.

9. A storage device, characterized in that: It comprises a plurality of semiconductor structures according to any one of claims 1 to 8, wherein the plurality of semiconductor structures are stacked in sequence along a first direction, and the first chips of two adjacent semiconductor structures are connected to each other.

10. The storage device according to claim 9, wherein: Two adjacent semiconductor structures are staggered along a second direction perpendicular to the first direction to expose a portion of the first peripheral circuit of one of the semiconductor structures, and the two adjacent first peripheral circuits are connected via a first wire.

11. The storage device according to claim 10, wherein: The storage device also includes: Package substrate; A plastic package is used to package the plurality of semiconductor structures on the packaging substrate, and the first peripheral circuit closest to the packaging substrate is connected to the packaging substrate via a second wire.

12. A storage system, characterized in that: The invention comprises a controller and the storage device according to any one of claims 9 to 11, wherein the controller is coupled to the storage device and is used to control the storage device to store data.

13. A method for preparing a semiconductor structure, characterized in that: include: forming a first chip including a first peripheral circuit, a two-dimensional memory array, and a second peripheral circuit, wherein the second peripheral circuit is connected to the first peripheral circuit and the two-dimensional memory array respectively; forming a second chip including a three-dimensional memory array; as well as The first peripheral circuit of the first chip is bonded to the second chip along a first direction.

14. The method for preparing a semiconductor structure according to claim 13, wherein: Forming a first chip including a first peripheral circuit, a two-dimensional memory array, and a second peripheral circuit includes: forming the first peripheral circuit; forming the second peripheral circuit on one side of the first peripheral circuit along a second direction, the second direction being perpendicular to the first direction; and The two-dimensional memory array is formed on one side of the second peripheral circuit along the first direction.

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