IGBT structure with floating p and n type buried layers

Abstract

The application relates to an IGBT structure with floating P and N type buried layers, wherein a collector, a P type substrate, an n type buffer zone and an n type drift zone are sequentially arranged from bottom to top; a first floating P zone, a first gate, a P body zone, a second gate and a second floating P zone are sequentially in electrical contact with the upper surface of the n type drift zone from left to right; an n type carrier buried layer is buried in the P body zone; a first N+ source zone and a second N+ source zone are respectively arranged between the first gate and the second gate; the lower surface of a gate oxide layer is in electrical contact with the upper surface of the floating P zone and the gate; and the lower surface of an emitter is in electrical contact with the upper surfaces of the first gate oxide layer, the first N+ source zone, the second N+ source zone, the protruding part of the P body zone, the second N+ source zone and the second gate oxide layer. The application can improve the withstand voltage capacity, reduce the conduction loss and the switching loss, and thus improve the reliability and the service life.

Description

Technical Field

[0001] This invention relates to the field of IGBTs, and more specifically to an IGBT structure having floating P-type and N-type buried layers. Background Technology

[0002] With the rapid development of power electronics technology, IGBTs, as important power semiconductor devices, have been widely used in power conversion, motor drives, and renewable energy. However, traditional IGBT structures have certain limitations in terms of current density, switching speed, and losses, making it difficult to meet the ever-increasing demands for high efficiency and high reliability. For example:

[0003] Current density is generally limited by physical structure and manufacturing process. Although IGBT has the characteristic of high current density, the traditional IGBT structure is often limited by chip design, material selection and packaging technology, which limits the improvement of current density. As the current density increases, the heat generation problem of IGBT will become more serious, which will affect its reliability and service life.

[0004] Switching speed often determines the application range of IGBTs in high-frequency circuits. The switching speed of traditional IGBTs is affected by the internal carrier movement speed and circuit structure, and is usually lower than that of high-speed switching devices such as MOSFETs. Slower switching speed leads to higher switching losses, increases system energy consumption and heat generation, and also limits the application of IGBTs in high-frequency circuits, especially in applications that require fast response and precise control.

[0005] Losses generally directly affect the efficiency and heat generation of a system. The losses of traditional IGBTs mainly include conduction losses and switching losses. Conduction losses are due to the saturation voltage Vcesat of the IGBT in the conduction state, which causes energy loss when current flows. Switching losses are generated during the switching process of the IGBT, including turn-on losses Eon and turn-off losses Eoff, which will reduce the efficiency of the system, increase heat generation, and may even cause the IGBT to overheat and be damaged.

[0006] Therefore, there is an urgent need to develop a new IGBT structure to solve the above-mentioned technical problems. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide an IGBT structure with floating P and N-type buried layers, which can improve the withstand voltage and switching speed, reduce conduction loss and switching loss, thereby improving reliability and service life.

[0008] To solve the above-mentioned technical problems, the technical solution of the present invention is: an IGBT structure with floating P-type and N-type buried layers, comprising:

[0009] The collector, P-type substrate, n-type buffer zone, and n-type drift region are arranged sequentially from bottom to top;

[0010] The first floating P region, the first gate, the P body region, the second gate, and the second floating P region are electrically contacted with the upper surface of the n-type drift region from left to right. The filling depth of the first floating P region is greater than the filling depth of the first gate, and the filling depth of the second floating P region is greater than the filling depth of the second gate.

[0011] An n-type carrier buried layer is embedded within the P-body region;

[0012] The first N+ source region and the second N+ source region are respectively disposed between the first gate and the second gate, and are separated by the upward protrusion of the P-body region. The first N+ source region is close to the first gate, and the second N+ source region is close to the second gate.

[0013] The lower surface of the first gate oxide layer is in electrical contact with the upper surface of the first floating P region and the first gate, respectively.

[0014] The lower surface of the second gate oxide layer is in electrical contact with the upper surface of the second floating P region and the second gate, respectively.

[0015] The emitter has its lower surface in electrical contact with the first gate oxide layer, the first N+ source region, the second N+ source region, the protrusion of the P-body region, the second N+ source region, and the upper surface of the second gate oxide layer.

[0016] Furthermore, the n-type drift region has an upwardly protruding embedment portion that is embedded between the first gate and the second gate, and the lower surface of the P-body region is in electrical contact with the embedment portion.

[0017] Furthermore, the first gate oxide layer, the second gate oxide layer, the first gate, and the second gate are all filled within a gate trench; wherein,

[0018] The first gate oxide layer and the second gate oxide layer are symmetrical about the embedding portion;

[0019] The first gate and the second gate are symmetrical about the embedded portion.

[0020] Furthermore, the first floating P region and the second floating P region are symmetrical about the embedded part.

[0021] Furthermore, in order to better lower the electric field lines near the gate and prevent electron accumulation, the first floating P region and the second floating P region are formed by ion implantation, with an implantation depth greater than that of the gate trench.

[0022] Furthermore, to better ensure the device's withstand voltage, the depth of the first floating P region and the second floating P region is 11 μm.

[0023] Furthermore, to further improve the breakdown voltage, the doping concentration of the n-type drift region is 2e12cm. -3 The P-body region has a thickness of 4 μm and a doping concentration of 1.5e15cm. -3 The doping concentration of the first N+ source region and the second N+ source region is 7e14cm. -3 .

[0024] By adopting the above technical solution, this invention optimizes the layout of the floating P-region and the N-type buried layer. The floating P-region improves the device's breakdown voltage performance. The filling depth of the floating P-region is greater than the gate's filling depth, which helps to reduce the electric field lines near the gate by adjusting the carrier concentration, preventing gate bottom breakdown caused by electron accumulation, thereby further improving the device's breakdown voltage. The N-type buried layer, embedded in the p-body region, forms a double-peak hole barrier. During forward conduction, this layer, embedded in the p-body region, separates the hole barrier from the drift region, preventing a decrease in breakdown voltage due to high n-doping. This reduces the on-state voltage drop and conduction losses without affecting the device's breakdown voltage. Furthermore, the on-state resistance is lower, thus reducing switching losses and improving switching speed. The symmetrical design of the gate, gate oxide layer, floating P-region, and N+ source region improves the device's uniformity and switching speed, reduces internal stress concentration, and enhances reliability and lifespan, making it suitable for high-power, high-frequency applications. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the IGBT structure with floating P and N-type buried layers of the present invention;

[0026] Figure 2 This is a flowchart illustrating the fabrication process of the IGBT structure with floating P-type and N-type buried layers according to the present invention.

[0027] Figure 3 This is a comparison chart of the conduction characteristic curves of an embodiment and a conventional planar gate IGBT;

[0028] Figure 4 Band diagrams for the embodiments and comparative examples;

[0029] Figure 5 A comparison diagram of the turn-on resistance for the embodiment and the comparative example;

[0030] Figure 6 The diagram shows the correspondence between the withstand pressure value and the floating P-region of different thicknesses in the example.

[0031] Figure 7 The diagram shows the withstand voltage values ​​under the optimal parameters of the embodiment.

[0032] In the figure, 1. Collector; 2. P-type substrate; 3. n-type buffer zone; 4. n-type drift region; 5. First floating P-region; 6. First gate; 7. P-body region; 8. Second gate; 9. Second floating P-region; 10. n-type buried carrier layer; 11. First N+ source region; 12. Second N+ source region; 13. First gate oxide layer; 14. Second gate oxide layer; 15. Emitter;

[0033] Figure 3 In the diagram, (a) shows the conduction characteristic curves of a traditional planar gate IGBT under different gate voltages; (b) shows the conduction characteristic curves of an embodiment under different gate voltages; and (c) shows... Figure 3 (b) Enlarged view of the gray area;

[0034] Figure 4 In the diagram, (a) is the band diagram of the comparative example; (b) is the band diagram of the embodiment.

[0035] Figure 6 In the figure, (a) shows the collector voltage-current diagram of the device corresponding to the floating P region with different thicknesses; Figure 6 (b) represents the withstand voltage of devices corresponding to floating P-regions of different thicknesses. Detailed Implementation

[0036] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0037] like Figure 1 As shown, an IGBT structure with floating P-type and N-type buried layers includes:

[0038] Collector 1, P-type substrate 2, n-type buffer zone 3 and n-type drift region 4 are arranged sequentially from bottom to top;

[0039] The first floating P region 5, the first gate 6, the P body region 7, the second gate 8, and the second floating P region 9 are electrically contacted with the upper surface of the n-type drift region 4 from left to right. The filling depth of the first floating P region 5 is greater than the filling depth of the first gate 6, and the filling depth of the second floating P region 9 is greater than the filling depth of the second gate 8.

[0040] n-type carrier buried layer 10 is buried in P-body region 7;

[0041] The first N+ source region 11 and the second N+ source region 12 are respectively disposed between the first gate 6 and the second gate 8, and are separated by the upward protrusion of the P-body region 7. The first N+ source region 11 is close to the first gate 6, and the second N+ source region 12 is close to the second gate 8.

[0042] The lower surface of the first gate oxide layer 13 is in electrical contact with the upper surfaces of the first floating P region 5 and the first gate 6, respectively.

[0043] The lower surface of the second gate oxide layer 14 is in electrical contact with the upper surface of the second floating P region 9 and the second gate 8, respectively.

[0044] The emitter 15 has its lower surface in electrical contact with the first gate oxide layer 13, the first N+ source region 11, the second N+ source region 12, the protrusion of the P-body region 7, the upper surface of the second N+ source region 12 and the second gate oxide layer 14.

[0045] Among them, the size of the n-type drift region 4 determines the voltage withstand capability of the device. The depth of the n-type drift region 4 is preferably 85 μm, and the doping concentration is generally set to 1e10-1e15 A / cm3. Different doping concentrations correspond to different on-state voltage drops and voltage withstand capabilities, which need to be considered in a compromise.

[0046] In one embodiment, such as Figure 1 As shown, the n-type drift region 4 has an upwardly protruding embedment portion (mesa width W) to be embedded between the first gate 6 and the second gate 8. Ncs The lower surface of P-body region 7 is in electrical contact with the embedded part.

[0047] In one embodiment, such as Figure 1 As shown, the first gate oxide layer 13, the second gate oxide layer 14, the first gate 6, and the second gate 8 are all filled within a gate trench; wherein,

[0048] The first gate oxide layer 13 and the second gate oxide layer 14 are symmetrical about the embedding portion;

[0049] The first gate 6 and the second gate 8 are symmetrical about the embedded portion.

[0050] The gate trench etching depth is 8.05 μm, the thickness of the first gate oxide layer 13 and the second gate oxide layer 14 is 0.05 μm, and the thickness of the first gate 6 and the second gate 8 is 8 μm. The first gate 6 and the second gate 8 each include a gate and an oxide layer surrounding the gate. The left side of the first N+ source region 11, as well as the left side of the n-type carrier buried layer 10 and the P-body region 7, are also electrically connected to the oxide layer of the first gate 6. The right side of the second N+ source region 12, as well as the right side of the n-type carrier buried layer 10 and the P-body region 7, are also electrically connected to the oxide layer of the second gate 8.

[0051] In one embodiment, such as Figure 1 As shown, the first floating P region 5 and the second floating P region 9 are symmetrical about the embedded part.

[0052] In one embodiment, such as Figure 1As shown, the first floating P-region 5 and the second floating P-region 9 are formed by ion implantation, with an implantation depth greater than that of the gate trench. This helps to lower the electric field lines near the gate and prevent electron accumulation.

[0053] In one embodiment, such as Figure 1 As shown, the ion concentrations in the first floating P-region 5 and the second floating P-region 9 are 2e20-2e22 A / cm3. The depth (thickness) is preferably 11 μm.

[0054] In one embodiment, the doping concentration of the n-type drift region 4 is 2e12cm. -3 The thickness of the P-body region 7 is 4 μm, and the doping concentration is 1.5e15cm. -3 The doping concentration of the first N+ source region 11 and the second N+ source region 12 is 7e14cm. -3 .

[0055] The fabrication method of the IGBT structure with floating P and N-type buried layers involved in the above embodiments can be, but is not limited to, as follows: Figure 2 As shown, it includes:

[0056] Step 0: First, use coating, exposure and development to depict the pattern structure, and then form the n-type drift region 4 by epitaxy. This region should have good conductivity and voltage resistance.

[0057] Step 1: Thin the silicon wafer (n-type drift region 4) and ion implant it to form a p-type substrate 2, ensuring that it has sufficient resistivity and crystal quality;

[0058] Step 2: An n-type buffer layer 3 is formed on the p-type substrate 2 by ion implantation or epitaxial growth. This layer is used to optimize the breakdown voltage characteristics of the device.

[0059] Step 3: On the n-type drift region 4, a P-body region 7 and an n-type carrier buried layer 10 are formed sequentially by ion implantation or epitaxial growth technology. The n-type carrier buried layer 10 is embedded in the P-body region 7 to ensure a good interface between the P-body region 7 and the n-type carrier buried layer 10.

[0060] Step 4: Using photolithography and etching techniques, etch a surface onto the P-body region 7 to prepare for the subsequent definition of the gate and other regions;

[0061] Step 5: Form gate trenches on the mesa using photolithography and dry etching techniques. These trenches will be used to fill polysilicon gates later.

[0062] Step 6: Use LPCVD (low-pressure chemical vapor deposition) to grow an oxide layer on the bottom and sidewalls of the gate trench to isolate the polysilicon gate;

[0063] Step 7: Fill the polysilicon gate on the oxide layer and etch to make the lower surface of the polysilicon highly smooth and uniform, forming the first gate 6 and the second gate 82, and make the first gate 6 and the second gate 8 symmetrical about the embedding part (i.e. the part between the first gate 6 and the second gate 8 where the n-type drift region is displaced).

[0064] Step 8: A first floating P region 5 and a second floating P region 9 are formed above the n-type drift region 4 by ion implantation technology. In this embodiment of the invention, the implantation depth of the floating P region is deeper than the depth of the gate trench, and the first floating P region 5 and the second floating P region 9 are symmetrical about the embedding part.

[0065] Step 9: Above the n-type drift region 4, and in the region between the first floating P region 5 and the second floating P region 9, a first N+ source region 11 connected to the first gate 6 and a second N+ source region 12 connected to the second gate 8 are formed by ion implantation or epitaxial growth technology, and the first N+ source region 11 and the second N+ source region 12 are made symmetrical about the embedding portion.

[0066] Step 10: Deposit a metal layer on top of the oxide layer, and form the emitter 15 using photolithography and etching techniques, and make the emitter 15 contact the upper surface of the oxide layer;

[0067] Step 11: On the lower surface of the P-type substrate 2, a collector electrode 1 is formed by a metallization process, and the P-type substrate 2 and the collector electrode 1 are made into good ohmic contact.

[0068] Step 12: Perform the packaging process, including bonding wires and packaging shell, to complete the manufacturing of the IGBT device.

[0069] The following is a specific simulation process to illustrate the above embodiments ( Figure 1 The beneficial effects of the proposed solutions (shown) will be described in detail.

[0070] A. The above embodiments have a smaller on-state voltage drop and lower power consumption.

[0071] Figure 3 The above embodiments and conventional planar gate IGBTs are shown in the conduction characteristic curves. The simulation process is as follows:

[0072] By biasing the voltage of all electrodes to 0V, increasing the gate voltage from 0.1V to 2V, and scanning the collector voltage from 0.1V to 20V in a certain step, the conduction characteristic curve can be obtained. Figure 3 The conduction characteristic curves under different gate voltages are shown. The on-state voltage drop corresponding to the drain current reaching 1e-6A / μm is 1.5V, which meets the design requirements. The on-state voltage drop Von of the IGBT structure is:

[0073] V on =vp+N +V MOS +V FS

[0074] Among them, v p+N It is the voltage drop across the PN junction between collector 1 and N-type buffer 3, V FS It is the voltage drop of N-type buffer 3, V MOS It is the voltage drop of the MOSFET structure in the IGBT structure.

[0075] Figure 3 (a) shows the conduction characteristics of a traditional planar gate IGBT under different gate voltages. When the gate voltage reaches 5V, the device is turned off. As the gate voltage increases, the current density in the collector after the device is turned on is approximately 1e-4A / μm, and the corresponding on-state voltage drop is approximately 2.5V.

[0076] Figure 3 (b) is a graph showing the conduction characteristics of the above embodiments under different gate voltages. Figure 3 (c) is Figure 3 (b) A magnified view of the gray area, from Figure 3 (b) and Figure 3 (c) It can be seen that the on-state voltage drop when the collector current density is 1e-6A / um in the above embodiment is about 1.5V. The on-state voltage drop is lower than that of the traditional planar gate IGBT. The lower the on-state voltage drop, the lower the loss.

[0077] Figure 4 (a) is a band diagram of a comparative example (without the n-type carrier buried layer 10 compared to the above embodiment). Figure 4 (b) is the energy band diagram of this embodiment. The comparison results show that:

[0078] In the comparative example, the high n-doping concentration at the boundary between the P-body region 7 and the n-type drift region 4 partially blocks hole flow, limiting hole entry into the P-body region 7. This causes holes to accumulate between the P-body region 7 and the n-type drift region 4, increasing the carrier concentration in the n-type drift region 4 and reducing the device's on-state voltage drop. However, the N-type barrier doping concentration affects the internal electric field distribution of the device, which also leads to a decrease in breakdown voltage and affects the device's breakdown voltage.

[0079] In this embodiment, an n-type carrier buried layer 10 is introduced into the p-body region 7. As can be seen in the energy band diagram of this region, a double-peaked hole barrier is formed. During forward conduction, embedding this layer into the p-body region 7 separates the hole barrier from the drift region, preventing a decrease in breakdown voltage due to high n-doping. That is, this embodiment can reduce the on-state voltage drop without affecting the device's breakdown voltage.

[0080] B. The above embodiments have lower on-state resistance and lower switching losses under the same gate voltage.

[0081] Figure 5 The turn-on resistance diagrams for the embodiment and comparative example (without the n-type buried carrier layer 10 compared to the above embodiment) are shown. The rise time is set to 1 ms, the gate voltage to 6V, and the drain current of a conventional IGBT is approximately 1E-6 A / μm, resulting in a calculated on-state resistance of approximately 6000 Ω. The device in this embodiment has a drain current of approximately 1.4E-6 A / μm, resulting in a calculated on-state resistance of 4285 Ω. Compared to the comparative example, the on-state resistance is reduced by 1715 Ω, and the on-state voltage drop is reduced by approximately 1V. This is because, in the turn-on state, the p-body region of the conventional structure extracts holes from the n-drift region, thereby reducing the carrier concentration in the n-drift region, decreasing the leakage current, and increasing the on-state resistance. After introducing an n-type carrier buried layer, the movement trajectory of some carriers can be suppressed under high n-doping, causing them to be stored between the n-drift region and the p-body region. This increases the carrier concentration in the drift region, reduces the on-state resistance of the device, increases the leakage current, lowers the switching loss, and makes the device easier to turn on with lower conduction loss.

[0082] C. The above embodiments have higher pressure resistance.

[0083] Figure 6 This is a graph showing the correspondence between the withstand voltage of the device and floating P-regions of different thicknesses. Figure 6 (a) Collector voltage-current diagrams of devices corresponding to floating P-regions of different thicknesses; Figure 6 (b) represents the withstand voltage of devices corresponding to floating P-regions of different thicknesses.

[0084] from Figure 6 As can be seen, without the floating P-region structure (0µm), the device's breakdown voltage is as low as 324V (a traditional IGBT is without the floating P-region structure). Due to the concentration of electrons, breakdown is most likely to occur at the bottom corner of the gate oxide layer. Introducing the floating P-region structure improves the electron and hole concentration at the bottom of the gate oxide layer, lowers the equipotential line, and thus increases the device's breakdown voltage (862V). The deeper the floating P-structure (11µm), the lower the equipotential line, and the higher the device's breakdown voltage (862V). Therefore, in this embodiment, adding a floating P-region can limit the increase in the IGBT device's breakdown voltage.

[0085] Furthermore, the breakdown voltage of the device is also affected by the doping concentration of the n-type drift region 4. As the doping concentration of the drift region decreases, the depletion layer (J2) formed becomes thicker, and the breakdown voltage of the device increases. However, IGBTs require a trade-off between breakdown voltage and on-state voltage drop. Decreasing the doping concentration of the drift region thickens the J2 junction, thus increasing the on-state voltage drop. Therefore, simply reducing the doping concentration of the epitaxial layer is not without limitations. The breakdown voltage of an IGBT (Insulated Gate Bipolar Transistor) is affected by the P-body region 7 and the N+ source region, which are mainly related to the internal electric field distribution and the formation of the PN junction.

[0086] The size, doping concentration, and electric field distribution of the p-body region 7 significantly influence the formation and performance of the PN junction. Generally, a higher doping concentration in the p-body region 7 results in better device breakdown voltage. This is because it reduces the electric field concentration, thus mitigating breakdown at the PN junction. Since J2 plays a crucial role in breakdown voltage, increasing the doping concentration of the p-type region also helps increase the thickness of J2, thereby improving the breakdown voltage. However, compared to the n-type drift region 4, the size of the p-body region 7 is too small, so increasing the doping concentration has little effect on the device's breakdown voltage.

[0087] By controlling the doping concentration of the N+ source region, the electric field distribution inside the device can be made more uniform, and the electric field concentration near the PN junction can be reduced, thereby improving the device's breakdown voltage.

[0088] Through simulation experiments, the optimal parameters were determined: with a floating P-region depth of 11 μm, the doping concentration of the n-type drift region 4 was 2e12cm. -3 The P-body thickness is 4 μm, and the doping concentration is 1.5e15 cm⁻¹. -3 The N-source doping concentration is 7e14 cm⁻¹ -3 The resulting device breakdown voltage reaches 1300-1400V (specifically as follows). Figure 7 As shown in the figure, the on-state voltage drop is only 1.5V.

[0089] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An IGBT structure with floating P and N type buried layers, characterized in that, comprising: a collector (1), a P type substrate (2), an n type buffer region (3) and an n type drift region (4) arranged in order from bottom to top; a first floating P region (5), a first gate (6), a P body region (7), a second gate (8), a second floating P region (9) in electrical contact with the upper surface of the n type drift region (4) from left to right in order, the filling depth of the first floating P region (5) is greater than the filling depth of the first gate (6), the filling depth of the second floating P region (9) is greater than the filling depth of the second gate (8); an n type carrier buried layer (10) buried in the P body region (7); a first N+ source region (11) and a second N+ source region (12) arranged between the first gate (6) and the second gate (8) respectively, separated by the upward protruding part of the P body region (7), the first N+ source region (11) is close to the first gate (6), and the second N+ source region (12) is close to the second gate (8); a first gate oxide layer (13) whose lower surface is in electrical contact with the upper surface of the first floating P region (5) and the first gate (6) respectively; a second gate oxide layer (14) whose lower surface is in electrical contact with the upper surface of the second floating P region (9) and the second gate (8) respectively; an emitter (15) whose lower surface is in electrical contact with the upper surface of the first gate oxide layer (13), the first N+ source region (11), the second N+ source region (12), the protruding part of the P body region (7), the second N+ source region (12) and the second gate oxide layer (14) respectively.

2. The IGBT structure with floating P and N type buried layers according to claim 1, characterized in that, the n type drift region (4) has an embedding part protruding upward to be embedded between the first gate (6) and the second gate (8), and the lower surface of the P body region (7) is in electrical contact with the embedding part.

3. The IGBT structure with floating P and N type buried layers according to claim 2, characterized in that, the first gate oxide layer (13), the second gate oxide layer (14), the first gate (6) and the second gate (8) are all filled in a gate trench; wherein, the first gate oxide layer (13) and the second gate oxide layer (14) are symmetrical about the embedding part; the first gate (6) and the second gate (8) are symmetrical about the embedding part.

4. The IGBT structure with floating P and N type buried layers according to claim 3, characterized in that, the first floating P region (5) and the second floating P region (9) are symmetrical about the embedding part.

5. The IGBT structure with floating P and N type buried layers according to claim 3, characterized in that, the first floating P region (5) and the second floating P region (9) are formed by ion implantation, and the implantation depth is greater than the gate trench.

6. The IGBT structure with floating P and N type buried layers according to claim 5, characterized in that, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first floating P region (5) and the second floating P region (9) have a depth of 11 μm.

7. The IGBT structure with floating P and N type buried layers according to claim 1 or 6, characterized in that, the first floating P region (5) and the second floating P region (9) have a depth of 11 μm. The n-type drift region (4) has a doping concentration of 2e12 cm -3 The P body region (7) has a thickness of 4 μm and a doping concentration of 1.5e15 cm -3 The first N+ source region (11) and the second N+ source region (12) have a doping concentration of 7e14 cm -3 .

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