Manufacturing method of IGBT (Insulated Gate Bipolar Translator) device

Abstract

The invention discloses a manufacturing method of an IGBT (Insulated Gate Bipolar Translator) device, which comprises the following steps of: completing a front surface process on the front surface of a semiconductor substrate, and forming a first conductive type lightly doped drift region of the IGBT device in the front surface process; and then carrying out a back surface process, wherein the back surface of the semiconductor substrate is thinned. And performing first back ion implantation of a second conduction type to form a collector region on the back of the drift region, and setting the implantation dose of the first back ion implantation according to the activation rate of subsequent furnace tube annealing on the collector region to ensure that activated impurities in the collector region meet the requirement of normal-temperature saturation voltage drop. And furnace tube annealing is carried out, impurities in the collector region are uniformly activated through furnace tube annealing, and the uniformity of the activated impurities ensures that the high and low temperature saturation and the pressure drop difference meet the requirements. According to the invention, the high and low temperature saturation pressure drop difference can meet the requirement under the condition of keeping the normal temperature saturation pressure drop requirement, so that the high temperature saturation pressure drop can be prevented from rising, and the high temperature saturation pressure drop can also meet the requirement.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing an insulated gate bipolar transistor (IGBT) device. Background Art

[0002] like Figure 1 As shown, it is a schematic diagram of the structure of an existing IGBT device; the existing IGBT device usually adopts an N-type device. Taking the N-type device as an example, the existing IGBT device includes:

[0003] The drift region 3 is composed of an N-type lightly doped region formed on the surface of the silicon substrate.

[0004] A P-type doped channel region 5 is formed on the surface of the drift region 3 .

[0005] The gate structure includes a gate oxide layer 10 and a polysilicon gate 11 which are stacked in sequence. Figure 1 In the embodiment, the gate structure is a trench gate, a gate oxide layer 10 is formed on the inner surface of the gate trench, a polysilicon gate 11 is filled in the gate trench, the gate trench vertically passes through the channel region 5, and the surface of the channel region 5 covered by the side of the gate structure is used as the channel region. The gate structure can also adopt a planar gate.

[0006] The N-type heavily doped emitter region 6 is formed on the surface of the channel region 5 and is self-aligned with the gate structure.

[0007] An N-type doped carrier storage layer 4 (CS) is formed in the surface region of the drift region 3 at the bottom of the channel region 5 .

[0008] An N-type doped field stop layer 2 is formed on the back side of the drift region 3 . The field stop layer 2 is usually formed by back side implantation. The doping concentration of the field stop layer 2 is greater than the doping concentration of the drift region 3 .

[0009] A P-type heavily doped collector region 1 is formed on the back side of the field stop layer 2 .

[0010] The top surface of the collector region 1 and the bottom surface of the field stop layer 2 are in contact with each other and form a back PN junction.

[0011] The front metal layer 9 is patterned to form a gate and an emitter. Figure 1 Only the emitter is shown, and the gate electrode composed of the front metal layer 9 is not shown. Figure 1 The gate is connected to the polysilicon gate 11 at the bottom. The emitter is connected to the emitter region 6 at the bottom through the contact hole 7 passing through the interlayer film 8. A channel contact region is also formed on the surface of the channel region 5. The channel contact region is heavily doped with P type, and the emitter is also connected to the channel contact region.

[0012] A collector electrode composed of a back metal layer is formed on the back side of the collector region 1 .

[0013] In the existing IGBT manufacturing method, the collector region 1 is implanted with boron ions through back ion implantation, followed by laser annealing. When the boron ion implantation dose of the back ion implantation is low in the existing method, the process fluctuation of the laser annealing machine will cause a significant change in the device saturation voltage drop (VCESAT), and affect the parameter distribution, resulting in a discrete distribution of key parameters. The IGBT prepared according to the existing method has a large difference between the room temperature and high temperature saturation voltage drops. Generally, IGBTs are used in an environment of 125°C, and the high temperature saturation voltage drop will result in higher conduction losses, which will increase the temperature rise of the device and reduce the competitiveness of the product.

[0014] In the existing method, the collector region 1 is formed by back ion implantation of boron ions followed by laser annealing. The implantation dose of boron ions in the collector region 1 is 2e12cm -2 ~3e13cm -2 The principle of laser annealing is to irradiate the surface of the semiconductor substrate with a laser beam, generate extremely high temperatures in the irradiated area, repair the damage to the crystal, and eliminate dislocations. Laser annealing can effectively eliminate the lattice defects caused by ion implantation. At the same time, due to the extremely short heating time (about one millionth of ordinary thermal annealing), it can avoid damaging the shallow junction conductivity and other junction characteristics of the integrated circuit.

[0015] However, the difference between the room temperature and high temperature saturation voltage drops of the IGBT devices prepared by the existing method is large. The difference between the room temperature and high temperature saturation voltage drops is named delta VCESAT. Generally, IGBTs are used in an environment of 125°C. The high temperature saturation voltage drop will bring higher conduction losses, making the temperature rise of the device greater, reducing the competitive advantage of the product. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide a method for manufacturing an IGBT device, which can make the difference between high and low temperature saturation voltage drops meet the requirements under the condition of maintaining the requirements of normal temperature saturation voltage drop, thereby preventing the high temperature saturation voltage drop from increasing and making the high temperature saturation voltage drop meet the requirements, thereby reducing the conduction loss of the device at the operating temperature.

[0017] In order to solve the above technical problems, the manufacturing method of the IGBT device provided by the present invention comprises the following steps:

[0018] A front process is completed on the front side of the semiconductor substrate, in which a drift region of the IGBT device lightly doped with the first conductivity type is formed; and then a back process is performed, wherein the back process includes:

[0019] The back side of the semiconductor substrate is thinned.

[0020] A first back ion implantation of the second conductivity type is performed to form a collector region on the back side of the drift region, and an implantation dose of the first back ion implantation is set according to the activation rate of the collector region by subsequent furnace annealing to ensure that the activated impurities in the collector region meet the requirements of a saturation voltage drop at room temperature.

[0021] The furnace tube annealing is performed, and the furnace tube annealing uniformly activates the impurities in the collector area and the uniformity of the activated impurities ensures that the high and low temperature saturation voltage drop difference meets the requirements.

[0022] A further improvement is that the back side process also includes the step of forming a field stop layer doped with the first conductive type, the doping concentration of the field stop layer is greater than the doping concentration of the drift region, the field stop layer is located on the back side of the drift region, and the collector region is located on the back side of the field stop layer.

[0023] A further improvement is that the ion implantation of the field stop layer is performed before the furnace tube annealing, and the impurities of the field stop layer are also activated by the furnace tube annealing.

[0024] A further improvement is that the ion implantation of the field stop layer is performed after the first back side ion implantation.

[0025] A further improvement is that the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0026] A further improvement is that the implanted impurities of the first back ion implantation include boron, and the implantation dose is 6e12cm -2 ~5e13cm -2 .

[0027] A further improvement is that the temperature of the furnace tube annealing is 350° C. to 450° C. and the time is 30 minutes to 90 minutes.

[0028] A further improvement is that the doping impurities of the field stop layer are protons, which are implemented by proton ion implantation.

[0029] A further improvement is that the proton ion implantation is performed 1 to 4 times.

[0030] A further improvement is that the proton ion implantation energy is between 300keV and 1200keV, and the implantation dose is 2e13cm -2 ~5e14cm -2 .

[0031] A further improvement is that the working environment temperature of the IGBT device reaches a high temperature of above 125°C.

[0032] A further improvement is that the thickness of the semiconductor substrate after thinning is set according to the operating voltage of the IGBT device. The greater the operating voltage of the IGBT device, the thicker the thickness of the semiconductor substrate after thinning.

[0033] A further improvement is that the operating voltage of the IGBT device includes 650V to 1700V;

[0034] When the operating voltage of the IGBT device is 650V, the thickness of the semiconductor substrate after thinning is 50 microns to 75 microns;

[0035] When the operating voltage of the IGBT device is 1200V, the thickness of the semiconductor substrate after thinning is 90 microns to 120 microns.

[0036] A further improvement is that the IGBT device is a trench gate IGBT, and the gate structure of the IGBT device formed in the front process is a trench gate.

[0037] A further improvement is that after the furnace tube is annealed, the back side process further includes:

[0038] A back metal layer is formed, wherein the back metal layer contacts the collector region and serves as a collector.

[0039] The present invention makes special settings for the back process according to the requirements of the high-low temperature saturation voltage drop difference, that is, the difference between the saturation voltage drop at high temperature and the lower room temperature. Unlike the prior art, the collector region is achieved by back ion implantation plus laser annealing. The present invention adopts back ion implantation, that is, the first back ion implantation plus furnace tube annealing, and the first back ion implantation and furnace tube annealing are set according to the needs, mainly because the injection dose of the first back ion implantation needs to be set according to the activation rate of the collector region by furnace tube annealing. Due to the metal layer that has been formed in the front process, the temperature of the furnace tube annealing in the back process is limited. Usually, after the front metal layer is completed, the furnace tube annealing temperature cannot be higher than 450°C, which causes the activation rate of the furnace tube to be less than the activation rate of the laser annealing. Therefore, the injection dose of the first back ion implantation of the present invention will be increased on the basis of the injection dose of the back ion implantation of the existing method, so that the room temperature saturation voltage drop of the device formed by the present invention can meet the requirements.

[0040] In addition, the present invention adopts furnace tube annealing for activation of impurities in the collector region. Compared with laser annealing, furnace tube annealing can achieve uniform annealing with small process fluctuations, so the impurities in the collector region can be uniformly activated, so that the parameter distribution of the device is uniform and the discreteness of the parameter distribution is small. Among them, when the device is turned on, the collector region will inject minority carriers into the drift region and thereby adjust the on-resistance and the saturation voltage drop. Since the impurities in the collector region are uniformly activated, the discreteness of the saturation voltage drop distribution can be reduced, so that the deviation between the saturation voltage drop at high temperature, i.e., the high-temperature saturation voltage drop and the saturation voltage drop at lower room temperature, i.e., the room-temperature saturation voltage drop, i.e., the difference between high and low temperature saturation voltage drops becomes smaller. In this way, when the room-temperature saturation voltage drop meets the requirements, the high-temperature saturation voltage drop also meets the requirements, so that both the room-temperature saturation voltage drop and the high-temperature saturation voltage drop meet the requirements. However, in the existing methods, due to uneven laser annealing, especially when the injection dose of back ion implantation in the collector region is low, the uneven laser annealing will cause a large change in the saturation voltage drop, increase the discreteness of the device parameter distribution at room temperature, which is not conducive to the parallel application of the device, and will cause a large deviation between the room temperature saturation voltage drop and the high temperature saturation voltage drop. When the room temperature saturation voltage drop meets the requirements, the high temperature saturation voltage drop will be too high and cannot meet the requirements, and vice versa. Therefore, the present invention can overcome the defect of the existing method that the difference between the high and low temperature saturation voltage drops is too large, so that both the room temperature saturation voltage drop and the high temperature saturation voltage drop meet the requirements. Since the actual working environment temperature of the device is not a fixed value, but is between room temperature and high temperature, when the saturation voltage drops at room temperature and high temperature meet the requirements, the invention can finally reduce the conduction loss of the device in actual working environments of various temperatures.

[0041] In addition, in the present invention, in order to make the saturation pressure drop at room temperature meet the requirements, the injection dose of the first back ion implantation is increased. The increase in the injection dose can further facilitate process control, reduce process fluctuations, further reduce the high and low temperature saturation pressure drop difference, and make process control simpler.

[0042] In addition, the doping impurities of the field stop layer of the present invention can be protons, which can be achieved through proton ion implantation. Proton ion implantation can form a deeper depth and a better concentration distribution, and can be effectively activated through furnace tube annealing. In this way, the field stop layer and the collector area can share the same furnace tube annealing process, which can further simplify the process, shorten the process cycle and reduce the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0044] Figure 1 It is a structural schematic diagram of an existing IGBT device;

[0045] Figure 2 It is a flow chart of a method for manufacturing an IGBT device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] like Figure 2 , which is a flow chart of a method for manufacturing an IGBT device according to an embodiment of the present invention; and the IGBT device corresponding to the method for manufacturing an IGBT device according to an embodiment of the present invention is also referred to. Figure 1 As shown, the manufacturing method of the IGBT device according to the embodiment of the present invention comprises the following steps:

[0047] Step S1 : completing a front process on the front side of a semiconductor substrate (sub), in which a drift region 3 lightly doped with a first conductivity type of an IGBT device is formed.

[0048] In the embodiment of the present invention, the IGBT device is a trench gate IGBT, and the gate structure of the IGBT device formed in the front process is a trench gate. In other embodiments, the IGBT device can also be a planar gate IGBT, and the corresponding gate structure is a planar gate.

[0049] Figure 1 2 shows that the trench gate includes a gate dielectric layer 10 formed in a gate trench and a gate conductive material layer 11 filled in the gate trench. In some embodiments, the gate dielectric layer 10 includes a gate oxide layer, and the gate conductive material layer 11 includes a polysilicon gate.

[0050] In some embodiments, the semiconductor substrate includes a silicon substrate.

[0051] The following structures are also formed in the front process:

[0052] The channel region 5 of the second conductivity type, the gate trench passes through the channel region 5, and the surface of the channel region 5 covered by the side surface of the gate conductive material layer 11 is used to form a conductive channel.

[0053] An emitter region 6 heavily doped with the first conductivity type is formed on the surface of the channel region 5 in self-alignment with the gate trench.

[0054] The top of the emitter region 6 is connected to the emitter electrode composed of the front metal layer 9 through a contact hole 7 passing through the interlayer film 8.

[0055] A channel contact region heavily doped with the second conductivity type is also formed on the surface of the channel region 5 , and the channel region 5 is connected to the emitter through the channel contact region.

[0056] In some embodiments, a carrier storage layer 4 doped with the first conductive type is also formed in the drift region 3 at the bottom of the channel region 5, and the doping concentration of the carrier storage layer 4 is greater than the doping concentration of the drift region 3, which is used to block minority carriers from entering the channel region 5 and thereby increase the minority carrier concentration in the drift region 3.

[0057] Step S2: Perform back surface processing, which includes:

[0058] Step S21, thinning the back side of the semiconductor substrate.

[0059] The thickness of the semiconductor substrate after thinning is set according to the operating voltage of the IGBT device. The greater the operating voltage of the IGBT device, the thicker the thickness of the semiconductor substrate after thinning. Figure 1 The semiconductor substrate shown in the figure is a thinned semiconductor substrate, the thickness of which is the thickness from the top surface of the emitter region 6 to the bottom surface of the collector region 1 formed subsequently. The drift region 3 occupies the main part and determines the breakdown voltage of the device.

[0060] In the embodiment of the present invention, the operating voltage of the IGBT device includes 650V to 1700V, for example: 650V, 750V, 950V, 1200V and 1700V.

[0061] When the operating voltage of the IGBT device is 650V, the thickness of the thinned semiconductor substrate is 50 microns to 75 microns.

[0062] When the operating voltage of the IGBT device is 1200V, the thickness of the thinned semiconductor substrate is 90 microns to 120 microns.

[0063] The thickness of the thinned semiconductor substrate at various other operating voltages can also be set in sequence as required, which will not be listed in detail here.

[0064] Step S22, perform the first back ion implantation of the second conductivity type to form a collector region 1 on the back side of the drift region 3, and set the implantation dose of the first back ion implantation according to the activation rate of the collector region 1 in the subsequent furnace tube annealing to ensure that the activated impurities in the collector region 1 meet the requirements of the saturation voltage drop at room temperature.

[0065] Step S23, performing furnace tube annealing, the furnace tube annealing uniformly activates the impurities in the collector region 1 and the uniformity of the activated impurities ensures that the high and low temperature saturation voltage drop difference meets the requirements.

[0066] In the embodiment of the present invention, the high temperature of the working environment of the IGBT device is above 125° C. The high and low temperature saturation voltage drop difference is the difference between the saturation voltage drop when working in a high temperature environment, that is, the high temperature saturation voltage drop and the saturation voltage drop when working in a low temperature environment, such as a normal temperature environment.

[0067] In an embodiment of the present invention, the back process also includes the step of forming a field stop layer 2 doped with a first conductive type, the doping concentration of the field stop layer 2 is greater than the doping concentration of the drift region 3, the field stop layer 2 is located on the back side of the drift region 3, and the collector region 1 is located on the back side of the field stop layer 2.

[0068] The ion implantation of the field stop layer 2 is performed before the furnace annealing, and the impurities of the field stop layer 2 are also activated by the furnace annealing. Preferably, the ion implantation of the field stop layer 2 is performed after the first back ion implantation. In other embodiments, the ion implantation of the field stop layer 2 can also be performed before the first back ion implantation.

[0069] In the embodiment of the present invention, the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the IGBT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. The following description takes the IGBT device as an N-type device as an example.

[0070] Taking an N-type device as an example, in some embodiments, the implanted impurities of the first back ion implantation include boron, and the implantation dose is 6e12cm -2 ~5e13cm -2 .

[0071] The temperature of the furnace tube annealing is 350°C to 450°C, and the time is 30 minutes to 90 minutes.

[0072] The doping impurities of the field stop layer 2 are protons, which are implemented by proton ion implantation.

[0073] The number of proton ion implantation is 1 to 4 times.

[0074] The implantation energy of proton ion implantation is between 300keV and 1200keV, and the implantation dose is 2e13cm -2 ~5e14cm -2 .

[0075] In the embodiment of the present invention, after the furnace tube is annealed, the back side process further includes:

[0076] A back metal layer is formed, and the back metal layer contacts the collector region 1 and serves as a collector.

[0077] The embodiment of the present invention makes special settings for the back process according to the requirements of the high-low temperature saturation voltage drop difference, that is, the difference between the saturation voltage drop at high temperature and the lower room temperature. Unlike the prior art, the collector area 1 is achieved by back ion implantation plus laser annealing. The embodiment of the present invention adopts back ion implantation, that is, the first back ion implantation plus furnace tube annealing, and the first back ion implantation and furnace tube annealing are set according to the needs. The main reason is that the injection dose of the first back ion implantation needs to be set according to the activation rate of the collector area 1 by furnace tube annealing. Due to the metal layer that has been formed in the front process, the temperature of the furnace tube annealing in the back process is limited. Usually, the furnace tube annealing temperature cannot be higher than 450°C, so the activation rate of the furnace tube annealing is less than the activation rate of the laser annealing. Therefore, the injection dose of the first back ion implantation in the embodiment of the present invention will be increased on the basis of the injection dose of the back ion implantation in the existing method, so that the room temperature saturation voltage drop of the device formed by the embodiment of the present invention can meet the requirements.

[0078] In addition, the embodiment of the present invention adopts furnace tube annealing to activate the impurities of the collector region 1. Compared with laser annealing, furnace tube annealing can achieve uniform annealing with small process fluctuations, so the impurities of the collector region 1 can be uniformly activated, so that the parameter distribution of the device is uniform and the discreteness of the parameter distribution is small. Among them, when the device is turned on, the collector region 1 will inject minority carriers into the drift region 3 and thereby adjust the on-resistance and the saturation voltage drop. Since the impurities in the collector region 1 are uniformly activated, the discreteness of the saturation voltage drop distribution can be reduced, so that the deviation between the saturation voltage drop at high temperature, i.e., the high-temperature saturation voltage drop and the saturation voltage drop at lower room temperature, i.e., the room-temperature saturation voltage drop, i.e., the difference between the high and low temperature saturation voltage drops becomes smaller. In this way, when the room-temperature saturation voltage drop meets the requirements, the high-temperature saturation voltage drop also meets the requirements, so that both the room-temperature saturation voltage drop and the high-temperature saturation voltage drop meet the requirements. In the existing method, due to the uneven laser annealing, especially when the injection dose of the back ion implantation of the collector region 1 is low, the uneven laser annealing will cause a large change in the saturation voltage drop, increase the discreteness of the device parameter distribution at room temperature, which is not conducive to the parallel application of the device, and will cause a large deviation between the room temperature saturation voltage drop and the high temperature saturation voltage drop. When the room temperature saturation voltage drop meets the requirements, the high temperature saturation voltage drop will be too high and cannot meet the requirements, and vice versa. Therefore, the embodiment of the present invention can overcome the defect of the existing method that the difference between the high and low temperature saturation voltage drops is too large, so that both the room temperature saturation voltage drop and the high temperature saturation voltage drop meet the requirements; since the actual working environment temperature of the device is between room temperature and high temperature, the embodiment of the present invention can finally reduce the conduction loss of the device at the working temperature.

[0079] In addition, in the embodiment of the present invention, in order to make the saturation pressure drop at room temperature meet the requirements, the injection dose of the first back ion implantation is increased. The increase in the injection dose can further facilitate process control, reduce process fluctuations, further reduce the high and low temperature saturation pressure drop difference, and make process control simpler.

[0080] In addition, the doping impurities of the field stop layer 2 of the embodiment of the present invention can be protons, which can be achieved through proton ion implantation. Proton ion implantation can form a deeper depth and a better concentration distribution, and can be effectively activated through furnace annealing. In this way, the field stop layer 2 and the collector region 1 can share the same furnace annealing process, which can further simplify the process, shorten the process cycle and reduce the process cost.

[0081] Compared with the existing method, the embodiment of the present invention changes the laser annealing mode of the collector region 1 to furnace annealing, which can reduce the high-temperature saturation voltage drop while keeping the room-temperature saturation voltage drop unchanged, that is, reduce delta VCESAT. Since the activation efficiency of furnace annealing is lower than that of laser annealing, it is necessary to appropriately increase the implantation dose of boron ions in the collector region 1. The implantation concentration of boron ions, that is, the implantation dose, is 6e12cm -2 ~5e13cm -2 .

[0082] The furnace tube annealing temperature is 350℃~450℃, and the time is 30~90min. A higher boron ion implantation concentration is more conducive to process control. When the boron ion implantation dose is too small, process fluctuations will cause the IGBT saturation voltage drop to increase and the distribution dispersion to increase. However, in the case of a higher boron ion implantation concentration, process control will be simpler.

[0083] Generally, there are two ways to form the field stop layer 2, one is ion implantation of phosphorus ions, and the other is multiple proton implantation, among which multiple proton implantation has a better effect. Proton implantation has two advantages: one is that the penetration depth of protons is large, and the other is that the temperature required to activate such a proton buffer layer is low. By adjusting the implantation energy, protons can be implanted in different depth ranges within the target material, and then annealed at a low temperature to form hydrogen-related donors, wherein proton ion implantation is usually achieved by hydrogen ion implantation. Compared with the existing traditional N-type buffer layer, i.e., the structure of the field stop layer 2, the proton implantation buffer layer has a deeper implantation junction depth and a different concentration distribution, which will affect the performance and dynamic robustness of the device.

[0084] In the existing method, when the collector region is equipped with a field stop layer with multiple proton implants, it is necessary to first complete the boron ion implantation and laser annealing of the collector region before proton implantation and annealing, so the process cycle is relatively long. In the embodiment of the present invention, after the annealing process of the collector region 1 is changed to a furnace tube, the annealing of the collector region 1 and the field stop layer 2 can be integrated, and the furnace tube annealing temperature is 350°C to 450°C, and the time is 30min to 90min. Under this condition, multiple protons can be effectively activated, and a certain activation rate of phosphorus ions can be guaranteed. While keeping the saturation voltage drop at room temperature unchanged, the high-temperature saturation voltage drop of the IGBT is reduced at the same time.

[0085] The embodiments of the present invention are applicable to IGBTs of multiple voltage levels, including but not limited to 650V / 750V / 950V / 1200V / 1700V, etc.

[0086] Taking a 650V trench gate IGBT as an example, the manufacturing method of the IGBT device of the embodiment of the present invention is further described:

[0087] 1. Complete the required front side process according to the process of trench gate IGBT; that is, complete step S1.

[0088] Then, step S2 is started.

[0089] 2. After completing the front-side process, the wafer, i.e., the wafer composed of the semiconductor substrate, is thinned on the back side by the TAIKO process to remove a portion of the substrate. The thickness of the substrate after thinning is 50 to 75 microns.

[0090] 3. Boron ions are implanted into the collector region 1 through back ion implantation. The implantation concentration of boron ions is 6e12cm -2 ~5e13cm -2 .

[0091] 4. The field stop layer 2 is formed by multiple proton ion implantation. The number of proton implantations is 1-4 times, the implantation energy is 300-1200keV, and the proton implantation dose is 2e13cm -2 ~5e14cm -2 .

[0092] 5. After the multiple proton implantation is completed, the wafer is furnace annealed at a temperature of 350°C to 450°C for 30 to 90 minutes;

[0093] 6. After annealing is completed, continue with the back metal process.

[0094] Taking a 1200V trench gate IGBT as an example, the manufacturing method of the IGBT device of the embodiment of the present invention is further described:

[0095] 1. Complete the required front side process according to the process of trench gate IGBT; that is, complete step S1.

[0096] Then, step S2 is started.

[0097] 2. After completing the front-side process, the wafer, i.e. the wafer composed of the semiconductor substrate, is thinned on the back side using the TAIKO process to remove a portion of the substrate. The thickness of the thinned substrate is between 90 and 120 microns.

[0098] 3. Boron ions are implanted into the collector region 1 through back ion implantation. The implantation concentration of boron ions is 6e12cm -2 ~5e13cm -2 .

[0099] 4. The field stop layer 2 is formed by multiple proton ion implantation, the number of proton implantations is 1 to 4 times, the implantation energy is 300 to 1200 keV, and the proton implantation dose is 2e13 cm -2 ~5e14cm -2 .

[0100] 5. After the multiple proton implantation is completed, the wafer is furnace annealed at a temperature of 350°C to 450°C for 30 to 90 minutes;

[0101] 6. After annealing is completed, continue with the back metal process.

[0102] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing an IGBT device, characterized in that: The steps include: A front process is completed on the front side of the semiconductor substrate, in which a drift region of the IGBT device lightly doped with a first conductivity type is formed; Then, the back side process is performed, and the back side process includes: Thinning the back side of the semiconductor substrate; Performing a first back ion implantation of a second conductivity type to form a collector region on the back of the drift region, and setting an implantation dose of the first back ion implantation according to an activation rate of the collector region by subsequent furnace annealing to ensure that the activated impurities in the collector region meet the requirements of a saturation voltage drop at room temperature; The furnace tube annealing is performed, and the furnace tube annealing uniformly activates the impurities in the collector area and the uniformity of the activated impurities ensures that the high and low temperature saturation voltage drop difference meets the requirements.

2. The method for manufacturing an IGBT device according to claim 1, wherein: The backside process also includes the step of forming a field stop layer doped with a first conductivity type, wherein the doping concentration of the field stop layer is greater than the doping concentration of the drift region, the field stop layer is located on the backside of the drift region, and the collector region is located on the backside of the field stop layer.

3. The method for manufacturing an IGBT device according to claim 2, wherein: The ion implantation of the field stop layer is performed before the furnace annealing, and the impurities of the field stop layer are also activated by the furnace annealing.

4. The method for manufacturing an IGBT device according to claim 4, wherein: The ion implantation of the field stop layer is performed after the first back surface ion implantation.

5. The method for manufacturing an IGBT device according to claim 3, wherein: The IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

6. The method for manufacturing an IGBT device according to claim 5, wherein: The implanted impurities of the first back ion implantation include boron, and the implantation dose is 6e12cm -2 ~5e13cm -2 .

7. The method for manufacturing an IGBT device according to claim 6, wherein: The temperature of the furnace tube annealing is 350° C. to 450° C., and the time is 30 minutes to 90 minutes.

8. The method for manufacturing an IGBT device according to claim 6, wherein: The doping impurities of the field stop layer are protons, which are implemented by proton ion implantation.

9. The method for manufacturing an IGBT device according to claim 8, wherein: The number of proton ion implantation is 1 to 4 times.

10. The method for manufacturing an IGBT device according to claim 8, wherein: The proton ion implantation has an implantation energy of 300keV to 1200keV and an implantation dose of 2e13cm -2 ~5e14cm -2 .

11. The method for manufacturing an IGBT device according to claim 1, wherein: The working environment temperature of the IGBT device is as high as 125°C or above.

12. The method for manufacturing an IGBT device according to claim 1, wherein: The thickness of the semiconductor substrate after thinning is set according to the operating voltage of the IGBT device. The greater the operating voltage of the IGBT device, the thicker the thickness of the semiconductor substrate after thinning.

13. The method for manufacturing an IGBT device according to claim 12, wherein: The operating voltage of the IGBT device ranges from 650V to 1700V.

14. The method for manufacturing an IGBT device according to claim 1, wherein: The IGBT device is a trench gate IGBT, and the gate structure of the IGBT device formed in the front process is a trench gate.

15. The method for manufacturing an IGBT device according to claim 1, wherein: After the furnace tube is annealed, the back side process further includes: A back metal layer is formed, wherein the back metal layer contacts the collector region and serves as a collector.

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