A two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device and a preparation method and application thereof

Abstract

The application belongs to the field of artificial neuron devices, in order to solve the problems of single function, complex manufacturing process and inability to adapt to mass production of the existing artificial neuron devices, the application provides a preparation method of a micro multifunctional artificial neuron device based on a two-dimensional WSe2 transistor, comprising the following steps: preparing a single-layer / few-layer selenium disulfide thin channel; evaporating Se / Au electrodes to manufacture a P-type WSe2 transistor; evaporating Bi / Au electrodes to manufacture an N-type WSe2 transistor and connecting by adopting a CMOS structure; the application also tests the electrical performance of the prepared device and the input and output curves of the activation function thereof, simulates various indexes and obtains the accuracy of the simulation results, and proves that the application can be applied to realize the activation function and the artificial synapse function.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor artificial neuron devices, in particular to a micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor and a preparation method and application thereof. BACKGROUND

[0002] The large number of interconnections between neurons in an artificial neural network (ANN) enables information input to be quickly transmitted to individual neurons for parallel processing, and in the process of value transmission, data calculation and storage functions are simultaneously completed. The mapping relationship between input and output is stored in the form of connection strength (weight) between neurons, so the operation efficiency is higher than that of traditional serial data processing. The more the number of neurons and layers, the stronger the data processing ability of the neural network, and the faster the learning speed. In recent years, neural networks have achieved unprecedented development and success in many aspects such as Internet of Things, cloud data processing, and machine learning. Therefore, artificial neurons, as the basic component of artificial neural networks, are particularly important. Two-dimensional materials are considered to be emerging materials with ideal properties for building the next generation of electronic products, which have the advantages of atomic thinness and no dangling bonds on the surface, attracting the attention of many researchers. Research on neural morphological devices based on two-dimensional materials has already made some achievements, such as various artificial synapse devices, memristors, optoelectronic synapses, and heterosynapses, which can realize memory effects such as conductance weight update and short-term / long-term plasticity (STP / LTP).

[0003] However, in artificial neural networks, the functions of neurons not only include inputs (synapses) with different weight changes, but also signal accumulation summation, non-linear activation, and other important functions. In early research on neural morphological devices based on two-dimensional materials, the activation function was realized by traditional metal-oxide-semiconductor (CMOS) circuits and digital-to-analog converter (ADC) circuits with reconfigurable function mapping. In recent years, with the rapid development of artificial neural networks, the number of layers required for neural networks has increased dramatically, and the number of required activation functions has also increased significantly, resulting in a sharp increase in energy consumption. Therefore, researchers have made new explorations on neural morphological devices with activation functions, such as using two-dimensional materials to realize common ReLU, Sigmoid, and Tanh activation functions. However, the current functions of these synapses, such as accumulation summation and non-linear activation, are present in separate devices, and their structures and processes are complex, which will inevitably increase the system manufacturing steps and costs and occupy more space in the case of higher hardware resource requirements and integration levels of deep neural networks.

[0004] Traditional artificial neurons, such as artificial synapses, activated neurons are made by stacking different kinds of materials in a specific structure. However, these devices have the problem of single function, which can only realize perception as artificial synapses or only realize the function of storing stimulus signals. And current artificial synapse devices based on two-dimensional materials mostly rely on TMDs, graphene, boron nitride, ferroelectric materials and other artificial stacking. The required materials are various, and the production process is complex and time-consuming, which is not conducive to the application of future large-scale neuromorphic devices. SUMMARY

[0005] The purpose of the present application is to provide a preparation method of a micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor, which can solve the problem of separate devices and complex production of required materials for current synaptic function and activation function.

[0006] The multi-functional platform based on WSe2 transistor prepared by the present application can realize the functions of Sigmoid activation function and artificial synapse, and has simple structure and low production complexity. It adjusts the output voltage by controlling the public gate input voltage to realize the output sigmoid curve. Programming different gate electric stimulation signals successfully simulates a variety of synaptic functions, including excitatory / inhibitory postsynaptic potential (EPSC / IPSC), double pulse excitatory / inhibitory (PPF / PPD) and LTP / LTD, etc. The present application aims to overcome the limitation that the artificial synapse and nonlinear activation function are in a separate state in the existing artificial neuromorphic device, and realizes stable effect with simple materials and production method, which provides a more simple manufacturing process for the realization of future all-hardware artificial neural network.

[0007] The present application provides a preparation method of a micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor, which comprises the following steps:

[0008] S1 obtains a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, transfers a WSe2 film to the insulating silicon oxide layer in the silicon wafer as a channel; the WSe2 film is composed of 10 or fewer monolayer two-dimensional WSe2;

[0009] S2 prepares two parallel strip-shaped Au electrodes on the WSe2 film; wherein the two parallel strip-shaped Au electrodes are respectively used as the source and drain of the P-type WSe2 transistor; a silicon wafer comprising a P-type WSe2 transistor is obtained;

[0010] S3, two parallel strip-shaped Bi / Au electrodes are prepared on the WSe2 film; the two parallel strip-shaped Bi / Au electrodes are respectively used as the source electrode and the drain electrode of the N-type WSe2 transistor; a silicon wafer comprising the P-type WSe2 transistor and the N-type WSe2 transistor is obtained; the heavily doped conductive silicon layer in the silicon wafer is used as the common gate electrode of the P-type WSe2 transistor and the N-type WSe2 transistor; the source electrode of the P-type WSe2 transistor and the source electrode of the N-type WSe2 transistor are connected to each other to form a common source and common gate structure.

[0011] Preferably, in the step S2, the two parallel strip-shaped Au electrodes are prepared on the WSe2 film, and the preparation process specifically comprises the following steps: photoresist is coated on the WSe2 film, ultraviolet exposure and development are performed to obtain two parallel strip-shaped electrode patterns, Se with a thickness of 8-15 nm and Au with a thickness of 40-100 nm are sequentially evaporated, and after the photoresist is removed, the Se layer is removed by vacuum drying to obtain a silicon wafer comprising the P-type WSe2 transistor.

[0012] Preferably, in the step S3, the two parallel strip-shaped Bi / Au electrodes are prepared on the WSe2 film, and the preparation process specifically comprises the following steps: photoresist is coated on the WSe2 film, ultraviolet exposure and development are performed to obtain two parallel strip-shaped electrode patterns, a Bi layer with a thickness of 2-10 nm and an Au layer with a thickness of 40-100 nm are sequentially evaporated, and after the photoresist is removed, a silicon wafer comprising the P-type WSe2 transistor and the N-type WSe2 transistor is obtained.

[0013] The application further provides a two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device, comprising a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, and a WSe2 film as a channel is arranged on the insulating silicon oxide layer; the WSe2 film is composed of 10 or fewer single-layer two-dimensional WSe2;

[0014] Two parallel strip-shaped Au electrodes are arranged on the WSe2 film; the two parallel strip-shaped Au electrodes are respectively used as the source electrode and the drain electrode of the P-type WSe2 transistor; the thickness of the strip-shaped Au electrode is 40-100 nm;

[0015] Two parallel strip-shaped Bi / Au electrodes are further arranged on the WSe2 film; the two parallel strip-shaped Bi / Au electrodes are respectively used as the source electrode and the drain electrode of the N-type WSe2 transistor; the Bi / Au electrode is composed of a Bi layer with a thickness of 2-10 nm and an Au layer with a thickness of 40-100 nm, and the Bi layer is located between the Au layer and the WSe2 film;

[0016] The heavily doped conductive silicon layer in the silicon wafer simultaneously serves as a common gate of a P-type WSe2 transistor and a N-type WSe2 transistor; the source of the P-type WSe2 transistor and the source of the N-type WSe2 transistor are connected to each other as a common source.

[0017] Preferably, the micro multi-functional artificial neuron device based on the two-dimensional WSe2 transistor has an insulating silicon oxide layer with a thickness of 260-500 nm; a channel width between two parallel strip-shaped Au electrodes is 4-7 microns; and a channel width between two parallel strip-shaped Bi / Au electrodes is 4-7 microns.

[0018] The application further provides an application of the micro multi-functional artificial neuron device based on the two-dimensional WSe2 transistor in realizing an activation function, which comprises the following steps: inputting a level signal varying between a positive level and a negative level to the common gate, wherein the positive level is not greater than 60 V, and the negative level is not less than -60 V; connecting a constant level signal to the drain of the P-type WSe2 transistor; grounding the drain of the N-type WSe2 transistor; outputting a signal varying with the level of the common gate through the common source; and the relationship between the signal output by the common source and the level signal input to the common gate conforms to the function relationship of the activation function.

[0019] Preferably, the activation function is a Sigmoid function, and the level signal varying between the positive level and the negative level is specifically a level signal varying from -20 V to 20 V, and the drain of the N-type WSe2 transistor is connected to a constant level signal of 1 V.

[0020] The application further provides an application of the micro multi-functional artificial neuron device based on the two-dimensional WSe2 transistor in realizing a synaptic function, which comprises the following steps: keeping a constant common source voltage, taking the common gate as an electrical signal stimulation input end, inputting an electrical signal stimulation, and taking the drain current of the drain of the P-type WSe2 transistor as an output.

[0021] The application further provides an application of the micro multi-functional artificial neuron device based on the two-dimensional WSe2 transistor in realizing a full hardware artificial neural network, which comprises the following steps: the full hardware artificial neural network comprises no less than two micro multi-functional artificial neuron devices based on the two-dimensional WSe2 transistor, wherein at least one of the micro multi-functional artificial neuron devices based on the two-dimensional WSe2 transistor serves as an artificial neuron node device, and at least one of the micro multi-functional artificial neuron devices based on the two-dimensional WSe2 transistor serves as an activation function device.

[0022] Preferably, the artificial neuron node device, the common gate as a stimulus signal input end, a voltage signal in the range of 5V-30V is applied, the common source is connected to a constant voltage signal of 1V, the drain of the P-type WSe2 transistor is grounded through a connecting resistance element; a node is arranged between the resistance element and the drain of the P-type WSe2 transistor, a lead wire is drawn from the node to connect the common gate of the activation function device as the input of the activation function device, and the common source of the activation function device is connected as the output; the drain of the N-type WSe2 transistor of the activation function device is connected to a constant voltage signal of 1V, and the drain of the P-type WSe2 transistor of the activation function device is grounded; when the full hardware artificial neural network includes more than one artificial neuron node device, the nodes between the resistance and the drain of each artificial neuron node device are connected together to serve as the input of the activation function device in parallel to achieve the purpose of accumulating summation.

[0023] In order to solve the problems of single function, complex manufacturing process and inability to adapt to mass production of the existing artificial synapses, the present application uses multilayer WSe2 as a channel material and uses different work function metals to construct contact electrodes, thereby obtaining different channel types and further constructing a transistor type device that realizes a Sigmoid function. The polarity of the WSe2 transistor is changed by the method of metal contact, which only requires one material and does not require additional chemical doping. The multiple material stacking reduces the complexity of the neuromorphic device manufacturing process, and the modulation effect stability is ensured through repeated experiments. At the same time, the WSe2 transistor has a memory function due to the adsorption of air, water and oxygen molecules and the surface defects of the dielectric layer, and can realize the functions of artificial synapses and activation functions on one device.

[0024] Compared with the prior art, the technical scheme conceived by the present application can achieve the following beneficial effects:

[0025] (1) The present application can realize the functions of synapses and nonlinear activation on one device, increase the diversity of device functions, and simplify the manufacturing process. This can reduce the space occupied by elements in future large-scale integrated circuits, improve the space efficiency and usability of elements.

[0026] (2) The present application changes the polarity of the WSe2 transistor by the method of metal contact, which can realize n and p type effects at the same time with only one material. Compared with other artificial neuron devices, the present application only requires one material and does not need to be stacked, has the characteristics of simple manufacturing materials and stable manufacturing effect, has the advantages of simple chemical doping process, low cost and easy manufacturing. The present application has good stability and excellent reproducibility, and enhances the reliability and repeatability of the method. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description, and then some specific embodiments of the present application will be described in detail with reference to the drawings in an exemplary but non-limiting manner. The same reference signs in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0028] Figure 1 is a structural schematic diagram of a micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor according to the present application.

[0029] Figure 2 is a flowchart of the mechanical peeling and transferring process in the preparation method of the micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor according to the present application. In the figure, reference sign (1) represents transferring the mechanically peeled two-dimensional material on the adhesive tape to the PDMS, reference sign (2) represents the PDMS on which the two-dimensional material has been transferred, reference sign (3) represents placing the PDMS with the two-dimensional material close to the silicon substrate, reference sign (4) represents tightly placing the PDMS with the two-dimensional material on the silicon substrate and heating to 60 degrees to assist the transferring, reference sign (5) represents slowly lifting the PDMS, and reference sign (6) represents that the two-dimensional material has been transferred to the silicon substrate.

[0030] Figure 3 is a flowchart of the UV lithography and thermal evaporation steps in the preparation method of the micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor according to the present application. In the figure, reference sign (1) represents spinning the photoresist on the silicon substrate with the two-dimensional material, reference sign (2) represents drawing the electrode pattern after UV light exposure, reference sign (3) represents showing the electrode pattern after developing the sample with the developing agent, and reference sign (4) represents evaporating the metal to form the electrode.

[0031] Figure 4 is an optical microscope image of the micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor according to the present application and a schematic diagram of the electrical connection thereof.

[0032] Figure 5 is a scanning electron microscope image of the micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor according to the present application.

[0033] Figure 6 is an electrical characterization image of the metal contact polarity adjustment in the micro multi-functional artificial neuron device based on a two-dimensional WSe2 transistor according to the present application; wherein (a) is the output characteristic curve of a P-type transistor, (b) is the transfer characteristic curve of a P-type transistor, (c) is the output characteristic curve of an N-type transistor, and (d) is the transfer characteristic curve of an N-type transistor.

[0034] Figure 7is the sigmoid activation function and its simulation accuracy in the micro multi-functional artificial neuron device of the two-dimensional WSe2 transistor in the embodiment of the application, wherein (a) is a test curve and its fitting image compared with the original sigmoid curve image, (b) is the fitting curve and the sigmoid curve in the simulation recognition accuracy of the convolutional neural network (CNN) and the multi-layer perceptron (MLP).

[0035] Figure 8 is the artificial synapse function and its simulation result in the micro multi-functional artificial neuron device of the two-dimensional WSe2 transistor in the embodiment of the application, wherein (a) is the post-synaptic current of different amplitude V GS , (b) is the PPF exponential fitting image, (c) is the PPD exponential fitting image, (d) is the post-synaptic current (V GS = 20 V, V DS = 1 V) of different frequencies, (e) is the synapse enhancement / inhibition image, and (f) is the accuracy of the artificial synapse in the crossim platform in handwritten digital recognition.

[0036] Figure 9 is the effect of the synaptic characteristics of the micro multi-functional artificial neuron device of the two-dimensional WSe2 transistor in the embodiment under a closed environment, (a) and (b) are the excitatory post-synaptic current images (V GS = 20 V, V DS = 1 V) under the conditions of air and vacuum at frequencies of 1 Hz and 5 Hz, respectively, (c) and (d) are the inhibitory post-synaptic current images (V GS = 20 V, V DS = 1 V) under the conditions of air and vacuum at frequencies of 1 Hz and 5 Hz, respectively. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0038] (1) Fabrication of WSe2 channel: Take a small piece of WSe2 crystal and place it on the adhesive tape. Tear the tape with the material by mechanical exfoliation. Stick the tape with the material on the prepared PDMS. Find the WSe2 film under the microscope. Then transfer the WSe2 film to the silicon wafer by the stamp transfer method using the transfer table.

[0039] (2) P-type WSe2 transistor fabrication by evaporating Se / Au electrode: spin a layer of photoresist LOR3A, 180 degree baking for 5 minutes, then spin photoresist S1805, 120 degree baking for 1 minute. After UV exposure to make electrode pattern, immerse in developer for 30-45 seconds. After development, put into thermal evaporator to evaporate 10 nm Se and 50 nm Au. After immersing in N-methyl pyrrolidone solution for two hours to remove excess metal, put the prepared device into a vacuum drying oven to anneal, bake at 160 degrees for 4 hours to remove the Se layer;

[0040] (3) N-type WSe2 transistor fabrication by evaporating Bi / Au electrode and adopting common gate and common drain structure: continue to spin a layer of photoresist LOR3A on the device annealed in step (2), 180 degree baking for 5 minutes, then spin photoresist S1805, 120 degree baking for 1 minute. After UV exposure to make electrode pattern, immerse in developer for 30-45 seconds. Put into thermal evaporator to evaporate 5 nm Bi and 50 nm Au under vacuum. After immersing in N-methyl pyrrolidone solution for two hours to remove excess metal, put the prepared device into a vacuum drying oven to bake at 100 degrees for 0.5-2 hours to remove excess moisture. Two Au electrodes, the WSe2 film material sandwiched therebetween, a 280 nm thick high-voltage-resistant insulating silicon oxide layer, and a heavily doped conductive silicon wafer constitute a P-type transistor. The two parallel electrodes form the source and drain, and the heavily doped silicon wafer is the global gate. The width of the electrode is 1-3 μm, and the channel width between the two parallel electrodes is 4-7 μm. Similarly, Bi / Au, WSe2 film insulating layer, and heavily doped silicon wafer constitute an N-type transistor, which is a three-terminal device with source, drain, and gate. In the process of patterning the Bi / Au electrode, the source of the N-type and P-type transistors is connected to form a common source and common gate structure. The obtained device is optically imaged, and the image and scanning electron microscope image are shown in Figure 4 , Figure 5 ;

[0041] (4) Test various electrical properties of artificial synapses and their activation function input-output curves, simulate various indicators, and obtain the accuracy of the simulation results: test the metal contact polarity adjustment effect of the multifunctional device prepared in step (3), as well as the post-synaptic current (PSC) in the artificial synapse, including excitatory / inhibitory post-synaptic current (EPSC / IPSC), double-pulse facilitation (PPF), double-pulse depression (PPD), and the effect of synaptic enhancement and inhibition on the renewable transformed conductance. And by controlling the input of the common gate electrical signal, the sigmoid test curve is obtained, and the feasibility and recognition effect are tested in artificial neural network simulation. For specific test methods, refer to Figure 4 The structure, first test the performance of N, P transistor alone, respectively, 1V voltage is applied to the source and drain, and the gate voltage is from -60V to 60V, and the characteristic curve is shown inFigure 6 , indicating that WSe2 is a transistor that modulates from ambipolar to N, P characteristics. The sigmoid curve is tested by applying a varying level from -20 V to 20 V to the common gate, while the Au electrode not connected to the Bi / Au electrode is connected to a constant level signal of 1 V. The Bi / Au electrode not connected to the Au electrode is grounded. The Bi / Au electrode connected to the Au electrode is connected as a common source output signal that varies with the common gate level. As shown in a of Figure 7 , the experimental test curve in the figure is compared with the standard curve, and the simulation accuracy of the convolutional neural network (CNN) and the multi-layer perceptron (MLP) reaches more than 98%. In the synaptic function, the gate is an electrical signal stimulation input, and the source-drain current is an output. We read the source-drain current by encoding the input voltage signal with a constant 1 V source-drain voltage. The synaptic effect diagram is shown in Figure 8 . There is an obvious hysteresis window in the transfer characteristic curve of the transistor bidirectional scanning, which shows the memory performance. The main reason is the adsorption / desorption of water and oxygen molecules on the surface of the two-dimensional material and the interfacial charge trapping / detrapping between the two-dimensional material and the dielectric layer. Based on the regulation of the gate voltage on I DS , we regard the gate electrode signal input end of the transistor as the presynaptic membrane, and the source electrode signal output end as the postsynaptic membrane, and I DS as the postsynaptic current (PSC) to realize the synaptic weight change function to simulate the plasticity of biological synapses.

[0042] 1 V is taken as the value of the fixed read voltage V DS , and different VGS pulse voltages are programmed as presynaptic membrane stimulation signals to study the effects of V GS pulse amplitude and width on PSCs. As can be clearly seen from a of Figure 6 , V GS has an enhancing effect on PSCs. When the voltage signal pulse width is 1 ms and the amplitude increases from 5 V to 30 V, the excitatory postsynaptic current (EPSC) gradually increases from 10 nA to nearly 100 nA. These phenomena show that the postsynaptic current can change differently through different electrical stimulation, which is consistent with the corresponding potential change of biological synapses caused by neurotransmitters. In addition, by applying two consecutive V GS input pulses with different time intervals, the behavior of paired-pulse facilitation (PPF) and paired-pulse depression (PPD) is successfully simulated. In the enhancement / depression of the postsynaptic current, the PSC generated by the second electrical signal stimulation is different from the PSC generated by the first electrical signal stimulation, and the postsynaptic current generated by the second signal stimulation is larger (ΔI2>ΔI1), which is a paired-pulse enhancement / depression. This is similar to the excitatory / inhibitory effect of the presynaptic membrane releasing neurotransmitters on the postsynaptic membrane in biological synapses. We set V DS = 1 V, V GSPPF, PPD were measured at different intervals of time with 20V (enhancement), -10V (inhibition) and 1ms pulse width. Then PPF, PPD indices were calculated according to equation (1).

[0043] PPF / PPD index = [ | ΔI2- ΔI1| / ΔI1] * 100% (1)

[0044] Where ΔI1and ΔI2are the absolute values of the difference between PSC and presynaptic current of each pulse stimulation. According to PPF, PPD indices at different time intervals, we obtained the fitting non-linear as Figure 8 where b and c. At larger intervals of voltage pulse, both PPF and PPD indices decreased significantly. This decreasing trend is consistent with the biological memory double exponential function, that is, the transistor synapse can mimic the memory learning function of biological synapse.

[0045] According to the PPF and PPD indices calculated by equation (1), we can further calculate their relaxation times. Equation (2) is the fitting formula of double exponential function, from which we can calculate the relaxation times τ of the two stages of rapid and slow decrease of PPF and PPD indices when the time interval changes. Respectively, 3.1ms (τ1, PPF), 154.9ms (τ2, PPF), 2.9ms (τ1, PPD) and 454.3ms (τ2, PPD), these data show that the memory effect of our device can be enhanced / inhibited in short time intervals.

[0046] PPF / PPD index = A + B1exp(-t / τ1) + B2exp(-t / τ2) (2)

[0047] Moreover, at V GS The postsynaptic current also has different changes under the action of signals with different frequencies (1Hz, 5Hz, 10Hz). Figure 7 As can be seen in Fig. 4d, EPSC increases significantly from 1Hz to 5Hz, indicating that our device can also achieve the purpose of weight update by applying voltage pulses with different frequencies. Then we verify the stability of the continuous change of the enhancement / inhibition effect under continuous stimulation by applying the programmed pulse sequence stimulation. Using positive pulse V GS = 30V, negative pulse V GSA continuous pulse signal of -5V with a pulse width and interval of 50ms was used to stimulate the PSC after 60 pulses, resulting in a graph showing the change in PSC. Positive (negative) pulses induced an increase (decrease) in PSC. Under positive pulses, PSC gradually increased from 200nA to 800nA, exhibiting weak linearity until approaching saturation. Under negative voltage pulses, PSC gradually decreased to saturation. We used this enhanced / inhibited postsynaptic current data to calculate the changing conductance data, and then imported it into a pre-built model for simulation verification. A perceptron artificial neural network (MLP) was built using the CrossIM simulation platform and supervised learning was performed using the MNIST dataset. The model was trained for 20 epochs with 8000 handwritten digit images for recognition in each training epoch. The accuracy was as follows: Figure 6 As shown in Figure 'a', the data in the figure shows that the standard model's recognition accuracy reached 98.05% after several training cycles, while the accuracy of our synaptic device obtained from the experimental data simulation was 90.53%. These results demonstrate that our synaptic device can accurately recognize digits after learning. To investigate the effect of its synaptic properties in a closed environment, we conducted experiments in air and high vacuum (4.5 × 10⁻⁶). -5 We tested its electrical and memory properties under conditions of Pa. DS =1V, Width=10ms, V GS The EPSC was obtained under a positive bias of 20V. Figure 9 (a, b) in the text. Negative bias voltage V GS Inhibitory postsynaptic current (IPSC) is obtained under a stimulus of -10V, such as Figure 9 As shown in figures c and d, under 20 consecutive signal stimuli at frequencies of 10 Hz and 5 Hz, it can be seen that the transistor synapse retains its memory properties in a vacuum. This means that the trapping / detrapping of electrons by interfacial defects between the two-dimensional material and the dielectric layer is the cause of this phenomenon. The figure shows that the PSC (Power Strain Concentration) is lower than that measured in air, indicating that the adsorption of water and oxygen molecules, along with the trapping / detrapping of interfacial charges between the material and the dielectric layer, have a synergistic effect on synaptic behavior.

[0048] This invention employs metal contacts to adjust the polarity of WSe2 transistors to construct activation function connection structures and artificial synaptic properties. The applicable metal materials and two-dimensional semiconductor materials are not limited to Au / Bi and WSe2; other metals with high work functions can also be used during the fabrication process to alter the polarity of two-dimensional semiconductor materials, constructing sigmoid circuit structures to achieve activation and artificial synaptic functions. Furthermore, the fabrication method of this invention can be extended to other transition metal selenium group compound two-dimensional materials.

[0049] The application provides application of a two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device in realizing an activation function, wherein a level signal changing between a positive level and a negative level is input to a common gate, the positive level is not greater than 60 V, and the negative level is not less than -60 V.

[0050] The drain of the N-type WSe2 transistor is connected with a constant level signal.

[0051] The drain of the P-type WSe2 transistor is grounded, a signal changing with the common gate level is output through the common source, and the relationship between the signal output by the common source and the level signal input to the common gate conforms to the function relationship of the activation function.

[0052] The application provides application of a two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device in realizing a synapse function, wherein a constant common source voltage is maintained, the common gate is used as an electrical signal stimulation input end, an electrical signal stimulation is input, and the drain current of the drain of the P-type WSe2 transistor is used as output.

[0053] The application provides application of a two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device in realizing a full hardware artificial neural network, and the full hardware artificial neural network comprises no less than two two-dimensional WSe2 transistor-based micro multi-functional artificial neuron devices, wherein at least one two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device is used as an artificial neuron node device, and at least one two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device is used as an activation function device.

[0054] The above merely illustrates some specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A method for preparing a two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device, characterized in that, The method comprises the following steps: S1: obtaining a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, transferring a WSe2 film onto the insulating silicon oxide layer in the silicon wafer as a channel; the WSe2 film is composed of 10 or fewer monolayer two-dimensional WSe2; S2: preparing two parallel strip-shaped Au electrodes on the WSe2 film; the two parallel strip-shaped Au electrodes are respectively used as a source electrode and a drain electrode of a P-type WSe2 transistor; a silicon wafer comprising the P-type WSe2 transistor is obtained; S3: preparing two parallel strip-shaped Bi / Au electrodes on the WSe2 film; the two parallel strip-shaped Bi / Au electrodes are respectively used as a source electrode and a drain electrode of an N-type WSe2 transistor; a silicon wafer comprising the P-type WSe2 transistor and the N-type WSe2 transistor is obtained; the heavily doped conductive silicon layer in the silicon wafer is used as a common gate electrode of the P-type WSe2 transistor and the N-type WSe2 transistor; the source electrode of the P-type WSe2 transistor and the source electrode of the N-type WSe2 transistor are connected to each other to form a common-source common-gate structure; In step S2, the two parallel strip-shaped Au electrodes on the WSe2 film are prepared by the following steps: coating photoresist on the WSe2 film, exposing to ultraviolet light and developing to obtain two parallel strip-shaped electrode patterns, sequentially evaporating Se with a thickness of 8-15 nm and Au with a thickness of 40-100 nm, and removing the Se layer by vacuum drying after removing the photoresist to obtain a silicon wafer comprising the P-type WSe2 transistor; In step S3, the two parallel strip-shaped Bi / Au electrodes on the WSe2 film are prepared by the following steps: coating photoresist on the WSe2 film, exposing to ultraviolet light and developing to obtain two parallel strip-shaped electrode patterns, sequentially evaporating a Bi layer with a thickness of 2-10 nm and an Au layer with a thickness of 40-100 nm, and removing the photoresist to obtain a silicon wafer comprising the P-type WSe2 transistor and the N-type WSe2 transistor.

2. The micro multi-functional artificial neuron device based on two-dimensional WSe2 transistor prepared by the preparation method of claim 1, characterized in that, It comprises: a silicon wafer composed of an insulating silicon oxide layer and a heavily doped conductive silicon layer, wherein a WSe2 film is arranged on the insulating silicon oxide layer as a channel; the WSe2 film is composed of 10 or fewer monolayer two-dimensional WSe2; two parallel strip-shaped Au electrodes are arranged on the WSe2 film; the two parallel strip-shaped Au electrodes are respectively used as a source electrode and a drain electrode of a P-type WSe2 transistor; the thickness of the strip-shaped Au electrode is 40-100 nm; two parallel strip-shaped Bi / Au electrodes are further arranged on the WSe2 film; the two parallel strip-shaped Bi / Au electrodes are respectively used as a source electrode and a drain electrode of an N-type WSe2 transistor; the Bi / Au electrode is composed of a Bi layer with a thickness of 2-10 nm and an Au layer with a thickness of 40-100 nm, wherein the Bi layer is located between the Au layer and the WSe2 film; The heavily doped conductive silicon layer in the silicon wafer serves as a common gate for both the P-type WSe2 transistor and the N-type WSe2 transistor; the source of the P-type WSe2 transistor and the source of the N-type WSe2 transistor are connected to each other as a common source.

3. The two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device of claim 2, wherein, The thickness of the insulating silicon oxide layer is 260-500 nm; the channel width between the two parallel strip-shaped Au electrodes is 4-7 μm; the channel width between the two parallel strip-shaped Bi / Au electrodes is 4-7 μm.

4. The application of the two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device in realizing the function of activation function according to claim 2, characterized in that, The method comprises the following steps: A level signal varying between a positive level and a negative level is input to the common gate, wherein the positive level is not greater than 60 V, and the negative level is not less than -60 V; The drain of the N-type WSe2 transistor is connected to a constant level signal; The drain of the P-type WSe2 transistor is connected to ground; a signal varying with the level of the common gate is output through the common source; the relationship between the signal output by the common source and the level signal input to the common gate conforms to the function relationship of an activation function.

5. The use according to claim 4, wherein the compound is ###0002### The activation function is a Sigmoid function, The level signal varying between the positive level and the negative level is specifically a level signal varying from -20 V to 20 V, and the drain of the N-type WSe2 transistor is connected to a constant level signal of 1 V.

6. The use of the two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device according to claim 2 in realizing synaptic function, wherein, The method comprises the following steps: A constant common source voltage is maintained, the common gate is taken as an electrical signal stimulation input end, an electrical signal stimulation is input, and the drain current of the drain of the P-type WSe2 transistor is taken as an output.

7. The application of two-dimensional WSe2 transistor-based micro multi-functional artificial neuron device in realizing full hardware artificial neural network according to claim 2, characterized in that, The method comprises the following steps: The all-hardware artificial neural network comprises no less than two micro multi-functional artificial neuron devices based on two-dimensional WSe2 transistors, wherein at least one of the micro multi-functional artificial neuron devices based on two-dimensional WSe2 transistors serves as an artificial neuron node device, and at least one of the micro multi-functional artificial neuron devices based on two-dimensional WSe2 transistors serves as an activation function device.

8. Use according to claim 7, wherein the compound is ###0002### The common gate of the artificial neuron node device serves as a stimulation signal input end, a voltage signal in the range of 5 V to 30 V is applied, the common source of the artificial neuron node device is connected to a constant level signal of 1 V, and the drain of the P-type WSe2 transistor is grounded through a connection resistor element; a node is arranged between the resistor element and the drain of the P-type WSe2 transistor, a lead wire is drawn from the node to connect the common gate of the activation function device as an input of the activation function device, and the common source of the activation function device is taken as an output; the drain of the N-type WSe2 transistor of the activation function device is connected to a constant voltage level signal of 1 V, and the drain of the P-type WSe2 transistor of the activation function device is grounded; When the all-hardware artificial neural network comprises more than one artificial neuron node device, the nodes between the resistor elements and the drains of the artificial neuron node devices are connected together to serve as inputs of the activation function device, so as to realize parallel superposition and achieve the purpose of accumulation and summation.

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