Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present disclosure is to suppress corrosion of a metal used in a termination structure in a semiconductor device. A semiconductor substrate (1) is provided with: a plurality of first termination semiconductor layers (12) of a first conductivity type provided in a first termination region (22) on a surface layer on the first main surface (S1) side of a drift layer (10); a second termination semiconductor layer (13) of a second conductivity type is provided on a surface layer on the first main surface (S1) side of the drift layer (10) at an end of the semiconductor substrate (1) in the second termination region (23). A semiconductor device (101) is provided with: a first insulating layer (2) provided on a first main surface (S1) in a first termination region (22); a plurality of first terminal electrode layers (5) that are provided on the first main surface (S1) and are electrically connected to the plurality of first terminal semiconductor layers (12); a second termination electrode layer (6) that is provided on the first main surface (S1) and is electrically connected to the second termination semiconductor layer (13); a second insulating layer (3) provided on the first main surface (S1) and in contact with the outermost first termination semiconductor layer (12) and the second termination semiconductor layer (13); and a sealing material (9) which is in contact with the upper surface of the second insulating layer (3).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] In semiconductor devices, RFP (Resistive Field Plate) is sometimes used to improve the withstand voltage of the terminal region. RFP promotes the expansion of the depletion layer at the edge of the pn junction in the terminal region and relaxes the electric field concentration. This can prevent the edge of the pn junction from breaking down (see, for example, Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-150025

[0004] Recently, with the purpose of low carbonization and energy saving, the use of semiconductor products represented by power modules has been diversified, and high reliability in various environments corresponding to the urgent expectations of users has been required. In particular, in the temperature and humidity bias (THB) test, the required level is tending to be higher. In the THB test, the metal used in the terminal structure will corrode, and there is a problem of damage or increase in withstand voltage leakage. Summary of the invention

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to suppress corrosion of metal used in a terminal structure in a semiconductor device.

[0006] The semiconductor device disclosed in the present invention is divided into an active region, a first terminal region surrounding the active region, and a second terminal region surrounding the first terminal region in a plan view, and comprises a semiconductor substrate having a first main surface and a second main surface which is a main surface opposite to the first main surface, the semiconductor substrate comprising: a drift layer of a second conductivity type; a plurality of first terminal semiconductor layers of a first conductivity type, which are provided as surface layers on the first main surface side of the drift layer in the first terminal region; and a second terminal semiconductor layer of a second conductivity type, which is provided on the drift layer at an end of the semiconductor substrate in the second terminal region. The semiconductor device comprises: a first insulating layer, which is arranged on the first main surface in the first terminal region; a plurality of first terminal electrode layers, which are arranged on the first main surface and are electrically connected to the plurality of first terminal semiconductor layers via openings in the first insulating layer; a second terminal electrode layer, which is arranged on the first main surface and is electrically connected to the second terminal semiconductor layer; a second insulating layer, which is arranged on the first main surface and has one end in contact with the outermost first terminal semiconductor layer among the plurality of first terminal semiconductor layers and the other end in contact with the second terminal semiconductor layer; and a sealing member, which is in direct contact with the upper surface of the second insulating layer.

[0007] According to the semiconductor device disclosed herein, the sealing member is in direct contact with the upper surface of the second insulating layer. Therefore, in the THB test, ions generated in the outermost first terminal semiconductor layer or the second terminal semiconductor layer are dispersed to the sealing member while moving on the upper surface of the second insulating layer. Therefore, corrosion of the metal used in the first terminal electrode layer or the second terminal electrode layer can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 2 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figure 3 It is a plan view showing the structure of a semiconductor device according to the second embodiment.

[0011] Figure 4 It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0012] Figure 5 This is a cross-sectional view of a main part of a semiconductor device according to Embodiment 2 showing a second insulating layer in which a non-reference surface is formed of a recessed portion.

[0013] Figure 6 This is a cross-sectional view of the main part of the semiconductor device according to the second embodiment showing that a part of the non-reference surface formed by the protrusion enters into the first terminal electrode layer and the second insulating layer under the second terminal electrode layer.

[0014] Figure 7 It is a cross-sectional view showing the second insulating layer in which the cross section of the non-reference plane is triangular.

[0015] Figure 8 It is a cross-sectional view showing the second insulating layer in which the non-reference surface has a tapered shape.

[0016] Fig. 9 It is a cross-sectional view showing the second insulating layer in which the non-reference surface is a curved surface.

[0017] Fig.10 It is a cross-sectional view showing the second insulating layer in which the non-reference surface is formed of both convex portions and concave portions.

[0018] Fig.11 When the concavo-convex pattern on the upper surface of the second insulating layer is a stripe pattern Figure 3 Magnified view of area B.

[0019] Fig.12 When the concavo-convex pattern on the upper surface of the second insulating layer is a discontinuous stripe pattern Figure 3 Magnified view of area B.

[0020] Fig.13 When the concavo-convex pattern on the upper surface of the second insulating layer is a checkered pattern Figure 3 Magnified view of area B.

[0021] Fig.14 When the concavo-convex pattern on the upper surface of the second insulating layer is a dot pattern Figure 3 Magnified view of area B.

[0022] Fig.15 It is a plan view showing the structure of the semiconductor device according to the second embodiment when the concavo-convex region of the second insulating layer is provided only at the chip corner.

[0023] Fig.16 This is a plan view of the structure of the semiconductor device according to the second embodiment when the density of the concavo-convex pattern of the second insulating layer in the chip corner is higher than the density of the concavo-convex pattern of the second insulating layer in other regions.

[0024] Fig.17 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0025] Fig.18 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0026] Fig.19 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0027] Fig. 20 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0028] Fig.21 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0029] Fig. 22 This is a cross-sectional view of a main part of a semiconductor device according to a third embodiment.

[0030] Fig.23 This is a cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION

[0031] In the following description, the conductivity type of the semiconductor is the first conductivity type or the second conductivity type. For example, the first conductivity type is the n-type and the second conductivity type is the p-type. However, the first conductivity type may be the p-type and the second conductivity type may be the p-type.

[0032] <A. Implementation method 1>

[0033] <A-1. Structure>

[0034] Figure 1 FIG. 1 is a top view of the semiconductor device 101 according to the first embodiment. Figure 1 As shown, in a plan view, the semiconductor device 101 is divided into an active region 21 in the center, a first terminal region 22 surrounding the active region 21 , and a second terminal region 23 surrounding the first terminal region 22 .

[0035] Figure 2 It is along Figure 1 The semiconductor device 101 is a cross-sectional view of the semiconductor device 101 along the line AA′ of FIG. The semiconductor device 101 includes a semiconductor substrate 1 , a first insulating layer 2 , a second insulating layer 3 , an active region electrode layer 4 , a first terminal electrode layer 5 , a second terminal electrode layer 6 , a back electrode 8 , and a sealing member 9 .

[0036] The semiconductor substrate 1 has a first main surface S1 and a second main surface S2 which is a main surface opposite to the first main surface S1. The semiconductor substrate 1 is a substrate having a thickness of 50 μm to several hundred μm and made of silicon, silicon carbide or gallium nitride. The semiconductor substrate 1 is configured to include a drift layer 10, an active region semiconductor layer 11, a first terminal semiconductor layer 12, a second terminal semiconductor layer 13 and a buffer layer 7.

[0037] The semiconductor substrate 1 includes a drift layer 10 of the second conductivity type. An active region semiconductor layer 11 of the first conductivity type, a plurality of first terminal semiconductor layers 12 of the first conductivity type, and a second terminal semiconductor layer 13 of the second conductivity type are partially formed on the surface layer on the first main surface S1 side of the drift layer 10. The active region semiconductor layer 11 is formed in the active region 21, the plurality of first terminal semiconductor layers 12 are formed in the first terminal region 22, and the second terminal semiconductor layer 13 is formed at the end of the semiconductor substrate 1 in the second terminal region 23. The plurality of first terminal semiconductor layers 12 concentrically surround the active region semiconductor layer 11. The active region semiconductor layer 11 and the plurality of first terminal semiconductor layers 12 contribute to the withstand voltage maintenance by controlling the extension of the depletion layer from the center to the end of the semiconductor device 101. The second terminal semiconductor layer 13 is provided by ion implantation or the like.

[0038] A first insulating layer 2 and a second insulating layer 3 are provided on the first main surface S1 of the semiconductor substrate 1. The first insulating layer 2 is provided in the active region 21 and the first terminal region 22. The second insulating layer 3 is provided in the second terminal region 23. One end of the second insulating layer 3 is in contact with the outermost first terminal semiconductor layer 12, and the other end is in contact with the second terminal semiconductor layer 13. The first insulating layer 2 has an opening on the first terminal semiconductor layer 12.

[0039] The active region electrode layer 4 is an electrode provided on the first main surface S1 of the semiconductor substrate 1 in the active region 21 and is used to conduct the main current of the semiconductor device 101. The active region electrode layer 4 is in contact with the active region semiconductor layer 11 via the opening of the first insulating layer 2. An IGBT (Insulated Gate Bipolar Transistor) or a diode may be provided on the semiconductor substrate 1 in the active region 21 in contact with the active region electrode layer 4.

[0040] The plurality of first terminal electrode layers 5 are provided on the first main surface S1 of the semiconductor substrate 1 in a manner separated from the active region electrode layer 4 in the first terminal region 22. Each of the first terminal electrode layers 5 is electrically separated. Each of the first terminal electrode layers 5 is in contact with the first terminal semiconductor layer 12 via an opening of the first insulating layer 2. The plurality of first terminal electrode layers 5 are field plates that contribute to the withstand voltage maintenance of the semiconductor device 101.

[0041] The second terminal electrode layer 6 is provided on the first main surface S1 of the semiconductor substrate 1 in a manner separated from the active region electrode layer 4 and the first terminal electrode layer 5 in the second terminal region 23. The second insulating layer 3 is provided between the outermost first terminal electrode layer 5 and the second terminal electrode layer 6. One end of the second insulating layer 3 is in contact with the outermost first terminal electrode layer 5, and the other end is in contact with the second terminal electrode layer 6. The second terminal electrode layer 6 is conductively connected to the first terminal semiconductor layer 12. The plurality of first terminal electrode layers 5 and the second terminal electrode layer 6 are made of a metal such as Al.

[0042] A buffer layer 7 of the second conductivity type is provided on the surface layer on the second main surface S2 side of the semiconductor substrate 1. The surface of the buffer layer 7 constitutes the second main surface S2. A back electrode 8 is provided on the second main surface S2 of the semiconductor substrate 1. In addition, a semiconductor layer of the first conductivity type or a semiconductor layer of the second conductivity type may be provided between the buffer layer 7 and the back electrode 8. For example, when the semiconductor device 101 is an IGBT, a collector layer of the first conductivity type is arranged between the buffer layer 7 and the back electrode 8. In addition, when the semiconductor device 101 is a diode, a cathode layer of the second conductivity type is arranged between the buffer layer 7 and the back electrode 8.

[0043] The upper surfaces of the active region electrode layer 4, the first terminal electrode layer 5, the second terminal electrode layer 6, the first insulating layer 2, and the second insulating layer 3 are in direct contact with the sealing member 9. The sealing member 9 is made of an insulating material such as silicone or epoxy resin.

[0044] <A-2. Effect>

[0045] The semiconductor device 101 according to the first embodiment is divided into an active region 21, a first terminal region 22 surrounding the active region 21, and a second terminal region 23 surrounding the first terminal region 22 in a plan view. The semiconductor device 101 has a first main surface S1 and a second main surface S2 which is a main surface opposite to the first main surface S1. The semiconductor substrate 1 includes: a drift layer 10 of a second conductivity type; a plurality of first terminal semiconductor layers 12 of a first conductivity type provided on the surface of the drift layer 10 on the first main surface S1 side in the first terminal region 22; and a second terminal semiconductor layer 13 of a second conductivity type provided on the surface of the drift layer 10 on the first main surface S1 side at an end of the semiconductor substrate 1 in the second terminal region 23. The semiconductor device 101 comprises: a first insulating layer 2, which is arranged on the first main surface S1 in the first terminal region 22; a plurality of first terminal electrode layers 5, which are arranged on the first main surface S1 and are electrically connected to the plurality of first terminal semiconductor layers 12 via openings in the first insulating layer 2; a second terminal electrode layer 6, which is arranged on the first main surface S1 and is in contact with the second terminal semiconductor layer 13; a second insulating layer 3, which is arranged on the first main surface S1, one end of which is in contact with the outermost first terminal semiconductor layer 12 among the plurality of first terminal semiconductor layers 12, and the other end of which is in contact with the second terminal semiconductor layer 13; and a sealing member 9, which is in direct contact with the upper surface of the second insulating layer 3.

[0046] According to the above configuration, ions generated in the outermost first terminal electrode layer 5 or second terminal electrode layer 6 are dispersed into the sealing member 9 while moving on the surface of the second insulating layer 3. Therefore, it is possible to suppress corrosion of the metal used for the first terminal electrode layer 5 or the second terminal electrode layer 6. In addition, since it is unnecessary to form a protective film between the second insulating layer 3 and the sealing member 9, it is possible to suppress manufacturing costs.

[0047] <B. Implementation method 2>

[0048] <B-1. Structure>

[0049] Figure 3 It is a top view of the semiconductor device 102 according to the second embodiment. Figure 4 It is along Figure 3 The semiconductor device 102 is a cross-sectional view of the semiconductor device 102 taken along the line AA′. The semiconductor device 102 is different from the semiconductor device 101 according to the first embodiment in that the upper surface of the second insulating layer 3 has a concavo-convex region 30 having a concavo-convex shape. Figure 3 In FIG. 1 , the uneven area 30 is shaded in a pear-skin manner.

[0050] Specifically, the upper surface of the second insulating layer 3 is configured to include a reference surface 31 at the same height as the upper surface of the first insulating layer 2 and a non-reference surface 32 formed by a convex portion protruding from the reference surface 31. The upper surface of the second insulating layer 3 is formed into a concavo-convex shape by the reference surface 31 and the non-reference surface 32. The region formed into a concavo-convex shape in the upper surface of the second insulating layer 3 is referred to as a concavo-convex region 30. In addition, the second insulating layer 3 needs to have a film thickness in the reference surface 31 to a degree that can maintain insulation from the semiconductor substrate 1.

[0051] like Figure 3 As shown, the concavo-convex region 30 exists over the entire region of the second terminal region 23 so as to surround the first terminal region 22 .

[0052] <B-2. Concavo-convex shape of second insulating layer>

[0053] The concavo-convex shape of the second insulating layer 3 can be conceived in various shapes. Figure 4 In the embodiment, the non-reference surface 32 is formed by a convex portion protruding from the reference surface 31. However, it is also possible to Figure 5 As shown, the non-reference surface 32 is formed by a recessed portion recessed from the reference surface 31. In this case, the second insulating layer 3 needs to have a film thickness sufficient to maintain insulation from the semiconductor substrate 1 in the non-reference surface 32.

[0054] In the case where the non-reference surface 32 is formed by a convex portion protruding from the reference surface 31, as shown in FIG. Figure 6 As shown, the protrusions at both ends of the second insulating layer 3 can enter under the outermost first terminal electrode layer 5 and the second terminal electrode layer 6 .

[0055] exist Figures 4 to 6 In the embodiment, the cross-sectional shape of the non-reference surface 32 of the second insulating layer 3 is a rectangle. However, the cross-sectional shape of the non-reference surface 32 may also be as follows: Figure 7 As shown, it is a triangle, or it can be Figure 8 In addition, as shown in Fig. 9 As shown, the non-reference surface 32 may also be a curved surface. Fig. 9 In the figure, the non-reference surface 32 is formed by both a convex portion and a concave portion relative to the reference surface 31 . Fig.10 The example shown is that the non-reference surface 32 is formed of both a convex portion and a concave portion with respect to the reference surface 31 , and the convex portion or the concave portion forming the non-reference surface 32 is rectangular in cross-sectional view.

[0056] <B-3. Arrangement pattern of non-reference surface>

[0057] The concavo-convex region 30 has a reference surface 31 and a non-reference surface 32. In the concavo-convex region 30, the non-reference surface 32 can be arranged in various patterns. Figure 3 In FIG. 1 , a portion of the concavo-convex region 30 is shown as region B. Fig.11 yes Figure 3 A magnified view of area B. Fig.11 In the embodiment, the non-reference surface 32 is arranged in a stripe pattern. Here, the thickness, length, number and interval of the stripe pattern are not limited to those shown in the figure.

[0058] You can also Fig.12 As shown, the non-reference surface 32 is Fig.11 The stripe pattern is configured by missing a part of the pattern, the so-called incomplete stripe pattern. Fig.12 In the figure, the three patterns other than the left end of the four patterns of the non-reference surface 32 are not completely continuous patterns in the vertical direction of the figure, and are interrupted at least in one place. The missing parts of the patterns of these non-reference surfaces 32 are not limited to Fig.12 The situation shown.

[0059] You can also Fig.13 As shown, the non-reference surface 32 is configured in a rectangular dot pattern. The size of the dots or the positional relationship between adjacent patterns is not limited to Fig.13 The situation shown. Fig.13 In the figure, the patterns of adjacent non-reference surfaces 32 are connected, and the reference surface 31 is surrounded by four patterns of non-reference surfaces 32. However, the patterns of adjacent non-reference surfaces 32 may not be connected. In addition, the shape of the dot pattern is not limited to a rectangle, and may also be a polygon.

[0060] You can also Fig.14 As shown, the non-reference surface 32 is configured with a circular dot pattern. In addition, an elliptical dot pattern can be used instead of a circular dot pattern. The size of the dots or the positional relationship between adjacent patterns is not limited to Fig.14 The situation shown. Fig.14 In the embodiment, the patterns of adjacent non-reference surfaces 32 are not connected, but may be connected.

[0061] <B-4. Arrangement of concave and convex areas>

[0062] exist Figure 3 In the embodiment, the concavo-convex region 30 exists over the entire area of ​​the second terminal region 23 in a manner surrounding the first terminal region 22. However, the concavo-convex region 30 may be provided only in a part of the second terminal region 23. For example, Fig.15 As shown, the concavo-convex region 30 is provided only at the corner of the semiconductor device 102 in the second terminal region 23. By providing the concavo-convex region 30 at the corner where a high electric field is likely to be generated, the damage or increase of leakage current caused by the THB test can be effectively suppressed and delayed. In addition, the concavo-convex region 30 can also be provided at other places other than the corner as long as it is a place where a high electric field is likely to be generated.

[0063] You can also Fig.16 As shown, after the concavoconvex region 30 is arranged in the entire area of ​​the second terminal region 23, the corner is made into a high-density concavoconvex region 30a having a higher density of concavoconvex patterns than other concavoconvex regions 30. In addition, the high-density concavoconvex region 30a can be set in other places other than the corners as long as it is a place where a high electric field is easily generated.

[0064] <B-5. Manufacturing process>

[0065] The following Figure 4 The second insulating layer 3 having the non-reference surface 32 formed by the protrusion with respect to the reference surface 31 shown in the figure and the formation process of its periphery will be described.

[0066] First, if Fig.17 As shown, a first terminal semiconductor layer 12 and a second terminal semiconductor layer 13 are formed on the surface of the first main surface S1 of the semiconductor substrate 1 having the drift layer 10. Then, a second insulating layer 3 is formed on the first main surface S1 of the semiconductor substrate 1. In addition, the second insulating layer 3 may be formed before the first terminal semiconductor layer 12 and the second terminal semiconductor layer 13 are formed.

[0067] Next, if Fig.18 As shown in FIG. 1 , a resist film 14 having an arbitrary opening is formed on the second insulating layer 3. In the case of forming the second insulating layer 3 having a non-reference surface 32 formed by a recessed portion relative to the reference surface 31, Fig.18 The pattern of the resist film 14 shown may be reversed.

[0068] Then, if Fig.19 As shown, a portion of the thickness of the second insulating layer 3 in the opening of the resist film 14 is removed. At this time, the second insulating layer 3 in the opening of the resist film 14 needs to have a film thickness that can maintain insulation from the semiconductor substrate 1. This treatment is a general half-etching or etching, and can be either a wet or dry method. Through this treatment, the upper surface of the second insulating layer 3 in the opening of the resist film 14 becomes a reference surface 31, and the upper surface of the second insulating layer 3 directly below the resist film 14 becomes a non-reference surface 32.

[0069] Next, the resist film 14 is removed to obtain Fig. 20 The structure shown.

[0070] Then, the first terminal electrode layer 5 and the second terminal electrode layer 6 are formed separately to obtain Fig.21 The structure shown.

[0071] The above process is the simplest method for forming a concavo-convex shape on the upper surface of the second insulating layer 3. In addition, although the number of man-hours increases, the concavo-convex shape of the second insulating layer 3 can be formed using the LOCOS (LOCal Oxidation of Silicon) process. In addition, by forming the second insulating layer 3 by a deposition process of a rough surface and roughening the surface of the flat second insulating layer 3 formed once by etching, although a deep concavo-convex shape cannot be obtained, the concavo-convex shape of the second insulating layer 3 can be formed simply.

[0072] <B-6. Effect>

[0073] In the semiconductor device 102 according to the second embodiment, the upper surface of the second insulating layer 3 has a concavo-convex region 30 in a concavo-convex shape in cross-sectional view. Therefore, according to the semiconductor device 102, in addition to the effect of the semiconductor device 101 according to the first embodiment, the following effect can be obtained. That is, since the upper surface of the second insulating layer 3 is in a concavo-convex shape, the distance that the melt ionized by the corrosion of the outermost first terminal electrode layer 5 or the second terminal electrode layer 6 due to the test load during the THB test moves between the outermost first terminal electrode layer 5 and the second terminal electrode layer 6 by the voltage bias becomes longer. As a result, it is possible to suppress or delay the destruction or increase of the leakage current caused by the THB test.

[0074] <C. Implementation method 3>

[0075] <C-1. Structure>

[0076] The top view of the semiconductor device 103 according to the third embodiment is shown in FIG. Figure 3 As shown, this is the same as the semiconductor device 102 according to the second embodiment. Fig. 22 It is along Figure 3 A cross-sectional view of the semiconductor device 103 taken along line AA′ of FIG. The semiconductor device 103 is different from the semiconductor device 102 according to the second embodiment in that a plurality of third insulating layers 15 are discretely formed on the flat upper surface of the second insulating layer 3. That is, in the semiconductor device 103, a concave-convex shape is formed by the flat upper surface of the second insulating layer 3 and the plurality of third insulating layers 15. Although a plurality of third insulating layers 15 are used here, other insulating layers may be provided on the flat upper surface of the second insulating layer 3 separately from the third insulating layer 15. In addition, the number of other insulating layers that are provided in contact with each other on the third insulating layer 15 may be increased. It is sufficient to compare the advantage of improved tolerance in the THB test and the disadvantage of increased number of steps to decide which insulating layer to use.

[0077] <C-2. Effect>

[0078] In the semiconductor device 103 according to the third embodiment, the upper surface of the second insulating layer 3 is flat, and a plurality of third insulating layers are discretely provided on the upper surface of the second insulating layer 3. With this structure, since a concavo-convex shape is formed based on the upper surface of the second insulating layer 3 and the third insulating layer, the same effect as that of the semiconductor device 102 according to the second embodiment in which the upper surface of the second insulating layer 3 is a concavo-convex shape can be obtained.

[0079] <D. Implementation method 4>

[0080] <D-1. Structure>

[0081] The top view of the semiconductor device 104 according to the fourth embodiment is shown in FIG. Figure 3 As shown, this is the same as the semiconductor device 102 according to the second embodiment. Fig.23 It is along Figure 3 The semiconductor device 104 is a cross-sectional view of the semiconductor device 104 along the line AA′. The semiconductor device 104 is different from the semiconductor device 102 according to the second embodiment in that the first insulating layer 2 has protrusions 16 on the upper surface between the active region electrode layer 4 and the first terminal electrode layer 5 and between adjacent first terminal electrode layers 5. The number of protrusions 16 of the first insulating layer 2 is not limited to Fig.23 It is not necessary to provide the projections 16 between the active region electrode layer 4 and the first terminal electrode layer 5 and between adjacent first terminal electrode layers 5 .

[0082] <D-2. Effect>

[0083] In the semiconductor device 104 according to the fourth embodiment, the semiconductor substrate 1 includes an active region semiconductor layer 11 of the first conductivity type provided on the surface layer on the first main surface S1 side of the drift layer 10 in the active region 21. The semiconductor device 104 includes an active region electrode layer 4 provided on the first main surface S1 and conductively connected to the active region semiconductor layer 11. The upper surface of the first insulating layer 2 has a convex portion 16 in at least one of the active region electrode layer 4 and the first terminal electrode layer 5 and between adjacent first terminal electrode layers 5. According to the above structure, the distance between the active region electrode layer 4 and the first terminal electrode layer 5 or the distance between the first terminal electrode layers 5 can be specified by the width of the convex portion 16 of the first insulating layer 2. These distances are important design parameters for maintaining the withstand voltage. If these distances become smaller, the bridging of the corrosive products will be advanced. However, by making the upper surface of the second insulating layer 3 concave and convex, the THB tolerance can be maintained or improved. Therefore, the first terminal region 22 can be designed to be dedicated to the withstand voltage maintenance and the size can be freely designed.

[0084] Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments and the like without departing from the scope described in the scope of claims for protection of the present application.

[0085] Hereinafter, each aspect of the present disclosure will be collectively described as a supplementary note.

[0086] (Note 1)

[0087] A semiconductor device, wherein:

[0088] The active region is divided into an active region, a first terminal region surrounding the active region, and a second terminal region surrounding the first terminal region in a plan view.

[0089] and comprising a semiconductor substrate having a first main surface and a second main surface which is a main surface opposite to the first main surface,

[0090] The semiconductor substrate comprises:

[0091] a drift layer of a second conductivity type;

[0092] a plurality of first-conductivity-type first-termination semiconductor layers provided on a surface layer on the first main surface side of the drift layer in the first-termination region; and

[0093] a second conductive type second termination semiconductor layer provided on a surface layer on the first main surface side of the drift layer at an end portion of the semiconductor substrate in the second termination region;

[0094] The semiconductor device comprises:

[0095] a first insulating layer disposed on the first main surface in the first terminal region;

[0096] A plurality of first terminal electrode layers are provided on the first main surface and are electrically connected to the plurality of first terminal semiconductor layers via the openings of the first insulating layer;

[0097] A second terminal electrode layer is provided on the first main surface and is electrically connected to the second terminal semiconductor layer;

[0098] a second insulating layer disposed on the first main surface, one end of which is in contact with the outermost first terminal semiconductor layer among the plurality of first terminal semiconductor layers, and the other end of which is in contact with the second terminal semiconductor layer; and

[0099] The sealing member is in direct contact with the upper surface of the second insulating layer.

[0100] (Note 2)

[0101] A semiconductor device according to note 1, wherein:

[0102] The upper surface of the second insulating layer has a concavo-convex region having a concavo-convex shape in cross-sectional view.

[0103] (Note 3)

[0104] A semiconductor device according to note 2, wherein:

[0105] The concavo-convex region includes a reference surface at the same height as the upper surface of the first insulating layer and a non-reference surface formed by a convex portion protruding from the reference surface.

[0106] (Note 4)

[0107] A semiconductor device according to note 2, wherein:

[0108] The concavo-convex region includes a reference surface at the same height as the upper surface of the first insulating layer and a non-reference surface formed by a concave portion recessed from the reference surface.

[0109] (Note 5)

[0110] A semiconductor device according to note 3, wherein:

[0111] The protrusions located at both ends of the second insulating layer are inserted under the outermost first terminal electrode layer among the plurality of first terminal electrode layers and the second terminal electrode layer.

[0112] (Note 6)

[0113] A semiconductor device as described in any one of Notes 3 to 5, wherein:

[0114] The cross-sectional shape of the non-reference surface is a rectangle.

[0115] (Note 7)

[0116] A semiconductor device as described in any one of Notes 3 to 5, wherein:

[0117] The cross-sectional shape of the non-reference surface is a triangle.

[0118] (Note 8)

[0119] A semiconductor device as described in any one of Notes 3 to 5, wherein:

[0120] The cross-sectional shape of the non-reference surface is tapered.

[0121] (Note 9)

[0122] A semiconductor device as described in any one of Notes 3 to 5, wherein:

[0123] The above-mentioned non-reference surface is a curved surface.

[0124] (Note 10)

[0125] A semiconductor device as described in any one of Notes 3 to 9, wherein:

[0126] The non-reference surfaces are arranged in a stripe pattern.

[0127] (Note 11)

[0128] A semiconductor device as described in any one of Notes 3 to 9, wherein:

[0129] The non-reference surfaces are arranged in an incomplete stripe pattern.

[0130] (Note 12)

[0131] A semiconductor device as described in any one of Notes 3 to 9, wherein:

[0132] The non-reference surface is arranged in a polygonal dot pattern.

[0133] (Note 13)

[0134] A semiconductor device as described in any one of Notes 3 to 9, wherein:

[0135] The non-reference surface is arranged in a circular or elliptical dot pattern.

[0136] (Note 14)

[0137] A semiconductor device as described in any one of Notes 2 to 13, wherein:

[0138] The concavo-convex region is provided only at a corner portion of the second terminal region.

[0139] (Note 15)

[0140] A semiconductor device as described in any one of Notes 2 to 13, wherein:

[0141] The concavo-convex region is provided in the entire region of the second terminal region.

[0142] The concavo-convex region provided at the corner of the second terminal region is a high-density concavo-convex region having a higher density of concavo-convex patterns than the other concavo-convex regions.

[0143] (Note 16)

[0144] A semiconductor device according to note 1, wherein:

[0145] The upper surface of the second insulating layer is flat.

[0146] The invention further includes a plurality of third insulating layers discretely provided on the upper surface of the second insulating layer.

[0147] (Note 17)

[0148] A semiconductor device as described in any one of Notes 1 to 16, wherein:

[0149] The semiconductor substrate includes an active region semiconductor layer of a first conductivity type provided on a surface layer on the first main surface side of the drift layer in the active region.

[0150] The semiconductor device comprises an active region electrode layer provided on the first main surface and electrically connected to the active region semiconductor layer.

[0151] The first insulating layer has a convex portion on its upper surface at least between the active region electrode layer and the first terminal electrode layer and between adjacent first terminal electrode layers.

[0152] (Note 18)

[0153] A method for manufacturing a semiconductor device, wherein the semiconductor device is divided into an active region, a first terminal region surrounding the active region, and a second terminal region surrounding the first terminal region in a plan view, wherein:

[0154] preparing a semiconductor substrate having a drift layer of a second conductivity type and having a first main surface and a second main surface which is a main surface opposite to the first main surface,

[0155] In the first termination region, a plurality of first termination semiconductor layers of the first conductivity type are formed on a surface layer of the drift layer on the first main surface side.

[0156] A second termination semiconductor layer of a second conductivity type is formed on a surface layer of the drift layer on the first main surface side at an end portion of the semiconductor substrate in the second termination region.

[0157] In the first terminal region, a first insulating layer is formed on the first main surface.

[0158] forming a plurality of first terminal electrode layers on the first main surface, the first terminal electrode layers being electrically connected to the plurality of first terminal semiconductor layers via the openings of the first insulating layer;

[0159] forming a second terminal electrode layer on the first main surface and electrically connected to the second terminal semiconductor layer;

[0160] forming a second insulating layer on the first main surface, the second insulating layer having one end in contact with the outermost first terminal semiconductor layer among the plurality of first terminal semiconductor layers and the other end in contact with the second terminal semiconductor layer;

[0161] The upper surface of the second insulating layer is sealed with a sealing material.

[0162] Description of Reference Numerals

[0163] 1…semiconductor substrate, 2…first insulating layer; 3…second insulating layer; 4…active region electrode layer; 5…first terminal electrode layer; 6…second terminal electrode layer; 8…back electrode; 9…sealing member; 10…drift layer; 11…active region semiconductor layer; 12…first terminal semiconductor layer; 13…second terminal semiconductor layer; 14…resist film; 15…third insulating layer; 16…convex portion; 21…active region; 22…first terminal region; 23…second terminal region; 30…concave-convex region; 31…reference plane; 32…non-reference plane; 101-104…semiconductor device.

Claims

1. A semiconductor device, characterized in that: The active region is divided into an active region, a first terminal region surrounding the active region, and a second terminal region surrounding the first terminal region in a plan view. and comprising a semiconductor substrate having a first main surface and a second main surface which is a main surface opposite to the first main surface, The semiconductor substrate comprises: a drift layer of a second conductivity type; a plurality of first-conductivity-type first-termination semiconductor layers provided on a surface layer on the first main surface side of the drift layer in the first-termination region; and a second conductive type second termination semiconductor layer provided on a surface layer on the first main surface side of the drift layer at an end portion of the semiconductor substrate in the second termination region; The semiconductor device comprises: a first insulating layer disposed on the first main surface in the first terminal region; A plurality of first terminal electrode layers are provided on the first main surface and are electrically connected to the plurality of first terminal semiconductor layers via the openings of the first insulating layer; A second terminal electrode layer is provided on the first main surface and is electrically connected to the second terminal semiconductor layer; a second insulating layer, disposed on the first main surface, having one end in contact with the outermost first terminal semiconductor layer among the plurality of first terminal semiconductor layers, and the other end in contact with the second terminal semiconductor layer; as well as The sealing member is in direct contact with the upper surface of the second insulating layer.

2. The semiconductor device according to claim 1, wherein: The upper surface of the second insulating layer has a concavo-convex region having a concavo-convex shape in cross-sectional view.

3. The semiconductor device according to claim 2, wherein: The concavo-convex region includes a reference surface having the same height as the upper surface of the first insulating layer and a non-reference surface formed by a convex portion protruding from the reference surface.

4. The semiconductor device according to claim 2, wherein: The concavo-convex region includes a reference surface at the same height as the upper surface of the first insulating layer and a non-reference surface formed by a concave portion recessed from the reference surface.

5. The semiconductor device according to claim 3, wherein: The protrusions located at both ends of the second insulating layer are inserted under the outermost first terminal electrode layer among the plurality of first terminal electrode layers and the second terminal electrode layer.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that The cross-sectional shape of the non-reference surface is a rectangle.

7. The semiconductor device according to any one of claims 3 to 5, characterized in that The cross-sectional shape of the non-reference surface is a triangle.

8. The semiconductor device according to any one of claims 3 to 5, characterized in that The cross-sectional shape of the non-reference surface is tapered.

9. The semiconductor device according to any one of claims 3 to 5, characterized in that The above-mentioned non-reference surface is a curved surface.

10. The semiconductor device according to any one of claims 3 to 9, wherein: The non-reference surfaces are arranged in a stripe pattern.

11. The semiconductor device according to any one of claims 3 to 9, wherein: The non-reference surfaces are arranged in an incomplete stripe pattern.

12. The semiconductor device according to any one of claims 3 to 9, wherein: The non-reference surface is arranged in a polygonal dot pattern.

13. The semiconductor device according to any one of claims 3 to 9, characterized in that The non-reference surface is arranged in a circular or elliptical dot pattern.

14. The semiconductor device according to any one of claims 2 to 13, characterized in that The concavo-convex region is provided only at a corner portion of the second terminal region.

15. The semiconductor device according to any one of claims 2 to 13, characterized in that The concavo-convex region is provided in the entire region of the second terminal region. The concavo-convex region provided at the corner of the second terminal region is a high-density concavo-convex region having a higher density of concavo-convex patterns than the other concavo-convex regions.

16. The semiconductor device according to claim 1, wherein: The upper surface of the second insulating layer is flat. The invention further includes a plurality of third insulating layers discretely provided on the upper surface of the second insulating layer.

17. The semiconductor device according to any one of claims 1 to 16, wherein: The semiconductor substrate includes an active region semiconductor layer of a first conductivity type provided on a surface layer on the first main surface side of the drift layer in the active region. The semiconductor device comprises an active region electrode layer provided on the first main surface and electrically connected to the active region semiconductor layer. The first insulating layer has a convex portion on its upper surface at least between the active region electrode layer and the first terminal electrode layer and between adjacent first terminal electrode layers.

18. A method for manufacturing a semiconductor device, wherein the semiconductor device is divided into an active region, a first terminal region surrounding the active region, and a second terminal region surrounding the first terminal region in a plan view, characterized in that: preparing a semiconductor substrate having a drift layer of a second conductivity type and having a first main surface and a second main surface which is a main surface opposite to the first main surface, In the first termination region, a plurality of first termination semiconductor layers of the first conductivity type are formed on a surface layer of the drift layer on the first main surface side. A second termination semiconductor layer of a second conductivity type is formed on a surface layer of the drift layer on the first main surface side at an end portion of the semiconductor substrate in the second termination region. In the first terminal region, a first insulating layer is formed on the first main surface. forming a plurality of first terminal electrode layers on the first main surface, the first terminal electrode layers being electrically connected to the plurality of first terminal semiconductor layers via the openings of the first insulating layer; forming a second terminal electrode layer on the first main surface and electrically connected to the second terminal semiconductor layer; forming a second insulating layer on the first main surface, the second insulating layer having one end in contact with the outermost first terminal semiconductor layer among the plurality of first terminal semiconductor layers and the other end in contact with the second terminal semiconductor layer; The upper surface of the second insulating layer is sealed with a sealing material.

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