Power device and preparation method thereof

Abstract

The invention discloses a power device and a preparation method thereof, and the power device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged, the semiconductor body also comprises a base region and a first region, and the conduction type of the first region is opposite to the conduction type of the base region; the first surface is provided with at least one gate trench group, and the gate trench group comprises at least two gate trenches; each gate trench extends into the semiconductor body from the first surface; the semiconductor body comprises a second region, and the second region and the base region are the same in conduction type; the second regions are located between the base region and the second surface and located on the two sides of each gate trench group; the vertical projection of the second region on the second surface is not overlapped with the vertical projection of the gate trench on the second surface; the gate structure is located in the gate trench; the source is located on one side of the first surface away from the second surface; the drain is located on one side of the second surface away from the first surface. According to the invention, forward on-resistance and reverse recovery noise can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a power device and a preparation method thereof. Background Art

[0002] In recent years, power devices have been used in various fields such as automobiles, industry, and infrastructure. In particular, it is hoped that high-efficiency power devices will be used in electric vehicles (EVs) to contribute to society. For power metal oxide semiconductor field effect transistors (MOSFETs), low on-resistance is one of the most important parameters for reducing conduction losses and thus achieving low power consumption and high efficiency. In order to achieve low on-resistance, charge compensation structures such as superjunction (SJ) MOS and vertical field plate (FP) MOS have been proposed as methods to surpass the limitations of silicon (Si); however, for superjunction MOS structures, due to the increase in reverse recovery current during switching, superjunction MOS has the disadvantage of relatively high recovery noise. The reason is that under the action of drain-source voltage, the drain-source capacitance of superjunction MOS changes dramatically, which leads to a fast reverse recovery current and large reverse recovery noise. Summary of the invention

[0003] The invention provides a power device and a preparation method thereof, which can reduce forward conduction resistance and reverse recovery noise.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a base region and a first region, the conductivity type of the first region being opposite to the conductivity type of the base region; the first region being located on the first surface, and the base region being located on a side of the first region away from the first surface; at least one gate trench group being arranged on the first surface, the gate trench group comprising at least two gate trenches; each gate trench extending from the first surface into the semiconductor body; the semiconductor body comprising a second region, the conductivity type of the second region being the same as that of the base region; the second region being located between the base region and the second surface, and being located on both sides of each gate trench group; the vertical projection of the second region on the second surface does not overlap with the vertical projection of the gate trench on the second surface;

[0006] A gate structure, the gate structure is located in the gate trench;

[0007] A source electrode, the source electrode is located on a side of the first surface away from the second surface;

[0008] The drain is located on a side of the second surface away from the first surface.

[0009] Optionally, the power device further includes:

[0010] a substrate, the substrate being located on a side of the drain electrode adjacent to the second surface;

[0011] The distance between the second region and the surface of the base region away from the first region is the same as the distance between the second region and the second surface.

[0012] Optionally, the doping concentration of the second region is greater than the doping concentration of the base region.

[0013] Optionally, the semiconductor body further includes a third region, the third region is located between adjacent gate trenches and between the base region and the first region; the third region and the base region have the same conductivity type.

[0014] Optional power devices also include:

[0015] The first insulating layer is located between the first region and the source electrode; the source electrode is in contact with the third region.

[0016] Optionally, the gate structure includes a second insulating layer and a gate, and the second insulating layer is located between the gate and the gate trench.

[0017] Optionally, the distance between adjacent second regions is 7 μm-9 μm;

[0018] The distance between the second region and the surface of the base region away from the first region is 2 μm-4 μm.

[0019] According to another aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0020] A semiconductor body is formed, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a base region and a first region, wherein the conductivity type of the first region is opposite to that of the base region; the first region is located on the first surface, and the base region is located on a side of the first region away from the first surface; at least one gate trench group is arranged on the first surface, and the gate trench group comprises at least two gate trenches; each gate trench extends from the first surface into the semiconductor body; the semiconductor body comprises a second region, and the conductivity type of the second region is the same as that of the base region; the second region is located between the base region and the second surface, and is located on both sides of each gate trench group; and a vertical projection of the second region on the second surface does not overlap with a vertical projection of the gate trench on the second surface;

[0021] forming a gate structure in the gate trench;

[0022] forming a source electrode on a side of the first surface away from the second surface;

[0023] A drain is formed on a side of the second surface away from the first surface.

[0024] Optionally, before forming the semiconductor body, the method further includes:

[0025] providing a substrate;

[0026] Forming a semiconductor body, comprising:

[0027] forming an epitaxial layer; a surface of the epitaxial layer away from the substrate is a first surface;

[0028] forming a second region;

[0029] A base region and a first region are formed on the first surface; the conductivity type of the first region is opposite to that of the base region; the first region is located on the first surface, and the base region is located on a side of the first region away from the first surface; and the conductivity type of the second region is the same as that of the base region;

[0030] At least one gate trench group is formed on the first surface; the gate trench group includes at least two gate trenches; each gate trench extends from the first surface into the semiconductor body; the second region is located between the base region and the second surface, and is located on both sides of each gate trench group; the vertical projection of the second region on the second surface does not overlap with the vertical projection of the gate trench on the second surface.

[0031] Optionally, forming a gate structure in the gate trench includes:

[0032] forming a second insulating layer in the gate trench; the second insulating layer covers the bottom and sidewalls of the gate trench;

[0033] A gate is formed on a side of the second insulating layer away from the second surface, and the gate covers the second insulating layer.

[0034] The power device provided by the embodiment of the present invention includes a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a base region and a first area, the conductivity type of the first area is opposite to the conductivity type of the base region; the first area is located on the first surface, and the base region is located on a side of the first area away from the first surface; the first surface is provided with at least one gate trench group, the gate trench group includes at least two gate trenches; each gate trench extends from the first surface into the semiconductor body; the semiconductor body includes a second area, the second area has the same conductivity type as the base area; the second area is located between the base region and the second surface, and is located on both sides of each gate trench group; the vertical projection of the second area on the second surface does not overlap with the vertical projection of the gate trench on the second surface; the gate structure, the gate structure is located in the gate trench; the source, the source is located on the side of the first surface away from the second surface; the drain, the drain is located on the side of the second surface away from the first surface. In an embodiment of the present invention, the gate trench group includes at least two gate trenches, which can increase the conduction channel and improve the current density, thereby reducing the on-resistance; when the power device is reversely conducted, since the second region is located between the base region and the second surface and is located on both sides of each gate trench group, the total area of ​​the second region and the base region is small, the source-drain capacitance gradually decreases with the source-drain voltage and changes slowly, so that better recovery characteristics can be obtained and reverse recovery noise can be reduced.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a structural schematic diagram of a power device in the prior art.

[0038] Figure 2 It is a schematic diagram of the structure of a power device provided by an embodiment of the present invention.

[0039] Figure 3 This is a curve of source-drain voltage and source-drain capacitance provided by an embodiment of the present invention.

[0040] Figure 4 This is a time and leakage current variation curve provided by an embodiment of the present invention.

[0041] Figure 5 It is a flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0042] Figure 6 yes Figure 5 A detailed flow chart included in S110. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0045] The inventor found that: in the prior art, Figure 1 This is a schematic diagram of the structure of a power device in the prior art. Figure 1 , the source-drain voltage V DS At zero bias, the base region 30 is in contact with the P column 31, the base region 30 is a P base region, and the areas of the base region 30 and the P column 31 are continuous, resulting in a large area of ​​the base region 30 and the P column 31, and the source-drain capacitance C DS However, after a certain positive bias, it will cause C DS Rapid decline. DS This rapid change in will lead to a deterioration in the restored noise characteristics.

[0046] In order to solve the problem of restoration noise degradation, an embodiment of the present invention provides a power device, Figure 2 is a schematic diagram of a power device provided by an embodiment of the present invention, with reference to Figure 2 , power devices include:

[0047] A semiconductor body 100, the semiconductor body 100 includes a first surface 01 and a second surface 02 arranged opposite to each other, the semiconductor body 100 also includes a base region 30 and a first region 40, the conductivity type of the first region 40 is opposite to the conductivity type of the base region 30; the first region 40 is located on the first surface 01, and the base region 30 is located on a side of the first region 40 away from the first surface 01; the first surface 01 is provided with at least one gate trench group, the gate trench group includes at least two gate trenches 03; each gate trench 03 extends from the first surface 01 to the semiconductor body 100; the semiconductor body 100 includes a second region 50, the second region 50 has the same conductivity type as the base region 30; the second region 50 is located between the base region 30 and the second surface 02, and is located on both sides of each gate trench group; the vertical projection of the second region 50 on the second surface 02 does not overlap with the vertical projection of the gate trench 70 on the second surface 02;

[0048] A gate structure 70, the gate structure 70 is located in the gate trench 03;

[0049] A source electrode 80 , the source electrode 80 is located on a side of the first surface 01 away from the second surface 02 ;

[0050] The drain electrode 90 is located on a side of the second surface 02 away from the first surface 01 .

[0051] Among them, the power device can be a trench MOSFET. The embodiment of the present invention is applicable to trench MOSFETs of 60V and below. The power device also includes a substrate 10; if the device is an N-type device, the conductivity type of the first region 40 is N-type, and the conductivity type of the base region 30 and the second region 50 is P-type; if the device is a P-type device, the conductivity type of the first region 40 is P-type, and the conductivity type of the base region 30 and the second region 50 is N-type. Exemplarily, the second region 50 can be a floating P column. The first region 40 can be an N+ region, the third region 60 can be a P+ region, and the base region 30 can be a P base region.

[0052] Specifically, the second region 50 is located between the base region 30 and the second surface 02, the second region 50 is not in contact with the base region 30, the size of each second region 50 can be 2μm*3μm, the first surface 01 is provided with at least one gate groove group, the second region 50 is located on both sides of the gate groove group, when the power device is forward-conducted, the gate groove group includes at least two gate grooves 03, which can increase the conduction channel, improve the current density, and thus reduce the on-resistance; when the power device is reverse-conducted, since the total area of ​​the second region 50 and the base region 30 is small, the source-drain voltage V DS Starting from zero bias, a depletion layer appears between the base region 30 and the second region 50, and the source-drain capacitance C DS With V DSGradually changes, therefore, better recovery characteristics can be obtained.

[0053] For example, Figure 2 An N-type MOSFET structure is shown as an example. Figure 2 It includes two gate trench groups, each gate trench group includes two gate trenches 03, a second region 50 is set on both sides of each gate trench group, and adjacent gate trench groups share a second region 50, which can increase the conduction channel and improve the current density, thereby reducing the conduction resistance.

[0054] Figure 3 is a curve of source-drain voltage and source-drain capacitance provided by an embodiment of the present invention, referring to Figure 3 , Figure 3 The horizontal axis is the source-drain voltage V DS , the vertical axis is the source-drain capacitance C DS Density (C DS density), the black line indicates Figure 1 The structure in V DS C when changing DS Density variation curve, the red line represents the embodiment of the present invention Figure 2 The structure in V DS C when changing DS Density change curve; it can be found that the structure in the prior art has C at the positions of black dots 3 and 4 DS Rapid drop and rapid change will lead to the deterioration of the recovery noise characteristics; V DS The same, the V of black point 4 and red point 8 DS The same, but in the embodiment of the present invention Figure 2 In the structure, C at the red dots 7 and 8 DS The change is small, the source-drain capacitance C DS With source-drain voltage V DS Gradual changes can achieve better recovery characteristics.

[0055] Figure 4 is a time-leakage current variation curve provided by an embodiment of the present invention, referring to Figure 4 , Figure 4 The waveform comparison of the existing structure of the reverse recovery of the turn-off device and the structure of the embodiment of the present invention; the horizontal axis is time, and the vertical axis is the leakage current I D , leakage current I D is the reverse recovery current; the black line is the leakage current I when the structure of the embodiment of the present invention changes with time D The red line is the leakage current I of the prior art structure when it changes with time. D The change curve of; in reverse conduction, in the existing structure, C DSIt drops sharply after a certain bias, and the drain waveform becomes faster when turned off; due to the leakage current I D The existing structure has a large switching noise; in the structure provided by the embodiment of the present invention, C DS With V DS The phase gradually decreases, and dIR / dt is suppressed to about half of the conventional structure; since the reverse recovery current is reduced, the reverse recovery waveform is more moderate, and the power device in the embodiment of the present invention has extremely low noise compared with the existing power device.

[0056] The power device provided in the embodiment of the present invention includes a semiconductor body 100, the semiconductor body 100 includes a first surface 01 and a second surface 02 arranged opposite to each other, the semiconductor body 100 also includes a base region 30 and a first region 40, the conductivity type of the first region 40 is opposite to the conductivity type of the base region 30; the first region 40 is located on the first surface 01, and the base region 30 is located on a side of the first region 40 away from the first surface 01; the first surface 01 is provided with at least one gate trench group, the gate trench group includes at least two gate trenches 03; each gate trench 03 extends from the first surface 01 to the semiconductor body 100; the semiconductor body 100 includes a second region 50, the second region 50 and the base region 30 have the same conductivity type; the second region 50 is located between the base region 30 and the second surface 02, and is located on both sides of each gate trench group; the vertical projection of the second region 50 on the second surface 02 does not overlap with the vertical projection of the gate trench 70 on the second surface 02; the gate structure 70, the gate structure 70 is located in the gate trench 03; the source 80, the source 80 is located on the side of the first surface 01 away from the second surface 02; the drain 90, the drain 90 is located on the side of the second surface 02 away from the first surface 01. In the embodiment of the present invention, the gate trench group includes at least two gate trenches 03, which can increase the conduction channel, improve the current density, and thus reduce the on-resistance; when the power device is reversely conducted, since the second region 50 is located between the base region 30 and the second surface 02, and is located on both sides of each gate trench group, the total area of ​​the second region 50 and the base region 30 is small, and the source-drain capacitance C DS With source-drain voltage V DS Gradually decreasing and changing slowly can obtain better recovery characteristics and reduce reverse recovery noise.

[0057] Optional, reference Figure 2 The power device further includes: a substrate 10, which is located on a side of the drain 90 adjacent to the second surface 02; a distance D1 between the second region 50 and the surface of the base region 30 away from the first region 40 is the same as a distance D2 between the second region 50 and the second surface 02.

[0058] The second region 50 can be formed by ion implantation, and the implantation position of the second region 50 can be adjusted by changing the implantation energy of the ion implantation. The longer D1 of the second region 50 is, the smaller the zero bias time C is. DS The smaller it is, the smaller dIR / dt is also. By adjusting the p-column injection energy, the best reverse recovery characteristics can be obtained. By setting the energy of ion injection into the second region so that the distance D1 between the second region 50 and the base region 30 away from the surface of the first region 40 and the distance D2 between the second region 50 and the second surface 02 are the same, the best reverse recovery characteristics can be obtained.

[0059] Optional, reference Figure 2 , the doping concentration of the second region 50 is greater than the doping concentration of the base region 30 .

[0060] The doping concentration of the second region 50 can be 1.6×10 16 cm -3 , the doping concentration of the base region 30 can be 4.4×10 13 cm -3 The semiconductor body also includes an epitaxial layer 20, which has an opposite conductivity type to the second region 50, so that the drift region in the device is composed of regions of different conductivity types. The doping concentration of the second region 50 is greater than the doping concentration of the base region 30, which can increase the doping level of the drift region and further improve the on-resistance of the device, while maintaining the reverse breakdown voltage of the device.

[0061] Optional, reference Figure 2 The semiconductor body 100 further includes a third region 60 , which is located between adjacent gate trenches 03 and between the base region 30 and the first region 40 ; the third region 60 and the base region 30 have the same conductivity type.

[0062] Among them, the third region 60 is located between adjacent gate trenches 03, and the third region 60 is located on the side of the first region 40 away from the first surface 01. The third region 60 has the same conductivity type as the base region 30, and the doping concentration of the third region 60 is different from that of the base region 30. The doping concentration of the third region 60 can be greater than the doping concentration of the base region 30, forming a good ohmic contact.

[0063] Optional, reference Figure 2 The power device further includes: a first insulating layer 101 , the first insulating layer 101 is located between the first region 40 and the source 80 ; the source 80 is in contact with the third region 60 .

[0064] The material of the first insulating layer 101 may be silicon nitride or silicon oxide. The first insulating layer 101 is located on a side of the first region 40 away from the base region 30 . The first insulating layer 101 is used to isolate the gate structure 70 from the source 80 and plays a role of insulating protection.

[0065] Optional, reference Figure 2 The gate structure 70 includes a second insulating layer 71 and a gate 72 , and the second insulating layer 71 is located between the gate 72 and the gate trench 03 .

[0066] The material of the second insulating layer 71 may be silicon oxide; the second insulating layer 71 may be a gate oxide layer, and the material of the gate 72 may be polysilicon.

[0067] Optional, reference Figure 2 , a distance D3 between adjacent second regions 50 is 7 μm-9 μm; a distance D1 between the second region 50 and the surface of the base region 30 away from the first region 40 is 2 μm-4 μm.

[0068] Among them, the distance D3 between adjacent second regions 50 is 7μm-9μm, and exemplarily, the distance D3 between adjacent second regions 50 can be 8μm; the distance D1 between the second region 50 and the surface of the base region 30 away from the first region 40 is 2μm-4μm, and exemplarily, the distance D1 between the second region 50 and the surface of the base region 30 away from the first region 40 can be 3μm; the width of the gate trench 03 in the first direction X can be 0.5μm, the width of the gate trench 03 in the second direction Y can be 2μm, the distance between the bottom of the gate trench 03 and the surface of the base region 30 away from the first region 40 can be 1μm, the distance between the second surface 03 and the surface of the base region 30 away from the first region 40 can be 9μm-15μm, the first direction X is perpendicular to the second direction Y, and the second direction Y is the direction from the first surface 01 to the second surface 02; the integration of the power device can be higher.

[0069] An embodiment of the present invention provides a method for preparing a power device based on the above embodiment, which is used to prepare the power device described in any of the above embodiments; Figure 5 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, with reference to Figure 5 , the preparation method comprises:

[0070] S110. Form a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a base region and a first area, the conductivity type of the first area is opposite to the conductivity type of the base region; the first area is located on the first surface, and the base region is located on a side of the first area away from the first surface; the first surface is provided with at least one gate trench group, the gate trench group comprises at least two gate trenches; each gate trench extends from the first surface into the semiconductor body; the semiconductor body comprises a second area, the conductivity type of the second area is the same as that of the base region; the second area is located between the base region and the second surface, and is located on both sides of each gate trench group; the vertical projection of the second area on the second surface does not overlap with the vertical projection of the gate trench on the second surface.

[0071] S120 , forming a gate structure in the gate trench.

[0072] S130 , forming a source electrode on a side of the first surface away from the second surface.

[0073] S140, forming a drain on a side of the second surface away from the first surface.

[0074] In the preparation method provided by the embodiment of the present invention, the gate trench group includes at least two gate trenches, which can increase the conduction channel and improve the current density, thereby reducing the on-resistance; when the power device is reversely conducted, since the second region is located between the base region and the second surface, and is located on both sides of each gate trench group, the total area of ​​the second region and the base region is small, the source-drain capacitance gradually decreases with the source-drain voltage, and the change is slow, so that better recovery characteristics can be obtained and the reverse recovery noise can be reduced.

[0075] Optionally, before forming the semiconductor body, the method further includes: providing a substrate.

[0076] Figure 6 yes Figure 5 A detailed flow chart included in S110, refer to Figure 6 , S110, forming a semiconductor body, including:

[0077] S111, forming an epitaxial layer; a surface of the epitaxial layer away from the substrate is a first surface.

[0078] Wherein, an epitaxial layer may be formed on the surface of the substrate through an epitaxial process.

[0079] S112. Form a second region.

[0080] The second region 50 may be formed by ion implantation, and P-type ions may be implanted into the second region 50. The doping concentration of the implanted ions may be 1.6×10 16 cm -3 .

[0081] S113, forming a base region and a first area on the first surface; the conductivity type of the first area is opposite to that of the base region; the first area is located on the first surface, and the base area is located on a side of the first area away from the first surface; the second area has the same conductivity type as that of the base area.

[0082] Among them, reference Figure 2 , the base region 30 and the first region 40 are formed by an ion implantation process. For example, ions can be implanted into the position of the base region 30 by an ion implantation process to form the base region 30; ions can be implanted into the position of the first region 40 by an ion implantation process to form the first region 40; P-type ions can be implanted into the base region 30, and N-type ions can be implanted into the first region 40.

[0083] S114. At least one gate trench group is formed on the first surface; the gate trench group includes at least two gate trenches; each gate trench extends from the first surface into the semiconductor body; the second region is located between the base region and the second surface, and is located on both sides of each gate trench group; the vertical projection of the second region on the second surface does not overlap with the vertical projection of the gate trench on the second surface.

[0084] Wherein, at least one gate trench group may be formed by an etching process.

[0085] Optionally, S130, forming a gate structure in the gate trench includes:

[0086] S131, forming a second insulating layer in the gate trench; the second insulating layer covers the bottom and sidewalls of the gate trench;

[0087] S132, forming a gate on a side of the second insulating layer away from the second surface, wherein the gate covers the second insulating layer.

[0088] The second insulating layer may be formed by an oxidation process, and the gate may be formed by a deposition process.

[0089] The method for preparing a power device provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0090] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0091] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a base region and a first region, the conductivity type of the first region being opposite to the conductivity type of the base region; the first region being located on the first surface, the base region being located on a side of the first region away from the first surface; the first surface being provided with at least one gate trench group, the gate trench group comprising at least two gate trenches; Each of the gate trenches extends from the first surface into the semiconductor body; the semiconductor body includes a second region, the second region has the same conductivity type as the base region; the second region is located between the base region and the second surface and is located on both sides of each of the gate trench groups; A vertical projection of the second region on the second surface does not overlap with a vertical projection of the gate trench on the second surface; a gate structure, wherein the gate structure is located in the gate trench; a source electrode, the source electrode being located on a side of the first surface away from the second surface; A drain electrode is located on a side of the second surface away from the first surface.

2. The power device according to claim 1, characterized in that: Also includes: a substrate, the substrate being located on a side of the drain electrode adjacent to the second surface; A distance between the second region and a surface of the base region away from the first region is the same as a distance between the second region and the second surface.

3. The power device according to claim 1, characterized in that: The doping concentration of the second region is greater than the doping concentration of the base region.

4. The power device according to claim 1, characterized in that: The semiconductor body further includes a third region, wherein the third region is located between adjacent gate trenches and between the base region and the first region; the third region and the base region have the same conductivity type.

5. The power device according to claim 4, characterized in that: Also includes: a first insulating layer, wherein the first insulating layer is located between the first region and the source electrode; The source electrode contacts the third region.

6. The power device according to claim 1, characterized in that: The gate structure includes a second insulating layer and the gate, wherein the second insulating layer is located between the gate and the gate trench.

7. The power device according to claim 1, characterized in that: The distance between adjacent second regions is 7 μm-9 μm; The distance between the second region and a surface of the base region away from the first region is 2 μm-4 μm.

8. A method for preparing a power device, characterized in that: include: A semiconductor body is formed, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a base region and a first region, the conductivity type of the first region is opposite to the conductivity type of the base region; the first region is located on the first surface, and the base region is located on a side of the first region away from the first surface; the first surface is provided with at least one gate trench group, and the gate trench group comprises at least two gate trenches; Each of the gate trenches extends from the first surface into the semiconductor body; the semiconductor body includes a second region, the second region and the base region have the same conductivity type; the second region is located between the base region and the second surface, and is located on both sides of each of the gate trench groups; a vertical projection of the second region on the second surface does not overlap with a vertical projection of the gate trench on the second surface; forming a gate structure in the gate trench; forming a source electrode on a side of the first surface away from the second surface; A drain is formed on a side of the second surface away from the first surface.

9. The method for preparing a power device according to claim 8, characterized in that: Before forming the semiconductor body, it also includes: providing a substrate; Forming a semiconductor body, comprising: forming an epitaxial layer; a surface of the epitaxial layer away from the substrate is a first surface; forming a second region; A base region and a first region are formed on the first surface; the conductivity type of the first region is opposite to that of the base region; the first region is located on the first surface, and the base region is located on a side of the first region away from the first surface; the second region has the same conductivity type as that of the base region; At least one gate trench group is formed on the first surface; the gate trench group includes at least two gate trenches; each of the gate trenches extends from the first surface into the semiconductor body; the second region is located between the base region and the second surface, and is located on both sides of each of the gate trench groups; a vertical projection of the second region on the second surface does not overlap with a vertical projection of the gate trench on the second surface.

10. The method for preparing a power device according to claim 8, characterized in that: A gate structure is formed in the gate trench, comprising: forming a second insulating layer in the gate trench; the second insulating layer covers the bottom and sidewalls of the gate trench; A gate is formed on a side of the second insulating layer away from the second surface, and the gate covers the second insulating layer.

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