Trench MOSFET device with integrated junction controlled diode and electronic device

Abstract

The present application provides a trench MOSFET device and electronic device with an integrated junction-controlled diode, and relates to the field of semiconductor device technology. The P-type epitaxial layer, the first P-type shielding layer, and the second P-type shielding layer are grounded, which can obtain a better electric field shielding effect during reverse withstand voltage, and can avoid the P-type epitaxial layer, the first P-type shielding layer, and the second P-type shielding layer from floating and causing voltage jumps during the switching process, thereby avoiding degradation of the switching characteristics of the device. In addition, a junction-controlled freewheeling diode region is introduced between the two trench MOSFET regions, and the conduction voltage drop of the integrated junction-controlled freewheeling diode will be lower than the body diode of the device, thereby shielding the conduction of the body diode; and the junction-controlled freewheeling diode is a unipolar device, does not have a minority carrier storage effect, and has a short reverse recovery time, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a trench MOSFET device with an integrated junction-controlled diode and an electronic device. Background Art

[0002] In recent years, wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have advantages over silicon (Si) in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. The power devices prepared from them, such as diodes, transistors, and power modules, have better electrical properties, which can overcome the defects of silicon-based materials that cannot meet the application requirements of high power, high voltage, high frequency, and high temperature. It is also one of the breakthrough paths to surpass Moore's Law. Therefore, they are widely used in new energy fields such as photovoltaics, energy storage, charging piles, electric vehicles, and other fields.

[0003] However, in the actual design, fabrication, and application of power devices, trench MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) made of wide-bandgap semiconductor materials still face several challenges. The high electric field in the material's drift region leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing rapid breakdown of the gate dielectric layer under high drain voltages. Furthermore, the device has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in circuits. Furthermore, the parasitic body diode exhibits minority carrier storage effects, resulting in a long reverse recovery time and increased switching losses. Therefore, how to reduce switching losses while simultaneously lowering the electric field at the gate trench corners of wide-bandgap semiconductor trench MOSFET devices has become a pressing issue. Summary of the Invention

[0004] In view of this, the present application provides a trench MOSFET device and electronic equipment with an integrated junction-controlled diode, which effectively solves the technical problems existing in the prior art and improves the performance of the trench MOSFET device.

[0005] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0006] A trench MOSFET device with an integrated junction-controlled diode, the trench MOSFET device comprising: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region between the two trench MOSFET regions;

[0007] The drain, N-type substrate, first N-type epitaxial layer, P-type epitaxial layer and second N-type epitaxial layer are stacked in sequence along the third direction:

[0008] Wherein, in the trench MOSFET region, the P-type epitaxial layer includes at least one N-type current channel arranged along a second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region including a source N+ region and a source P+ region; a trench gate electrode penetrating the source contact region and the P-type well region and extending deep into the second N-type epitaxial layer; a second P-type masking layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type masking layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane;

[0009] The junction-controlled freewheeling diode region includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, wherein the first P-type shielding layer is connected to the P-type well region;

[0010] and a source located on a side of the source contact region away from the N-type substrate.

[0011] Optionally, in the trench MOSFET region, the source N+ region and the source P+ region are arranged along the first direction, and the source P+ region is located on the side close to the first P-type masking layer, and the trench gate electrode penetrates the source N+ region and the P-type well region and penetrates into the second N-type epitaxial layer.

[0012] Optionally, at the junction-controlled freewheeling diode region, the first P-type shielding layer is extended along the second direction;

[0013] The first P-type masking layer and the P-type well region have a gap filled with the second N-type epitaxial layer in the first direction, and the trench MOSFET device also includes at least one second P-type grounding column located between the first P-type masking layer and the P-type well region, and the second P-type grounding column is in contact with and connected to the first P-type masking layer and the P-type well region.

[0014] Optionally, in the first direction, the second P-type grounding columns on both sides of the first P-type shielding layer are symmetrically or asymmetrically arranged with the first P-type shielding layer as an axis.

[0015] Optionally, the source P+ region also extends to the junction-controlled freewheeling diode region, and there is an overlapping area between the source P+ region and the first P-type shielding layer in the third direction, and there is a gap filled with the second N-type epitaxial layer between the source P+ region and the first P-type shielding layer in the third direction.

[0016] Optionally, in a direction from the source to the drain, the width of the first P-type shielding layer in the first direction tends to decrease.

[0017] Optionally, in the trench MOSFET region, the source N+ region includes a plurality of sub-source N+ regions extending along the first direction, and the source P+ region includes a plurality of sub-source P+ regions extending along the first direction, and the sub-source N+ regions and the sub-source P+ regions are alternately arranged in the second direction;

[0018] The sub-source N+ region and the sub-source P+ region of the two trench MOSFET regions extend to the junction-controlled freewheeling diode region and are correspondingly connected.

[0019] Optionally, at the junction-controlled freewheeling diode region, the first P-type shielding layer includes a plurality of sub-P-type shielding layers spaced apart along the second direction;

[0020] The sub-P-type shielding layer is in contact with and connected to the P-type well region.

[0021] Optionally, in the third direction, the sub-P-type shielding layer and the sub-source P+ region have an overlapping area.

[0022] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned trench MOSFET device with integrated junction-controlled diode.

[0023] Compared with the existing technology, the technical solution provided by this application has at least the following advantages:

[0024] The present application provides a trench MOSFET device and electronic device with an integrated junction-controlled diode, wherein the trench MOSFET device comprises: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region is included between the two trench MOSFET regions; a drain, an N-type substrate, a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer stacked in sequence along a third direction; wherein, at the trench MOSFET region, the P-type epitaxial layer includes at least one N-type current channel arranged along the second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region including a source N+ region and a source P+ region ; a trench gate electrode that penetrates the source contact region and the P-type well region and penetrates into the second N-type epitaxial layer; a second P-type shielding layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type shielding layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane; at the junction-controlled freewheeling diode region, includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, the first P-type shielding layer is connected to the P-type well region; and a source located on the side of the source contact region facing away from the N-type substrate.

[0025] As can be seen from the above content, the technical solution provided by this application shields the electric field at the trench gate electrode through the P-type epitaxial layer, the first P-type shielding layer, and the second P-type shielding layer, and the design of the first P-type grounding column and the first P-type shielding layer being connected to the P-type well region, so that the P-type epitaxial layer, the first P-type shielding layer, and the second P-type shielding layer are grounded, which can achieve a better electric field shielding effect during reverse withstand voltage, and can avoid the P-type epitaxial layer, the first P-type shielding layer, and the second P-type shielding layer from floating and generating voltage jumps during the switching process, thereby avoiding degradation of the device switching characteristics. In addition, a junction-controlled freewheeling diode region is introduced between the two trench MOSFET regions. The conduction voltage drop of the integrated junction-controlled freewheeling diode will be lower than that of the body diode of the device, thereby shielding the conduction of the body diode; and the junction-controlled freewheeling diode is a unipolar device, does not have a minority carrier storage effect, and has a short reverse recovery time, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0027] Figure 1 A schematic structural diagram of a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0028] Figure 2 A flow chart of a method for preparing a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0029] Figures 3a to 3f for Figure 2 Schematic diagram of the structure corresponding to each step;

[0030] Figure 4 A schematic structural diagram of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0031] Figure 5 A schematic structural diagram of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0032] Figure 6 for Figure 5 A sectional view at the mid-section A;

[0033] Figure 7 for Figure 5 Another cross-sectional view at mid-section A. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] As described in the background, several challenges remain in the design, fabrication, and application of power devices using wide-bandgap semiconductor trench MOSFETs. The high electric field in the material's drift region leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing rapid breakdown of the gate dielectric layer under high drain voltages. Furthermore, the device exhibits poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit. Furthermore, the parasitic body diode exhibits a minority carrier storage effect, resulting in a long reverse recovery time and increased switching losses. Therefore, the challenge of reducing switching losses while simultaneously lowering the electric field at the gate trench corners of wide-bandgap semiconductor trench MOSFETs remains.

[0036] Based on this, the embodiments of the present application provide a trench MOSFET device and electronic device with an integrated junction-controlled diode, which effectively solves the technical problems existing in the prior art and improves the performance of the trench MOSFET device.

[0037] To achieve the above purpose, the technical solutions provided in the embodiments of the present application are as follows, specifically combined with Figures 1 to 7 The technical solution provided by the embodiment of the present application is described in detail. It should be noted that the trench MOSFET device with integrated junction-controlled diode provided by the present application has many regions and structural layers, so the attached Figures 1 to 7 Each region and / or structural layer shown in the figure is indicated by a different color; Figures 1 to 7 The different colors shown are only used to distinguish the positional relationships of various regions and / or structural layers of the device.

[0038] refer to Figure 1The figure shows a schematic structural diagram of a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application, wherein the trench MOSFET device includes: two trench MOSFET regions S1 arranged along a first direction, and a junction-controlled freewheeling diode region S2 is included between the two trench MOSFET regions S1. The trench MOSFET device is in a stacked structure in a third direction, wherein the trench MOSFET device includes: a drain 10, an N-type substrate 21, a first N-type epitaxial layer 22, a P-type epitaxial layer 31, and a second N-type epitaxial layer 23 stacked in sequence along the third direction: wherein, at the trench MOSFET region S1, the P-type epitaxial layer 31 includes at least one N-type current channel 24 arranged along the second direction; a P-type well region 32 located on the second N-type epitaxial layer 23; a source contact region located on the P-type well region 32, the source contact region including a source An N+ region 25 and a source P+ region 33; a trench gate electrode that penetrates the source contact region and the P-type well region 32 and penetrates into the second N-type epitaxial layer 23, the trench gate electrode can extend along the second direction, and the trench gate electrode can include a gate dielectric layer 41 covering the inner wall of the gate trench and a gate 42 located in a groove formed in the gate dielectric layer 41; a second P-type masking layer 34 located at the bottom of the trench gate electrode; a first P-type grounding column 35 connecting the second P-type masking layer 34 and the P-type epitaxial layer 31; and an interlayer dielectric layer 43 covering the top of the trench gate electrode. The junction-controlled freewheeling diode region S2 includes a first P-type shielding layer 36 located within the second N-type epitaxial layer 23 and in communication with the P-type epitaxial layer 31. The first P-type shielding layer 36 is in communication with the P-type well region 32. Furthermore, a source electrode 50 is located on the side of the source contact region facing away from the N-type substrate 21. The source electrode 50 covers the source contact region, the interlayer dielectric layer 43, and the exposed surface of the second N-type epitaxial layer 23. The first direction and the second direction intersect at a reference plane, and the third direction intersects at the reference plane. Optionally, the first direction and the second direction are perpendicular to each other, and the third direction is perpendicular to the reference plane.

[0039] It can be understood that the first P-type grounding column 35 provided in the embodiment of the present application connects the P-type epitaxial layer 31 and the second P-type shielding layer 34, the first P-type shielding layer 36 is arranged in the second N-type epitaxial layer 23 and is connected to the P-type epitaxial layer 31, the first P-type shielding layer 36 is also connected to the P-type well region 32, the source P+ region 33 is arranged on the P-type well region 32 and is connected, and the source P+ region 33 is connected to the source 50, thereby forming a second P-type shielding layer. The connecting paths are from the shielding layer 34 to the first P-type grounding column 35, the first P-type grounding column 35 to the P-type epitaxial layer 31, the P-type epitaxial layer 31 to the first P-type shielding layer 36, the first P-type shielding layer 36 to the P-type well region 32, the P-type well region 32 to the source P+ region 33, and the source P+ region to the source 50. Since the source 50 is grounded by default when the trench MOSFET device is working, the grounding of all P-type regions in the trench MOSFET device is achieved.

[0040] From the above content, it can be seen that the technical solution provided in the embodiment of the present application jointly shields the electric field at the trench gate electrode through the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34, and through the design of the first P-type grounding column 35 and the first P-type shielding layer 36 connected to the P-type well region 32, the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34 are grounded, which can obtain a better electric field shielding effect during reverse withstand voltage, and can avoid the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34 from floating and causing voltage jumps during the switching process, thereby avoiding degradation of the device switching characteristics. In addition, a junction-controlled freewheeling diode region S2 is introduced between the two trench MOSFET regions S1. The conduction voltage drop of the integrated junction-controlled freewheeling diode will be lower than the body diode of the device, thereby shielding the conduction of the body diode; and the junction-controlled freewheeling diode is a unipolar device, there is no minority carrier storage effect, and the reverse recovery time is short, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0041] continue Figure 1As shown, in the trench MOSFET region S1, the source N+ region 25 and the source P+ region 33 are arranged along the first direction, and the source P+ region 33 is located on the side close to the first P-type masking layer 36 (i.e., the side of the source P+ region 33 close to the junction-controlled freewheeling diode region S2). The trench gate electrode penetrates the source N+ region 25 and the P-type well region 32 and extends deep into the second N-type epitaxial layer 23. The gate trench penetrates the source N+ region 25 and the P-type well region 32 and extends deep into the second N-type epitaxial layer 23. A gate dielectric layer 41 is formed on the inner wall of the gate trench, and a gate 42 is disposed in the groove formed by the gate dielectric layer 41. To prevent short circuit between the trench gate electrode and the source 50, an interlayer dielectric layer 43 is provided to cover the top surface of the gate 42. In which, the source P+ region 33 also extends to the junction-controlled freewheeling diode region S2, and there is an overlapping area between the source P+ region 33 and the first P-type masking layer 36 in the third direction, and there is a gap filled with the second N-type epitaxial layer 23 between the source P+ region 33 and the first P-type masking layer 36 in the third direction, and the second N-type epitaxial layer extends to fill the gap between the source P+ regions 33 of the two trench MOSFET regions S1, so that a PN junction-controlled freewheeling diode is formed between the two source P+ regions 33.

[0042] Still Figure 1 As shown, at the junction-controlled freewheeling diode region S2, the first P-type masking layer 36 is extended along the second direction; the first P-type masking layer 36 and the P-type well region 32 have a gap filled by the second N-type epitaxial layer 23 in the first direction, and the trench MOSFET device also includes at least one second P-type grounding column 37 located between the first P-type masking layer 36 and the P-type well region 32, and the second P-type grounding column 37 is in contact and connected with the first P-type masking layer 36 and the P-type well region 32, that is, the connection between the first P-type masking layer 36 and the P-type well region 32 is achieved through the second P-type grounding column 37. The trench MOSFET device provided in the embodiment of the present application introduces three JFET (Junction Field-Effect Transistor) regions between the two source P+ regions 33, between the first P-type masking layer 36 and the P-type well region 32, and between the first P-type masking layer 36 and the source P+ region 33. During reverse withstand voltage, the presence of multiple JFET regions can better suppress the leakage of the junction-controlled freewheeling diode, further improving the performance of the trench MOSFET device.

[0043] In one embodiment of the present application, the first P-type shielding layer 36, the second P-type shielding layer 34, the first P-type grounding column 35, the second P-type grounding column 37, the P-type well region 32, the source N+ region 25, the source P+ region 33, and the N-type current channel 24 provided in the embodiment of the present application can be formed by ion implantation. Figure 1 As shown in Figure 3, Figure 2 A flowchart of a method for preparing a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application is provided. Figures 3a to 3f for Figure 2 Schematic diagram of the structure corresponding to each step in the process. The method for preparing a trench MOSFET device includes:

[0044] S1, sequentially growing a first N-type epitaxial layer 22, a P-type epitaxial layer 31, and a second N-type epitaxial layer 23 on an N-type substrate 21, as shown in FIG. Figure 3a As shown in FIG. 1 , the N-type substrate 21 can be made of a wide bandgap semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), etc., so that the trench MOSFET device is formed into a wide bandgap trench MOSFET device.

[0045] S2, forming a first P-type shielding layer 36, a second P-type grounding column 37, a P-type well region 32, a source N+ region 25 and a source P+ region 33, as shown in FIG. Figure 3b shown. Figure 3b The left side is a cross-sectional view of the second P-type grounding column 37. Figure 3b The right side figure is a cross-sectional view without the second P-type grounding column 37. The second N-type epitaxial layer 23 is processed by ion implantation to form a first P-type shielding layer 36, a second P-type grounding column 37, a P-type well region 32, a source N+ region 25 and a source P+ region 33 in the second N-type epitaxial layer 23, wherein the first P-type shielding layer 36 is in contact with the P-type epitaxial layer 31, the second P-type grounding column 37 is in contact with the P-type well region 32, and the first P-type shielding layer 36 is in contact with the second P-type grounding column 37. Optionally, the first P-type shielding layer 36 and the first P-type grounding column 37 can be formed simultaneously by ion implantation; or, the first P-type shielding layer 36 and the first P-type grounding column 37 can be formed in two steps by ion implantation, and the ion input depths when the first P-type shielding layer 36 and the first P-type grounding column 37 are formed are the same or different, wherein the heights of the first P-type shielding layer 36 and the first P-type grounding column 37 in the third direction can be the same or different.

[0046] In the first direction, the second P-type grounding columns 37 on both sides of the first P-type shielding layer 36 provided in the embodiment of the present application are symmetrically or asymmetrically arranged with the first P-type shielding layer 36 as the axis.

[0047] S3, etching to form a gate trench 44, such as Figure 3c shown. Figure 3c The left side is a cross-sectional view of the second P-type grounding column 37. Figure 3c The right side figure is a cross-sectional view without the second P-type grounding column 37. The gate trench 44 passes through the source contact area, the P-type well area 32 and penetrates into the second N-type epitaxial layer 23. A dry etching process can be optionally used to form the gate trench 44. This application does not impose any specific restrictions on this.

[0048] S4, forming a first P-type masking layer 34, such as Figure 3d shown. Figure 3d The left side is a cross-sectional view of the second P-type grounding column 37. Figure 3d The right side figure is a cross-sectional view without the second P-type grounding column 37 , and the first P-type masking layer 34 is formed at the bottom of the gate trench 44 by ion implantation.

[0049] S5, forming an N-type current channel 24 and a first P-type grounding column 35, as shown in FIG. Figure 3e shown. Figure 3e The left side figure is a cross-sectional view of the second P-type grounding column 37, and Figure 3e The left figure shows the N-type current channel 24; Figure 3e The right side figure is a cross-sectional view without the second P-type grounding column 37, and Figure 3e The right side figure uses the first P-type grounding column 35 as an example, and uses ion implantation to form an N-type current channel 24 in the P-type epitaxial layer 31, and the N-type current channel 24 connects the first N-type epitaxial layer 22 and the second N-type epitaxial layer 23; and uses ion implantation to form the first P-type grounding column 35 to connect the second masking layer 34 and the P-type epitaxial layer 31.

[0050] S6, forming a gate dielectric layer 41, a gate 42, an interlayer dielectric layer 43, a source 50 and a drain 10, as shown in FIG. Figure 3f shown. Figure 3f The left side figure is a cross-sectional view of the second P-type grounding column 37, and Figure 3f The left figure shows the N-type current channel 24; Figure 3f The right side figure is a cross-sectional view without the second P-type grounding column 37, and Figure 3f The right-hand figure illustrates the process at the first P-type grounding pillar 35. A gate dielectric layer 41 is grown on the inner wall of the gate trench 44. The gate 32 is then filled into the trench formed by the gate dielectric layer 41 to form a trench gate electrode. Finally, an interlayer dielectric layer 43 is deposited and etched over the source contact region to cover the trench gate electrode. Furthermore, source metal is deposited to form a source electrode 50, covering the interlayer dielectric layer 43, the source contact region, and the exposed surface of the second N-type epitaxial layer 23. Drain metal is also deposited to form a drain electrode 10, located on the side of the N-type substrate 21 facing away from the source electrode 50.

[0051] exist Figure 1 Based on the trench MOSFET device shown, the first P-type shielding layer 36 provided in the embodiment of the present application can also be optimized to increase the current channel. Figure 4 FIG. 1 is a schematic diagram of the structure of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application, wherein Figure 1 Based on the trench MOSFET device shown, the width of the first P-type masking layer 36 in the first direction decreases in the direction from the source 50 to the drain 10. The first P-type masking layer 36 is formed into a shape that is wide at the top and narrow at the bottom, thereby widening the current channel below it and further improving the performance of the trench MOSFET device. Optionally, the sidewall of at least one side of the first P-type masking layer 36 in the first direction has multiple steps.

[0052] In some embodiments, the shapes of the trench MOSFET region S1 and the junction-controlled freewheeling diode region S2 provided in the embodiments of the present application can also be deformed to distinguish them from the Figure 1 The specific structure of the trench MOSFET device shown in FIG. Figure 5 and Figure 6 As shown, Figure 5 This is a schematic structural diagram of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application. Figure 6 for Figure 5Sectional view at the middle section A. Wherein, the trench MOSFET device includes: two trench MOSFET regions S1 arranged along the first direction, and a junction-controlled freewheeling diode region S2 is included between the two trench MOSFET regions S1. The trench MOSFET device is in a stacked structure in the third direction, wherein the trench MOSFET device includes: a drain 10, an N-type substrate 21, a first N-type epitaxial layer 22, a P-type epitaxial layer 31 and a second N-type epitaxial layer 23 stacked in sequence along the third direction: wherein, at the trench MOSFET region S1, the P-type epitaxial layer 31 includes at least one N-type current channel 24 arranged along the second direction; a P-type well region 32 located on the second N-type epitaxial layer 23; a source contact region located on the P-type well region 32, the source contact region including a source An N+ region 25 and a source P+ region 33; a trench gate electrode that penetrates the source contact region and the P-type well region 32 and penetrates into the second N-type epitaxial layer 23, the trench gate electrode can extend along the second direction, and the trench gate electrode can include a gate dielectric layer 41 covering the inner wall of the gate trench and a gate 42 located in a groove formed in the gate dielectric layer 41; a second P-type masking layer 34 located at the bottom of the trench gate electrode; a first P-type grounding column 35 connecting the second P-type masking layer 34 and the P-type epitaxial layer 31; and an interlayer dielectric layer 43 covering the top of the trench gate electrode. At the junction-controlled freewheeling diode region S2, it includes a first P-type masking layer 36 located in the second N-type epitaxial layer 23 and connected to the P-type epitaxial layer 31, the first P-type masking layer 36 is connected to the P-type well region 32; and a source 50 located on the side of the source contact region away from the N-type substrate 21, the source 50 covers the source contact region, the interlayer dielectric layer 43 and the exposed surface of the second N-type epitaxial layer 23.

[0053] Continue as Figure 5As shown, at the trench MOSFET area S1, the source N+ area 25 includes a plurality of sub-source N+ areas 251 extending along the first direction, and the source P+ area 33 includes a plurality of sub-source P+ areas 331 extending along the first direction, and the sub-source N+ areas 251 and the sub-source P+ areas 331 are alternately arranged in the second direction; the sub-source N+ areas 251 and the sub-source P+ areas 331 of the two trench MOSFET areas S1 extend to the junction-controlled freewheeling diode area S1 and are correspondingly connected. In addition, at the junction-controlled freewheeling diode region S1, the first P-type shielding layer 36 includes a plurality of sub-P-type shielding layers 361 spaced apart along the second direction; the sub-P-type shielding layers 361 are in contact with the P-type well region 32, wherein the gap between two adjacent sub-P-type shielding layers 361 is filled by the second N-type epitaxial layer 23, and the gap between the sub-P-type shielding layer 361 and the source contact region is also filled by the second N-type epitaxial layer 23, so that a PN junction-controlled freewheeling diode is formed between the two sub-source P+ regions 331, and the conduction voltage drop of the junction-controlled freewheeling diode will be lower than the body diode of the device, thereby shielding the conduction of the body diode; and the junction-controlled freewheeling diode is a unipolar device, there is no minority carrier storage effect, and the reverse recovery time is short, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0054] Furthermore, in the third direction, the sub-P-type shielding layer 361 and the sub-source P+ region 331 overlap, creating a double JFET region between two adjacent sub-P-type shielding layers 361 and between the sub-P-type shielding layer 361 and the sub-source P+ region 331. During reverse withstand voltage, the presence of multiple JFET regions can better suppress leakage of the junction-controlled freewheeling diode, further improving the performance of the trench MOSFET device.

[0055] It can be understood that the first P-type grounding column 35 provided in the embodiment of the present application connects the P-type epitaxial layer 31 and the second P-type shielding layer 34, the first P-type shielding layer 36 is arranged in the second N-type epitaxial layer 23 and is connected to the P-type epitaxial layer 31, the sub-P-type shielding layer 361 is also in contact with the P-type well region 32, the source P+ region 33 is arranged on the P-type well region 32 and is connected, and the source P+ region 33 is connected to the source 50, thereby forming a second P-type shielding layer The connection paths are from the first P-type grounding column 34 to the first P-type grounding column 35, from the first P-type grounding column 35 to the P-type epitaxial layer 31, from the P-type epitaxial layer 31 to the sub-P-type shielding layer 361, from the sub-P-type shielding layer 361 to the P-type well region 32, from the P-type well region 32 to the sub-source P+ region 331, and from the sub-source P+ region 331 to the source 50. Since the source 50 is grounded by default during operation of the trench MOSFET device, this achieves grounding of all P-type regions in the trench MOSFET device. Furthermore, a better electric field shielding effect can be achieved during reverse withstand voltage, and during the switching process, voltage jumps caused by floating of the P-type epitaxial layer 31, the first P-type shielding layer 36, and the second P-type shielding layer 34 can be avoided, thereby preventing degradation of the device switching characteristics.

[0056] like Figure 6 As shown, the sub-P-type shielding layer 361 and the sub-source P+ region 331 provided in the embodiment of the present application can be relatively overlapped in the third direction, that is, the sub-P-type shielding layer 361 and the sub-source P+ region 331 can have the same width in the second direction, and the sub-P-type shielding layer 361 and the sub-source P+ region 331 overlap in the third direction. Or, as Figure 7 As shown, the sub-P-type shielding layer 361 and the sub-source P+ region 331 provided in the embodiment of the present application can be staggered and overlapped in the third direction, that is, the sub-P-type shielding layer 361 and the sub-source P+ region 331 can have the same width in the second direction, and the sub-P-type shielding layer 361 and the sub-source P+ region 331 partially overlap in the third direction. In some embodiments, the sub-P-type shielding layer 361 and the sub-source P+ region 331 can also have different widths in the second direction, as long as the sub-P-type shielding layer 361 and the sub-source P+ region 331 at least partially overlap in the third direction. This application does not impose any specific restrictions on this.

[0057] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes a trench MOSFET device with an integrated junction-controlled diode provided by any of the above embodiments.

[0058] The embodiment of the present application provides a trench MOSFET device and an electronic device with an integrated junction-controlled diode, wherein the trench MOSFET device includes: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region is included between the two trench MOSFET regions; a drain, an N-type substrate, a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer stacked in sequence along a third direction: wherein, at the trench MOSFET region, the P-type epitaxial layer includes at least one N-type current channel arranged along the second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region including a source N+ region and a source P+ region; a trench gate electrode that penetrates the source contact region and the P-type well region and penetrates into the second N-type epitaxial layer; a second P-type shielding layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type shielding layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane; at the junction-controlled freewheeling diode region, it includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, the first P-type shielding layer is connected to the P-type well region; and a source located on the side of the source contact region facing away from the N-type substrate.

[0059] As can be seen from the above content, the technical solution provided by the embodiment of the present application shields the electric field at the trench gate electrode through the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer, and the design of the first P-type grounding column and the first P-type shielding layer being connected to the P-type well region makes the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer grounded, which can obtain a better electric field shielding effect during reverse withstand voltage, and can avoid the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer from floating and causing voltage jumps during the switching process, thereby avoiding degradation of the switching characteristics of the device. In addition, a junction-controlled freewheeling diode region is introduced between the two trench MOSFET regions. The junction-controlled freewheeling diode is a unipolar device, does not have a minority carrier storage effect, and has a short reverse recovery time, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0060] In the description of the embodiments of the present application, it should be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise clearly specified.

[0062] In the embodiments of this application, unless otherwise specified or limited, terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication between them; direct connections, indirect connections through an intermediate medium, and internal connections between two components or interactions between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0063] In the embodiments of the present application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, a first feature being "above," "above," and "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0064] In the embodiments of the present application, the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0065] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A trench MOSFET device with an integrated junction-controlled diode, characterized in that: The trench MOSFET device comprises: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region is included between the two trench MOSFET regions; The drain, N-type substrate, first N-type epitaxial layer, P-type epitaxial layer and second N-type epitaxial layer are stacked in sequence along the third direction: Wherein, in the trench MOSFET region, the P-type epitaxial layer includes at least one N-type current channel arranged along a second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region including a source N+ region and a source P+ region; a trench gate electrode penetrating the source contact region and the P-type well region and extending deep into the second N-type epitaxial layer; a second P-type masking layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type masking layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane; The junction-controlled freewheeling diode region includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, wherein the first P-type shielding layer is connected to the P-type well region; and a source located on a side of the source contact region away from the N-type substrate.

2. The trench MOSFET device with integrated junction-controlled diode according to claim 1, characterized in that: In the trench MOSFET region, the source N+ region and the source P+ region are arranged along the first direction, and the source P+ region is located on a side close to the first P-type masking layer. The trench gate electrode penetrates the source N+ region and the P-type well region and penetrates into the second N-type epitaxial layer.

3. The trench MOSFET device with integrated junction controlled diode according to claim 2, characterized in that: At the junction-controlled freewheeling diode region, the first P-type shielding layer is extended along the second direction; The first P-type masking layer and the P-type well region have a gap filled with the second N-type epitaxial layer in the first direction, and the trench MOSFET device also includes at least one second P-type grounding column located between the first P-type masking layer and the P-type well region, and the second P-type grounding column is in contact with and connected to the first P-type masking layer and the P-type well region.

4. The trench MOSFET device with integrated junction controlled diode according to claim 3, characterized in that: In the first direction, the second P-type grounding columns on both sides of the first P-type shielding layer are symmetrically or asymmetrically arranged with the first P-type shielding layer as an axis.

5. The trench MOSFET device with integrated junction controlled diode according to claim 3, characterized in that: The source P+ region also extends to the junction-controlled freewheeling diode region, and there is an overlapping area between the source P+ region and the first P-type shielding layer in the third direction, and there is a gap filled with the second N-type epitaxial layer between the source P+ region and the first P-type shielding layer in the third direction.

6. The trench MOSFET device with integrated junction controlled diode according to claim 3, characterized in that: In a direction from the source to the drain, the width of the first P-type shielding layer in the first direction tends to decrease.

7. The trench MOSFET device with integrated junction controlled diode according to claim 1, characterized in that: In the trench MOSFET region, the source N+ region includes a plurality of sub-source N+ regions extending along the first direction, and the source P+ region includes a plurality of sub-source P+ regions extending along the first direction, and the sub-source N+ regions and the sub-source P+ regions are alternately arranged in the second direction; The sub-source N+ region and the sub-source P+ region of the two trench MOSFET regions extend to the junction-controlled freewheeling diode region and are correspondingly connected.

8. The trench MOSFET device with integrated junction controlled diode according to claim 7, characterized in that: At the junction-controlled freewheeling diode region, the first P-type shielding layer includes a plurality of sub-P-type shielding layers spaced apart along the second direction; The sub-P-type shielding layer is in contact with and connected to the P-type well region.

9. The trench MOSFET device with integrated junction controlled diode according to claim 8, characterized in that: In the third direction, the sub-P-type shielding layer and the sub-source P+ region have an overlapping area.

10. An electronic device, characterized in that: The electronic device comprises a trench MOSFET device with an integrated junction-controlled diode according to any one of claims 1 to 9.

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