Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a metal gate structure, at least one dummy body, two source / drain regions and a dielectric layer. The metal gate structure is disposed on the substrate. The at least one dummy body is disposed in the metal gate structure. The two source / drain regions are disposed in the substrate on both sides of the metal gate structure. The dielectric layer is disposed on the substrate and surrounds the metal gate structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device with a metal gate structure and a manufacturing method thereof. Background Art

[0002] In the existing semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as a standard gate filling material. However, as the size of MOS transistors continues to shrink, the traditional polysilicon gate has problems such as the boron penetration effect, which leads to reduced device performance, and the unavoidable depletion effect, which increases the equivalent gate dielectric thickness and reduces the gate capacitance, leading to the decline of device driving ability. Therefore, the semiconductor industry has tried to use new gate filling materials, such as using work function metals to replace traditional polysilicon gates as control electrodes that match high-k gate dielectric layers.

[0003] In addition, as the size of semiconductor components is getting smaller and smaller, the manufacturing process of transistors has also been improved in many ways to produce small and high-quality transistors. However, as the size of equipment continues to decrease, it becomes more difficult to simultaneously form high-voltage components with relatively large line widths and low-voltage components with miniaturized line widths in the same semiconductor device, which makes the related manufacturing processes also face many limitations and challenges. Therefore, how to effectively improve the manufacturing process defects of high-voltage components has become an important issue in today's semiconductor industry. Summary of the invention

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, wherein at least one dummy is disposed within a metal gate structure to improve the structural reliability and device performance of the metal gate structure, thereby avoiding problems or structural defects caused by insufficient or excessive polishing during a planarization process when the metal gate structure is subjected to a replacement metal gate (RMG) process.

[0005] To achieve the above-mentioned object, the present invention provides a semiconductor device, comprising a substrate, a metal gate structure, at least one dummy body, two source / drain regions and a dielectric layer. The metal gate structure is disposed on the substrate. The at least one dummy body is disposed in the metal gate structure. The source / drain regions are disposed in the substrate on both sides of the metal gate structure. The dielectric layer is disposed on the substrate and surrounds the metal gate structure.

[0006] To achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate, forming a metal gate structure on the substrate; forming at least one dummy body in the metal gate structure; forming two source / drain regions in the substrate, respectively located on both sides of the metal gate structure; forming a dielectric layer on the substrate, surrounding the metal gate structure.

[0007] In general, the semiconductor device and its manufacturing method of the present invention are to pre-set at least one dummy body in the polysilicon gate structure when forming the polysilicon gate structure, and perform the metal gate replacement manufacturing process under the premise of the existence of at least one dummy body, so as to avoid the short circuit problem or structural defect of the metal gate structure caused by insufficient or excessive grinding during the planarization manufacturing process. In this way, the structural reliability and device performance of the semiconductor device of the present invention can be effectively improved to achieve better operating performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 3 Schematic diagram of a semiconductor device in a first embodiment of the present invention, wherein:

[0009] Figure 1 is a schematic cross-sectional view of a semiconductor device;

[0010] Figure 2 is a schematic top view of a semiconductor device; and

[0011] Figure 3 is another schematic top view of a semiconductor device;

[0012] Figures 4 to 8 Schematic diagram of a method for manufacturing a semiconductor device in a first embodiment of the present invention, wherein:

[0013] Figure 4 is a schematic cross-sectional view of a semiconductor device after a polysilicon gate layer is formed;

[0014] Figure 5 is a schematic cross-sectional view of a semiconductor device after a polysilicon gate structure is formed;

[0015] Figure 6 is a schematic cross-sectional view of a semiconductor device after a dielectric layer is formed;

[0016] Figure 7 is a schematic cross-sectional view of a semiconductor device after the polysilicon gate layer is removed; and

[0017] Figure 8 is a schematic cross-sectional view of a semiconductor device after a work function metal material layer and a conductive material layer are formed;

[0018] Figures 9 and 10 Schematic diagram of a semiconductor device in a second embodiment of the present invention, wherein:

[0019] Fig. 9 is a schematic cross-sectional view of a semiconductor device; and

[0020] Fig.10 A schematic top view of a semiconductor device.

[0021] Main component symbols

[0022] 10, 30 Semiconductor devices

[0023] 100 Base

[0024] 102 Source / drain region

[0025] 110 Dielectric layer

[0026] 120 Metal Gate Structure

[0027] 120a Gate unit

[0028] 122 Dielectric layer

[0029] 124 High dielectric constant dielectric layer

[0030] 126 Work function metal layer

[0031] 128 Barrier Layer

[0032] 130 Conductive layer

[0033] 132 Covering layer

[0034] 134 gap wall

[0035] 140 Virtual Body

[0036] 140a Square pattern

[0037] 140b, 140c Rectangular pattern

[0038] 220 Polysilicon Gate Structure

[0039] 224 Polysilicon layer

[0040] 226 Groove

[0041] 228 Gate trench

[0042] 232 High dielectric constant material layer

[0043] 234 Work function metal material layer

[0044] 236 Barrier Material Layer

[0045] 238 conductive material layer

[0046] 320 Metal Gate Structure

[0047] 320a, 320b Gate unit

[0048] 320c, 320d gate unit

[0049] 340 Virtual Body

[0050] 340a Square pattern

[0051] 340b, 340c Rectangular pattern

[0052] 342, 344 insulation layer

[0053] D1 First direction

[0054] D2 vertical direction

[0055] L1 Length

[0056] L31, L32, L33, L34 Length

[0057] P1, P2 spacing

[0058] S1 Line Width

[0059] W1, W2 Width DETAILED DESCRIPTION

[0060] In order to enable a person skilled in the art who is familiar with the technical field to which the present invention belongs to further understand the present invention, several preferred embodiments of the present invention are listed below, and the components and effects to be achieved of the present invention are described in detail with reference to the accompanying drawings. Moreover, without departing from the spirit of the present invention, the technical features of the different embodiments described below can be replaced, reorganized, or mixed with each other to form other embodiments.

[0061] Please refer to Figures 1 to 3 As shown, it is a schematic diagram of a semiconductor device 10 according to a first embodiment of the present invention. Figure 1As shown, the semiconductor device 10 includes a substrate 100, a metal gate structure 120, at least one dummy body 140, two source / drain regions 102 and a dielectric layer 110. The substrate 100 includes, for example, a silicon substrate, an epitaxial silicon substrate, a silicon containing substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The metal gate structure 120 is disposed on the substrate 100, and the two source / drain regions 102 are disposed in the substrate 100 on two opposite sides of the metal gate structure 120. The dielectric layer 110 is disposed on the substrate 100, surrounds the metal gate structure 120, and integrally covers the substrate 100 and the source / drain regions 102. In one embodiment, each source / drain region 102, for example, includes a doped region having a suitable conductivity type and dopant. For example, if the metal gate structure 120 is expected to form a P-type transistor (PMOS) in a subsequent manufacturing process, the doped region includes a P-type dopant such as boron. If the metal gate structure 120 is expected to form an N-type transistor (NMOS) in a subsequent manufacturing process, the doped region may include an N-type dopant such as phosphorus, but the present invention is not limited thereto.

[0062] It should be particularly noted that the dummy body 140 is disposed within the metal gate structure 120. Thus, when the metal gate structure 120 having a relatively large line width S1 (e.g., approximately 2 microns to 10 microns) is subjected to a planarization process such as chemical mechanical polishing, problems such as metal residue will not be generated due to insufficient polishing, nor will defects such as metal gate depressions be generated due to excessive polishing. This allows the metal gate structure 120 of the semiconductor device 10 to have a more reliable structure and effectively improve its component performance.

[0063] In one embodiment, the dummy body 140 includes, for example, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, but is not limited thereto. In addition, a plurality of dummy bodies 140 may be disposed in the metal gate structure 120 of the semiconductor device 10, and are disposed in the metal gate structure 120 in a spaced manner to further separate the metal gate structure 120 into a plurality of gate units 120a, such as Figure 1As shown. Under this configuration, a plurality of dummy bodies 140 and a plurality of gate units 120a are periodically arranged alternately in a specific direction within the metal gate structure 120, wherein each gate unit 120a has, for example, the same length L1 in the specific direction, and each dummy body 140 has, for example, the same width W1 in the specific direction, but is not limited thereto. It should be noted that the dummy body 140 is configured to cut off the extension length of the metal gate structure 120 in the specific direction (e.g., Figure 1 Therefore, the plurality of gate units 120a of the metal gate structure 120 are not separated from each other, but are connected and electrically connected to each other.

[0064] For example, in Figure 2 In the top view shown, the dummy body 140 has, for example, a plurality of square patterns 140a having the same shape and size (such as width W1) or a plurality of rectangular patterns 140b extending in the first direction D1. The dummy bodies 140a and 140b are arranged in the first direction D1 and / or the perpendicular direction D2 according to the same pitch P1 or pitch P2, and are arranged as a whole in a symmetric pattern, for example. Figure 2 The matrix pattern shown on the left is not limited to this. Those skilled in the art should be able to easily understand Figure 1 For example Figure 2 A schematic cross-sectional view along the tangent line A-A' in FIG. 1 , wherein the aforementioned specific direction is, for example, Figure 2 The vertical direction D2 is shown, but not limited to this.

[0065] In addition, those skilled in the art should also be able to easily understand that the specific number, shape, and arrangement pattern of the dummy body 140 can be adjusted according to actual device requirements. Figure 1 or Figure 2 In another embodiment, the dummy body 140 may also be selected to have a plurality of rectangular patterns 140c extending in the vertical direction D2, such as Figure 3 As shown on the left side, there are a plurality of rectangular patterns 140b extending in the first direction D1 and a plurality of rectangular patterns 140c extending in the vertical direction D2, which overlap each other and are arranged into a plurality of cross patterns, such as Figure 3 The dummy bodies 140b and 140c also have the same size (eg, width W1) and are arranged in the first direction D1 and / or the vertical direction D2 at the same spacing (not shown) to form a symmetrical pattern as a whole, but the present invention is not limited thereto.

[0066] Specifically, the metal gate structure 120 further includes a dielectric layer 122, a U-shaped high-k dielectric layer 124, a U-shaped work function metal layer 126, a U-shaped barrier layer 128, a conductive layer 130, and a cap layer 132, which are stacked in sequence from bottom to top, and a spacer 134 disposed on the sidewalls of the aforementioned stacked layers. Figure 1 As shown. Wherein, the spacer 134, for example, includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, and preferably has the same insulating material as the dummy body 140, but is not limited thereto. In one embodiment, the high dielectric constant dielectric layer 124, for example, includes a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), and the work function metal layer 126, for example, is a P-type work function metal layer, including materials such as nickel (Ni), tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti) nitride, or an N-type work function metal layer, including titanium aluminides (TiAl), aluminum zirconium (ZrAl), aluminum tungsten (WAl), aluminum tantalum (TaAl) or hafnium aluminide (Aluminum The barrier layer 128, for example, includes metal barrier materials such as titanium / titanium nitride (Ti / TiN) or tantalum / tantalum nitride (Ta / TaN), and the conductive layer 130, for example, includes low-resistance metal materials such as titanium, tantalum (Ta), aluminum (Al), copper (Cu) or tungsten, but is not limited to the foregoing.

[0067] Therefore, according to the semiconductor device 10 of the present embodiment, the dummy body 140 is disposed in the metal gate structure 120, so as to improve the structural reliability and device performance of the metal gate structure 120, and effectively avoid the metal gate structure 120 from causing short circuit problems due to insufficient polishing in the planarization process, or structural defects such as depression of the top surface of the metal gate caused by excessive polishing in the planarization process, during the metal gate replacement process. Accordingly, the semiconductor device 10 of the present embodiment has a more reliable structure and can achieve better operating performance, and can be applied to high-voltage devices operating at high voltage, medium-voltage devices operating at medium voltage, or low-voltage devices integrating the high-voltage device, the medium-voltage device, and low-voltage devices operating at low voltage, so as to avoid the metal gate structure 120 having a larger line width S1 and other low-voltage devices with smaller line widths (e.g., less than about 2 microns) from causing the aforementioned structural defects or short circuit problems during the planarization process such as chemical mechanical polishing. The aforementioned high-voltage component, for example, refers to a semiconductor component with a starting voltage between 10 volts (V) and 20 volts, the medium-voltage component, for example, refers to a semiconductor component with a starting voltage between 5 volts and 10 volts, and the low-voltage component, for example, refers to a semiconductor component with a starting voltage between 0.5 volts and 1 volt, but is not limited to this.

[0068] In order to enable a person skilled in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, a method for manufacturing the semiconductor device 10 of the present invention will be further described below.

[0069] Please refer to Figures 4 to 8 FIG. 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor device 10 in a first embodiment of the present invention. First, Figure 4As shown, a substrate 100 is provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon-containing substrate or a silicon-covered insulating substrate, and then a polysilicon gate structure 220 is formed on the substrate 100. The polysilicon gate structure 220 includes a dielectric layer 122 and a polysilicon layer 224 stacked in sequence, and has a relatively large line width S1, such as about 2 microns to 10 microns, but not limited to this. Among them, at least one groove (poly slot) 226 is further formed in the polysilicon layer 224. In one embodiment, the production of the polysilicon gate structure 220 and the groove 226 includes but is not limited to the following steps. First, a dielectric material layer (not shown) and a polysilicon material layer (not shown) stacked in sequence are formed on the substrate 100. Next, the dielectric material layer and the polysilicon material layer are patterned through a mask layer (not shown) to form a dielectric layer 122 and a polysilicon layer 224. When the polysilicon material layer is patterned, a trench 226 is formed in the polysilicon layer 224 through the mask layer. Then, after removing the mask layer, an ion implantation mask (not shown) is formed on the substrate 100 to define the NMOS region or PMOS region to be implanted. For example, a first ion implantation mask (not shown) is formed to cover the NMOS region and expose the PMOS region, or to cover the PMOS region and expose the NMOS region, or to cover a low voltage component region and expose a high voltage component region, etc. Thus, the ion implantation mask will cover each trench 226 simultaneously. An ion implantation process is performed through the ion implantation mask to form two doped regions in the substrate 100 at two opposite sides of the polysilicon layer 224 as the source / drain regions 102 of the semiconductor device 10 .

[0070] like Figure 5 As shown, a spacer 134 is formed on the sidewall of the polysilicon gate structure 220. In one embodiment, the production of the spacer 134 includes but is not limited to sequentially performing a deposition process and a back-etching process. First, through the deposition process, an insulating material layer (not shown) is formed on the substrate 100, conformally covering the polysilicon gate structure 220 and the substrate 100, wherein the insulating material layer, for example, includes insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, but is not limited thereto. Then, through the back-etching process, the insulating material is partially removed, and the spacer 134 is formed on the sidewall of the polysilicon gate structure 220. It should be particularly noted that during the deposition process, the insulating material layer is simultaneously filled into the groove 226 in the polysilicon layer 224, and the insulating material layer filled into the groove 226 will not be removed during the back-etching process. Thus, the insulating material layer filled in the trench 226 forms at least one dummy body 140 after the etch-back process. In other words, the dummy body 140 and the spacer 134 are formed by the same deposition and etch-back process and thus have the same insulating material.

[0071] like Figure 6 As shown, a dielectric layer 110 is formed on the substrate 100, covering the substrate 100 and surrounding the polysilicon gate structure 220 and the spacer 134. In one embodiment, the production of the dielectric layer 110 includes but is not limited to sequentially performing a deposition process and a planarization process. First, through the deposition process, a dielectric material layer (not shown) is integrally formed on the substrate 100, covering the substrate 100 and the polysilicon gate structure 220. Then, through the planarization process, such as a chemical mechanical polishing process, the dielectric material layer is partially removed to expose the top surface of the polysilicon gate structure 220 to form the dielectric layer 110 as an interlayer dielectric layer (ILD) of the semiconductor device 10. In one embodiment, the dielectric material layer includes dielectric materials such as silicon oxide and silicon oxynitride, and preferably includes a material having an etching selectivity with the spacer 134 and the dummy body 140, but is not limited thereto.

[0072] like Figure 7 As shown, a metal gate replacement process is performed to completely remove the polysilicon layer 224 of the polysilicon gate structure 220 to form a plurality of gate trenches 228 and expose the underlying dielectric layer 122 .

[0073] like Figure 8 As shown, multiple deposition processes are performed to sequentially form a high dielectric constant material layer 232, a work function metal material layer 234, a barrier material layer 236, and a conductive material layer 238 on the substrate 100. The high dielectric constant material layer 232, the work function metal material layer 234, and the barrier material layer 236 conformally cover the surface of the gate trench 228 and further cover the top surface of the dummy body 140 and the dielectric layer 110, while the conductive material layer 238 fills the gate trench 228 and covers the top surface of the dummy body 140 and the dielectric layer 110. Subsequently, a planarization process such as a chemical mechanical polishing process is performed on the dummy body 140 disposed in the gate trench 228 to remove the conductive material layer 238, the barrier material layer 236, the work function metal material layer 234, and the high dielectric constant material layer 232 covering the top surface of the dummy body 140 and the dielectric layer 110, and then a back etching process is performed to partially remove the conductive material layer 238, the barrier material layer 236, the work function metal material layer 234, and the high dielectric constant material layer 232 to below the top surface of the dielectric layer 110, so as to form a Figure 1 The conductive layer 130, barrier layer 128, work function metal layer 126 and high dielectric constant dielectric layer 124 are shown. Finally, a cap layer 132 is formed. Thus, the cap layer 132, the conductive layer 130, the barrier layer 128, the work function metal layer 126, the high dielectric constant dielectric layer 124 and the dielectric layer 122 together form the following structure: Figure 1The metal gate structure 120 shown also has a relatively large line width S1.

[0074] It should be particularly noted that, since the metal gate replacement process of the present embodiment performs the planarization process and the back etching process after the dummy body 140 has been pre-formed, it can effectively improve the loading effect that is easily derived from the pattern density difference, avoid defects such as dishing derived from over-grinding in components with relatively low pattern density (i.e., the metal gate structure 120 with a larger line width S1), or improve problems such as short circuits caused by residual conductive material layer 228 due to insufficient grinding.

[0075] According to the manufacturing method of the semiconductor device 10 of the present embodiment, when forming the polysilicon gate structure 220, a trench 226 is additionally formed in the polysilicon material layer 224 with a larger line width S1, so that when the spacer 134 is subsequently formed, the dummy body 140 is also formed in the trench 226. In this way, when the subsequent metal gate replacement manufacturing process is performed, the planarization manufacturing process and the back etching manufacturing process can be performed in the presence of the dummy body 140, effectively avoiding the short circuit problem or structural defect that may be derived from the metal gate structure 120 during the metal gate replacement manufacturing process, thereby improving the structural reliability and device performance of the metal gate structure 120. Therefore, the manufacturing method of the present embodiment can be applied to the manufacturing process of high-voltage devices, the manufacturing process of medium-voltage devices, or the manufacturing process integrating the high-voltage devices, the medium-voltage devices, and the low-voltage devices, so as to avoid the metal gate structure 120 with a larger line width S1 and other low-voltage devices with a smaller line width (for example, less than about 2 microns) from deriving the aforementioned short circuit problem or structural defect when performing a planarization manufacturing process such as chemical mechanical polishing.

[0076] Those skilled in the art should be able to easily understand that in order to meet actual needs, the semiconductor device and the manufacturing method of the present invention may have other aspects, not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and the manufacturing method of the present invention. And to simplify the description, the following description mainly describes the differences between the embodiments, and will not repeat the same parts. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0077] Please refer to Figures 9 and 10, which is a schematic diagram of a semiconductor device 30 in a second embodiment of the present invention. The structure of the semiconductor device 30 is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities are not repeated. The main difference between this embodiment and the previous embodiment is that the dummy body 340 includes a composite layer structure and / or the metal gate structure 320 includes gate units 320a, 320b of different lengths.

[0078] In detail, Fig. 9 As shown, a plurality of dummy bodies 340 are also provided in the metal gate structure 320 to further divide the metal gate structure 320 into a plurality of gate units 320a and 320b with different lengths L31 and L32, or into a plurality of gate units 320c and 320d with different lengths L33 and L34, but the present invention is not limited thereto. The gate units 320a and 320b or the gate units 320c and 320d are not separated, but are connected and electrically connected to each other. For example, in Fig.10 In the top view shown, the dummy body 340 includes, for example, a plurality of square patterns 340a, a plurality of rectangular patterns 340b extending in the first direction D1, and / or a plurality of rectangular patterns 340c extending in the vertical direction D2, but the present invention is not limited thereto. The square patterns 340a, the rectangular patterns 340b, and / or the rectangular patterns 340c are, for example, arranged separately from each other, or overlapped with each other and arranged in a cross pattern, etc., and the whole is arranged in an asymmetric pattern in the metal gate structure 320, for example, Fig.10 As shown, but not limited to this. Those skilled in the art should easily understand Fig. 9 For example Fig.10 The cross-sectional schematic diagram along the tangent line BB' is shown in FIG.

[0079] That is, in the present embodiment, each dummy body 340 disposed in the metal gate structure 320 includes, for example, a plurality of patterns 340a, 340b, 340c extending in different directions, having different shapes, or arranged at different intervals, thereby presenting the asymmetric pattern. In this way, each dummy body 340 can also cut off the metal gate structure 320 in a specific direction (for example, Fig.10 The extended length in the vertical direction D2) as shown ensures that the metal gate structure 320 will not have problems such as metal residue due to insufficient grinding during the subsequent planarization process, nor will it produce defects such as structural depressions due to excessive grinding, so that the metal gate structure 320 of the semiconductor device 30 can have a more reliable structure and effectively improve its performance.

[0080] On the other hand, in one embodiment, a dummy body 340 with different sizes (such as width W1 and W2) can be optionally provided in the metal gate structure 320, wherein the dummy body 340 with a smaller size W1 includes a single-layer structure (made of the same material as the spacer 134), and the dummy body 340 with a larger size W2 includes a composite layer structure composed of an insulating layer 342 and an insulating layer 344, but is not limited thereto. The manufacturing of the dummy body 340 includes but is not limited to the following steps: first, after forming a dummy body 340 as shown in FIG. Figure 4 When the polysilicon gate structure 220 is formed, a plurality of trenches (not shown) with different sizes (ie, widths W1 or W2) are formed in the polysilicon layer 224. Figure 5 When the spacers 134 are formed, the insulating material layer fills the grooves with a width of W1 to form a dummy body 340 with a width of W1, and partially fills the grooves with a width of W2 to form a first portion of the dummy body 340 with a width of W2, which is an insulating layer 342. Figure 6 When the dielectric layer 110 is formed as shown, the dielectric material layer fills the trench with a width of W2 to form a second portion of the dummy body 340 with a width of W2, which is the insulating layer 344.

[0081] Under this setting, the virtual body 340 with different sizes (such as width W1, W2) can also cut off the extension length of the metal gate structure 320 in the specific direction, so that when the metal gate structure 320 undergoes the subsequent planarization manufacturing process, it will not have problems such as metal residue due to insufficient grinding, nor will it produce defects such as structural depressions due to excessive grinding, so as to effectively improve the structural reliability and component performance of the semiconductor device 30, thereby achieving better operating performance.

[0082] It should be easily understood by those skilled in the art that although the aforementioned implementation is to set dummy bodies 340 of different sizes, shapes, or spacings in the metal gate structure 320 as an implementation mode for explanation, the setting changes of the dummy bodies 340 are not limited to this. In another embodiment, the setting density of the dummy bodies 340, the spacing between them, etc. can be further adjusted according to actual needs. For example, when the line width of a metal gate structure is larger (greater than 10 microns) or the area is wider, the setting density of the multiple dummy bodies set in the center of the metal gate structure is preferably greater than the multiple dummy bodies set in the peripheral part of the metal gate structure, but it is not limited to this. In addition, the width of each dummy body 340 on the channel length of the metal gate structure 320 (for example, the length of the metal gate structure 320 between the two source / drain regions 102) is preferably greater than the channel width of the dummy body 340 on the metal gate structure 320 (for example, the width of the metal gate structure 320 in the direction of the vertical source / drain region 102 connection) to obtain a better channel width.

[0083] In general, the semiconductor device and its manufacturing method of the present invention are to pre-set at least one dummy body in the polysilicon gate structure when forming the polysilicon gate structure, and perform the metal gate replacement manufacturing process under the premise of the existence of at least one dummy body, so as to avoid the short circuit problem or structural defect of the metal gate structure caused by insufficient or excessive grinding during the planarization manufacturing process. In this way, the structural reliability and device performance of the semiconductor device of the present invention can be effectively improved to achieve better operating performance.

[0084] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that include: substrate; A metal gate structure is disposed on the substrate; At least one dummy body is disposed in the metal gate structure; Two source / drain regions are respectively disposed in the substrate on both sides of the metal gate structure; as well as The dielectric layer is disposed on the substrate and surrounds the metal gate structure.

2. The semiconductor device according to claim 1, wherein: The at least one dummy body comprises a composite layer structure.

3. The semiconductor device according to claim 1, wherein: Also includes: A plurality of dummy bodies are disposed in the metal gate structure in a mutually separated manner.

4. The semiconductor device according to claim 3, wherein: The dummy bodies are arranged in an asymmetric pattern.

5. The semiconductor device according to claim 4, wherein: The dummy bodies include a plurality of first patterns and a plurality of second patterns, and the first patterns and the second patterns extend in different directions respectively.

6. The semiconductor device according to claim 4, wherein: The dummy bodies include a plurality of first patterns and a plurality of second patterns, and the first patterns and the second patterns include different shapes respectively.

7. The semiconductor device according to claim 4, wherein: The dummy bodies are arranged at different intervals.

8. The semiconductor device according to claim 3, wherein: The dummy bodies are arranged in a symmetrical pattern.

9. The semiconductor device according to claim 8, wherein: The dummy bodies are arranged in a matrix pattern.

10. The semiconductor device according to claim 8, wherein: The dummy bodies extend in the same direction.

11. The semiconductor device according to claim 8, wherein: The dummy bodies are arranged at the same intervals.

12. The semiconductor device according to claim 3, wherein: The metal gate structure also includes a plurality of gate units, and each of the gate units and each of the dummy bodies are alternately arranged in the metal gate structure.

13. The semiconductor device according to claim 12, wherein: At least two of the gate units have the same length.

14. The semiconductor device according to claim 12, wherein: At least two of the gate units have different lengths.

15. The semiconductor device according to claim 12, wherein: Each of the gate units includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, a U-shaped barrier layer, and a conductive layer, and the high-k dielectric layer, the work function metal layer, the barrier layer, and the conductive layer are stacked in sequence from bottom to top.

16. A method for manufacturing a semiconductor device, characterized in that include: providing a substrate; forming a metal gate structure on the substrate; forming at least one dummy body in the metal gate structure; forming two source / drain regions in the substrate, respectively located on two sides of the metal gate structure; and A dielectric layer is formed on the substrate to surround the metal gate structure.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: Forming the metal gate structure also includes: forming a polysilicon gate structure on the substrate; forming at least one trench in the polysilicon gate structure; forming the at least one dummy body to fill the at least one groove; and After removing the polysilicon gate structure, the metal gate structure is formed.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: Forming the at least one dummy body further comprises: forming a spacer on the sidewall of the polysilicon gate structure; forming the dielectric layer to surround the polysilicon gate structure; and When the spacer is formed, the at least one dummy body is formed.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: Forming the at least one dummy body further comprises: forming a spacer on the sidewall of the polysilicon gate structure; forming the dielectric layer to surround the polysilicon gate structure; and When forming the spacer, a portion of the at least one dummy body is formed, and when forming the dielectric layer, another portion of the at least one dummy body is formed.

20. The method for manufacturing a semiconductor device according to claim 17, wherein: Forming the metal gate structure also includes: removing the polysilicon layer of the polysilicon gate structure to form a gate trench; Sequentially forming a high dielectric constant material layer, a work function metal material layer, a barrier material layer and a conductive material layer in the gate trench to cover the at least one dummy body; Performing a planarization process using the at least one dummy body; and The metal gate structure is formed.

Images