Gate structure of semiconductor device and semiconductor device
By introducing a bidirectional complementary barrier structure into the gate structure of the gallium nitride semiconductor device, the material diffusion between the gate main layer and the contact layer is solved, and the problem of material diffusion at high temperature and high power is improved, and the stability and reliability of the device are improved.
Patent Information
- Application Number
- CN202311082573.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-25
- Publication Date
- 2025-02-28
AI Technical Summary
Under high temperature and high power operating conditions, gallium nitride semiconductor devices cause diffusion of gate internal materials, especially metal materials, which affects the stability of the device.
A gate structure of a semiconductor device is designed, including a gate contact layer arranged in a stack, a bidirectional complementary barrier structure and a gate body layer. The bidirectional complementary barrier structure blocks the diffusion of material between the gate body layer and the gate contact layer through the first and second barrier layers.
It effectively blocks the diffusion of material between the gate body layer and the gate contact layer, improves the stability of the gate, and thus improves the overall stability and reliability of the semiconductor device.
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Figure CN119545879A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronic technology, and in particular to a gate structure of a semiconductor device and a semiconductor device. Background Art
[0002] The semiconductor material gallium nitride has become a research hotspot due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In terms of electronic devices, gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices than silicon and gallium arsenide. It has broad application prospects and has become a research hotspot in the semiconductor industry.
[0003] Since GaN-based electronic devices operate at high temperatures and high power, the temperature inside the device is very high. Key internal layers, such as materials in the gate such as metal, will diffuse significantly when the device is operating, which will cause changes in the device's gate control. Therefore, the stability of the gate is particularly important.
[0004] Therefore, improving the diffusion of materials inside the gate, especially the mutual diffusion of metal materials, is an issue that needs to be urgently addressed. Summary of the invention
[0005] The embodiments of the present invention provide a gate structure of a semiconductor device and a semiconductor device, which can prevent materials in a gate main layer and a gate contact layer from diffusing each other, ensure the stability of the gate, and further improve the stability and reliability of the semiconductor device.
[0006] In a first aspect, an embodiment of the present invention provides a gate structure of a semiconductor device, including:
[0007] The gate comprises a gate contact layer, a bidirectional complementary barrier structure and a gate main body layer which are stacked; the bidirectional complementary barrier structure is used to simultaneously block the diffusion of materials on both sides of the bidirectional complementary barrier structure.
[0008] Optionally, the bidirectional complementary blocking structure includes a first blocking layer and a second blocking layer, wherein the first blocking layer blocks the material located on the side of the second blocking layer away from the first blocking layer from diffusing toward the first blocking layer, and the second blocking layer blocks the material located on the side of the first blocking layer away from the second blocking layer from diffusing toward the second blocking layer.
[0009] Optionally, the first barrier layer is located between the film layer where the gate contact layer is located and the film layer where the second barrier layer is located, and the second barrier layer is located between the film layer where the first barrier layer is located and the film layer where the gate main layer is located; the first barrier layer is used to block the metal in the gate main layer from diffusing into the gate contact layer, and the second barrier layer is used to block the metal in the gate contact layer from diffusing into the gate main layer.
[0010] Optionally, a material of the second barrier layer is the same as a material of the gate contact layer.
[0011] Optionally, a work function of the gate contact layer is greater than a work function of the first barrier layer.
[0012] Optionally, the gate contact layer has a thickness of d1, the first barrier layer has a thickness of d2, and the second barrier layer has a thickness of d3;
[0013] Among them, |d1-d2|≤50nm, |d2-d3|≤50nm.
[0014] Optionally, the gate contact layer has a thickness of d1, the first barrier layer has a thickness of d2, the second barrier layer has a thickness of d3, and the gate body layer has a thickness of d4;
[0015] Among them, d4 / d1≥10, d4 / d2≥10, d4 / d3≥10.
[0016] Optionally, the material of the gate contact layer includes nickel, titanium, tungsten, titanium nitride or tungsten nitride.
[0017] Optionally, the material of the first barrier layer includes platinum;
[0018] The material of the gate body layer includes gold.
[0019] In a second aspect, an embodiment of the present invention further provides a semiconductor device, comprising the gate structure described in any one of the first aspects, the semiconductor device comprising a substrate;
[0020] An epitaxial structure, located on one side of the substrate;
[0021] a gate, located at a side of the epitaxial structure away from the substrate;
[0022] A source electrode and a drain electrode, wherein the gate electrode is located between the source electrode and the drain electrode;
[0023] The epitaxial structure comprises a buffer layer, a channel layer and a barrier layer which are stacked, and the barrier layer and the channel layer form a heterojunction structure;
[0024] The gate comprises a gate contact layer, a bidirectional complementary barrier structure and a gate main body layer which are stacked;
[0025] The gate contact layer forms a Schottky contact with the barrier layer.
[0026] According to the technical solution provided by the embodiment of the present invention, the gate structure of the semiconductor device includes a gate contact layer, a bidirectional complementary barrier structure and a gate main layer which are stacked, that is, the bidirectional complementary barrier structure is located between the gate contact layer and the gate main layer. The bidirectional complementary barrier structure is used to simultaneously block the diffusion of materials on both sides of the bidirectional complementary barrier structure, that is, the bidirectional complementary barrier structure can block the metal in the gate main layer from diffusing to the gate contact layer, and at the same time, the bidirectional complementary barrier structure can also block the metal in the gate contact layer from diffusing to the gate main layer, so that the bidirectional complementary barrier structure can block the mutual diffusion of materials in the gate main layer and the gate contact layer, thereby ensuring the stability of the gate and thus improving the stability and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 A schematic structural diagram of a gate structure of a semiconductor device provided by an embodiment of the present invention;
[0028] Figure 2 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention;
[0029] Figure 3 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0031] Figure 1 A schematic diagram of a gate structure of a semiconductor device provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, in the gate structure of the semiconductor device, the gate 30 includes a stacked gate contact layer 301, a bidirectional complementary barrier structure 302 and a gate body layer 303; the bidirectional complementary barrier structure 302 is used to simultaneously block the diffusion of materials on both sides of the bidirectional complementary barrier structure 30.
[0032] Specifically, the gate 30 includes a stacked gate contact layer 301, a bidirectional complementary blocking structure 302 and a gate main layer 303. That is, the bidirectional complementary blocking structure 302 is arranged between the gate contact layer 301 and the gate main layer 303 to block the diffusion of materials on both sides of the bidirectional complementary blocking structure 302. Since semiconductor devices are accompanied by high temperature and high power when working, some materials will diffuse inside the gate 30. By setting the bidirectional complementary blocking structure 302, it is possible to block the material located on the side close to the gate contact layer 301 from diffusing to the side of the gate main layer 303, and it is also possible to block the material located on the side close to the gate main layer 303 from diffusing to the side of the gate contact layer 301, that is, it is possible to achieve bidirectional blocking of the diffusion of materials inside the gate 30.
[0033] The semiconductor device provided by the embodiment of the present invention comprises a gate including a gate contact layer, a bidirectional complementary barrier structure and a gate main layer which are stacked, that is, the bidirectional complementary barrier structure is located between the gate contact layer and the gate main layer. Optionally, other film layers suitable for the gate may be arranged between the bidirectional complementary barrier structure and the gate contact layer, and other film layers suitable for the gate may be arranged between the bidirectional complementary barrier structure and the gate main layer. The bidirectional complementary barrier structure is used to simultaneously block the diffusion of materials on both sides of the bidirectional complementary barrier structure, and the bidirectional complementary barrier structure blocks the diffusion of materials of at least one film layer on both sides thereof; in particular, the bidirectional complementary barrier structure can block the diffusion of materials in the gate main layer to the gate contact layer, and at the same time, the bidirectional complementary barrier structure can also block the diffusion of materials in the gate contact layer to the gate main layer, so that the bidirectional complementary barrier structure can block the mutual diffusion of materials in the gate main layer and the gate contact layer, thereby ensuring the stability of the gate, and thus improving the stability and reliability of the semiconductor device.
[0034] For further information, please refer to Figure 1 The bidirectional complementary barrier structure 302 includes a first barrier layer 3021 and a second barrier layer 3022. The first barrier layer 3021 can block the material located on the side of the second barrier layer 3022 away from the first barrier layer 3021 from diffusing toward the first barrier layer 3021, and the second barrier layer 3022 can block the material located on the side of the first barrier layer 3021 away from the second barrier layer 3022 from diffusing toward the second barrier layer 3022. In other words, the bidirectional complementary barrier structure 302 can achieve bidirectional blocking of the metal inside the gate 30, thereby improving the stability of the gate 30.
[0035] Optional, continue to refer to Figure 1The first barrier layer 3021 is located between the film layer where the gate contact layer 301 is located and the film layer where the second barrier layer 3022 is located, and the second barrier layer 3022 is located between the film layer where the first barrier layer 3021 is located and the film layer where the gate main layer 303 is located; the first barrier layer 3021 is used to block the material in the gate main layer 303 from diffusing into the gate contact layer 301, and the second barrier layer 3022 is used to block the material in the gate contact layer 301 from diffusing into the gate main layer 303.
[0036] Exemplarily, the first barrier layer 3021 is located between the film layer where the gate contact layer 301 is located and the film layer where the second barrier layer 3022 is located, and can block the material in the gate main layer 303 from diffusing into the gate contact layer 301; the second barrier layer 3022 is located between the film layer where the first barrier layer 3021 is located and the film layer where the gate main layer 303 is located, and can block the material in the gate contact layer 301 from diffusing into the gate main layer 303.
[0037] Specifically, the gate contact layer 301 forms a Schottky contact with the epitaxial structure 20, which can be understood as when the gate contact layer 301 contacts the epitaxial structure 20, the energy band of the semiconductor at the contact interface between the two is bent to form a Schottky barrier, and since there are a large number of interface charges in the barrier, the conductive performance of the gate 30 is guaranteed. The gate body layer 303, as the main structure of the gate 30, is used to receive the gate voltage and control the conduction and disconnection of the gate channel in the epitaxial structure 20 based on the gate voltage.
[0038] Optional, continue to refer to Figure 1 , the material of the second barrier layer 3022 is the same as that of the gate contact layer 301, that is, the bidirectional complementary barrier structure 302 and the gate contact layer 301 form a sandwich structure of blocking effect, and one of the outer layers of the sandwich structure, the second barrier layer 3022, blocks the other outer layer of the gate contact layer 301; in this way, even if the material in the gate contact layer 301 diffuses to the second barrier layer 3022, since the two materials are the same and the lattices match each other, the material in the gate contact layer 301 will not continue to diffuse to the gate body layer 303, or the second barrier layer 3022 can reduce the diffusion efficiency of the material in the gate contact layer 301 when diffusing to the gate body layer 303. In this way, the second barrier layer 3022 can block the material in the gate contact layer 301 from diffusing to the gate body layer 303, thereby ensuring the stability of the gate 30.
[0039] For further information, please refer to Figure 1The material of the gate contact layer 301 may include nickel, titanium, tungsten, titanium nitride or tungsten nitride. These materials have high melting points and stable properties, and can reduce the diffusion problem of the metal in the gate contact layer 301. In addition, when the gate contact layer 301 is made of the above materials, it can ensure that the gate contact layer 301 forms a good Schottky contact with the epitaxial structure 20, and ensure that the Schottky junction formed between the gate contact layer 301 and the epitaxial structure 20 has stable performance.
[0040] It should be noted that the material of the second barrier layer 3022 needs to be the same as that of the gate contact layer 301, so the material of the second barrier layer 3022 may include nickel, titanium, tungsten, titanium nitride or tungsten nitride. Since the two materials are the same, the lattices of the same metals match each other, and the metal in the gate contact layer 301 will not continue to diffuse into the gate body layer 303, or the second barrier layer 3022 can reduce the diffusion efficiency of the metal in the gate contact layer 301 when diffusing into the gate body layer 303. In this way, the second barrier layer 3022 can prevent the material in the gate contact layer 301 from diffusing into the gate body layer 303, thereby ensuring the stability of the gate 30.
[0041] Optional, continue to refer to Figure 1 , the work function of the gate contact layer 301 is greater than the work function of the first barrier layer 3021 .
[0042] Specifically, the work function can also be called work function or work function, which can be understood as the minimum energy required to move an electron from the inside of a solid to the surface of the object. In other words, the larger the work function, the less likely it is for the electrons contained in the film layer to escape from the surface of the film layer. The work function of the gate contact layer 301 is greater than the work function of the first barrier layer 3021, that is, the electrons in the gate contact layer 301 are relatively stable and are not likely to escape from the surface of the film layer of the gate contact layer 301. This is beneficial to the formation of Schottky contact between the gate contact layer 301 and the epitaxial structure, and can ensure that the electrons in the gate contact layer 301 are not likely to diffuse to the gate body layer 303.
[0043] Optional, continue to refer to Figure 1 The thickness of the gate contact layer 301 is d1, the thickness of the first barrier layer 3021 is d2, and the thickness of the second barrier layer 3022 is d3. Within the allowable range of device performance, d1, d2, and d3 can select a suitable numerical range as needed; preferably, |d1-d2|≤50nm, |d2-d3|≤50nm.
[0044] Specifically, the thickness d1 of the gate contact layer 301, the thickness d2 of the first barrier layer 3021, and the thickness d3 of the second barrier layer 3022 satisfy |d1-d2|≤50nm, |d2-d3|≤50nm, that is, the thickness of the first barrier layer 3021 is within 50nm of the thickness of the gate contact layer 301, and the thickness difference is not large. The thickness of the second barrier layer 3022 is within 50nm of the thickness of the gate contact layer 301, and the thickness difference is not large. In this way, the thickness of the gate contact layer 301, the first barrier layer 3021, and the second barrier layer 3022 can be ensured to be moderate. On the one hand, the Schottky contact between the gate contact layer 301 and the epitaxial structure 20 can be ensured to be stable, and the barrier performance of the first barrier layer 3021 and the second barrier layer 3022 to the diffused metal is stable, that is, the performance of each film layer can be ensured to be stable; on the other hand, the thickness difference between different film layers is not large, which reduces the process difficulty of the gate.
[0045] For further information, please refer to Figure 1 The thickness d1 of the gate contact layer 301 satisfies 5nm≤d1≤60nm, which can ensure that the thickness of the gate contact layer 301 is moderate, and thus ensure that the metal content in the gate contact layer 301 is moderate. On the one hand, it is beneficial for the gate contact layer 301 to form a Schottky contact with the epitaxial structure 20. On the other hand, even if there is a small amount of diffusion of metal in the gate contact layer 301, it will not have a significant impact on the performance of the gate 30.
[0046] Specifically, when d1 is less than 5 nm, it indicates that the thickness of the gate contact layer 301 is relatively thin. In this case, the film layer contains less metal. When the metal in the gate contact layer 301 is diffused, the gate contact layer 301 contains only a small amount of metal, which will have a significant impact on the performance of the gate 30. When d1 is greater than 60 nm, it indicates that the thickness of the gate contact layer 301 is relatively thick. In this case, the gate contact layer 301 will not form a Schottky contact with the epitaxial structure 20, but will form a conductive structure, which will have a significant impact on the performance of the gate 30.
[0047] Illustratively, the thickness of the gate contact layer 301 may be 10 nm, 15 nm, 20 nm, 25 nm, 35 nm, or 45 nm.
[0048] Optional, continue to refer to Figure 1 , the thickness of the gate contact layer 301 is d1, the thickness of the first barrier layer 3021 is d2, the thickness of the second barrier layer 3022 is d3, and the thickness of the gate body layer 303 is d4; wherein, d4 / d1≥10, d4 / d2≥10, and d4 / d3≥10.
[0049] Specifically, the thickness d1 of the gate contact layer 301, the thickness d2 of the first barrier layer 3021, the thickness d3 of the second barrier layer 3022, and the thickness d4 of the gate body layer 303 satisfy d4 / d1≥10, d4 / d2≥10, and d4 / d3≥10, that is, the thickness of the gate body layer 303 is thicker than the thickness of other metal film layers, ensuring that the gate body layer 303, as the main film layer of the gate 30, has good conductivity. Exemplarily, the thickness of the gate body layer 303 can be micrometer-level, and the thickness of the gate contact layer 301, the thickness of the first barrier layer 3021, and the thickness of the second barrier layer 3022 can all be nanometer-level.
[0050] Optional, continue to refer to Figure 1 , the material of the first barrier layer 3021 includes platinum; the material of the gate body layer 303 includes gold.
[0051] Specifically, the material of the first barrier layer 3021 includes platinum. The metal platinum material has high stability and is not easy to diffuse when the semiconductor device is working. Therefore, it can prevent the metal in the gate body layer 303 from diffusing to the gate contact layer 301. In addition, the material of the gate body layer 303 includes gold. On the one hand, the metal gold has good stability and a high melting point, so the stability of the gate 30 can be ensured. On the other hand, the metal gold has strong ductility, that is, it can have strong tensile force as the gate body layer 303.
[0052] In summary, the gate structure of the semiconductor device provided by the embodiment of the present invention comprises a gate contact layer, a bidirectional complementary barrier structure and a gate main body layer arranged in a stacked manner, that is, the bidirectional complementary barrier structure is located between the gate contact layer and the gate main body layer. The bidirectional complementary barrier structure comprises a first barrier layer and a second barrier layer, the first barrier layer is located between the film layer where the gate contact layer is located and the film layer where the second barrier layer is located, and can block the metal in the gate main body layer from diffusing into the gate contact layer, the second barrier layer is located between the film layer where the first barrier layer is located and the film layer where the gate main body layer is located, and can block the metal in the gate contact layer from diffusing into the gate main layer, so that the bidirectional complementary barrier structure can block the materials in the gate main layer and the gate contact layer from diffusing into each other, thereby ensuring the stability of the gate, and thus improving the stability and reliability of the semiconductor device.
[0053] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device, the semiconductor device comprising the gate structure provided by the above embodiment, Figure 2 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, Figure 3 A schematic diagram of the structure of another semiconductor device is provided for an embodiment of the present invention, such as Figure 2 and Figure 3As shown, the semiconductor device includes a substrate 10; an epitaxial structure 20, which is located on one side of the substrate 10; a gate 30, which is located on the side of the epitaxial structure 20 away from the substrate 10; a source 40 and a drain 50, and the gate 30 is located between the source 40 and the drain 50; the epitaxial structure 20 includes a buffer layer 201, a channel layer 202 and a barrier layer 203 arranged in a stacked manner, and the barrier layer 203 forms a heterojunction structure with the channel layer 202; the gate 30 includes a gate contact layer 301, a bidirectional complementary blocking structure 302 and a gate main layer 303 arranged in a stacked manner; the gate contact layer 301 forms a Schottky contact with the barrier layer 203.
[0054] Specifically, the substrate 10 can be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. The substrate 10 can also be any other material that can grow group III nitrides.
[0055] Furthermore, the epitaxial structure 20 can be understood as a multilayer film structure generated on one side of the substrate 10 using an epitaxial process. The epitaxial structure 20 can be formed by one or more III-V group nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride or indium aluminum gallium nitride.
[0056] Specifically, the gate 30 is located on a side of the epitaxial structure 20 away from the substrate 10. The gate 30 includes a stacked gate contact layer 301, a bidirectional complementary blocking structure 302 and a gate main layer 303. The bidirectional complementary blocking structure 302 can block the diffusion of materials in the gate contact layer 301 and the gate main layer 303, thereby ensuring the stability of the gate 30.
[0057] Specifically, the source 40 may form an ohmic contact with the epitaxial structure 20. Exemplarily, the drain 50 may be used as the output terminal of the semiconductor device, the source 40 may be used as the input terminal of the semiconductor device, the gate 30 may be used as the control terminal of the semiconductor device, and the current flow between the drain 50 and the source 40 may be achieved by controlling the voltage of the gate 30. That is, when a certain voltage is applied to the gate 30, a current will be generated between the drain 50 and the source 40, and the current between the drain 50 and the source 40 may be controlled by changing the gate 30 voltage.
[0058] For example, continue to refer to Figure 3 The buffer layer 201 is located on one side of the substrate 10. The material of the buffer layer 201 may be gallium nitride, and the buffer layer 201 may include iron atoms, which is conducive to achieving the high resistance performance of the buffer layer 201. On the one hand, the buffer layer 201 can block vertical leakage and improve the pinch-off performance of the semiconductor device. On the other hand, it can improve the quality of the semiconductor film layer that needs to be grown subsequently.
[0059] For example, the channel layer 202 may be a group III nitride, such as Al x Ga 1－x N, where 0≤x<1, that is, at the interface between the channel layer 202 and the barrier layer 203, that is, the energy of the conduction band edge of the channel layer 202 is less than the energy of the conduction band edge of the barrier layer 203. Exemplarily, x=0 indicates that the channel layer 202 is GaN. The channel layer 202 may also be other III-group nitrides, such as InGaN and AlInGaN. The channel layer 202 may be undoped or unintentionally doped. The channel layer 202 may also be a multilayer structure, such as a combination of a superlattice, GaN or AlGaN.
[0060] Exemplarily, the barrier layer 203 may be AlN, AlInN, AlGaN or AlInGaN. The barrier layer 203 has a sufficient thickness and a sufficiently high Al component so that doping forms a significant carrier concentration at the interface between the channel layer 202 and the barrier layer 203. Exemplarily, the thickness of the barrier layer 203 may be 20 nm, and the doping concentration of the Al component may be 25%.
[0061] Exemplarily, the channel layer 202 may include GaN, and the barrier layer 203 may include AlGaN, that is, the material of the barrier layer 203 has a higher band gap than the material of the channel layer 202, and the channel layer 202 may also have a greater electron affinity than the barrier layer 203. Due to the band gap difference between the barrier layer 203 and the channel layer 202 and the piezoelectric effect at the interface between the barrier layer 203 and the channel layer 202, a two-dimensional electron gas (2DEG) is formed in the channel layer 202 and the barrier layer 203. Among them, a better two-dimensional electron gas interface can be obtained through the channel layer 202, interface scattering is reduced, and mobility and two-dimensional electron gas concentration are improved.
[0062] It is understandable that the epitaxial structure 20 may further include a nucleation layer. The material of the nucleation layer may be aluminum nitride, which is located between the substrate 10 and the buffer layer 201 to serve as a bonding agent for the semiconductor material layer to be grown next.
[0063] It is understandable that the epitaxial structure 20 may further include a cap layer, which is located on the surface of the barrier layer 203 away from the substrate 10. The cap layer can reduce the surface state, reduce the surface leakage of the subsequent semiconductor device, and inhibit current collapse, thereby improving the performance and reliability of the epitaxial structure 20 and the semiconductor device.
[0064] It should be noted that the upper surface of the epitaxial structure 20 may further include a dielectric layer, which may be used to passivate and protect the epitaxial structure 20 .
[0065] It should be understood that the embodiment of the present invention is from the perspective of semiconductor device design, by setting a bidirectional complementary blocking structure between the gate contact layer and the gate main layer, and the bidirectional complementary blocking structure includes a first blocking structure and a second blocking structure. The first blocking structure can block the material in the gate main layer from diffusing into the gate contact layer, and the second blocking structure can block the material in the gate contact layer from diffusing into the gate main layer. In this way, the materials in the gate main layer and the gate contact layer can be blocked from diffusing into each other, thereby ensuring the stability of the gate, and thereby improving the stability and reliability of the semiconductor device. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMT) operating in high voltage and high current environments, transistors with silicon-on-insulator (SOI) structures, transistors based on gallium arsenide (GaAs), and metal-oxide-semiconductor field-effect transistors (MOSFET), metal-insulator semiconductor field-effect transistors (MISFET), double heterojunction field-effect transistors (DHFET), junction field-effect transistors (JFET), metal-semiconductor field-effect transistors (MESFET), and metal-insulator semiconductor heterojunction field-effect transistors. Transistor, referred to as MISHFET) or other field effect transistors. The bidirectional complementary barrier structure provided in the semiconductor device provided by the embodiment of the present invention can be widely used in the semiconductor device manufacturing fields such as radio frequency microwave and power electronics. In particular, the advantages of gallium nitride electronic devices with large bandgap width, high electron mobility, high breakdown field strength and good thermal conductivity are more obvious, and can better meet the high performance requirements of rapidly developing electronic communications and other fields.
[0066] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A gate structure of a semiconductor device, characterized in that: The gate comprises a gate contact layer, a bidirectional complementary barrier structure and a gate main body layer which are stacked; the bidirectional complementary barrier structure is used to simultaneously block the diffusion of materials on both sides of the bidirectional complementary barrier structure.
2. The gate structure according to claim 1, characterized in that: The bidirectional complementary barrier structure includes a first barrier layer and a second barrier layer, wherein the first barrier layer blocks the material located on the side of the second barrier layer away from the first barrier layer from diffusing toward the first barrier layer, and the second barrier layer blocks the material located on the side of the first barrier layer away from the second barrier layer from diffusing toward the second barrier layer.
3. The gate structure according to claim 2, characterized in that: The first barrier layer is located between the film layer where the gate contact layer is located and the film layer where the second barrier layer is located, and the second barrier layer is located between the film layer where the first barrier layer is located and the film layer where the gate main layer is located; the first barrier layer is used to block the material in the gate main layer from diffusing into the gate contact layer, and the second barrier layer is used to block the material in the gate contact layer from diffusing into the gate main layer.
4. The gate structure according to claim 2, characterized in that: The material of the second barrier layer is the same as that of the gate contact layer.
5. The gate structure according to claim 2, characterized in that: A work function of the gate contact layer is greater than a work function of the first barrier layer.
6. The gate structure according to claim 2, characterized in that: The thickness of the gate contact layer is d1, the thickness of the first barrier layer is d2, and the thickness of the second barrier layer is d3; Among them, |d1-d2|≤50nm, |d2-d3|≤50nm.
7. The gate structure according to claim 2, characterized in that: The thickness of the gate contact layer is d1, the thickness of the first barrier layer is d2, the thickness of the second barrier layer is d3, and the thickness of the gate main layer is d4; Among them, d4 / d1≥10, d4 / d2≥10, d4 / d3≥10.
8. The gate structure according to claim 3, characterized in that: The material of the gate contact layer includes nickel, titanium, tungsten, titanium nitride or tungsten nitride.
9. The gate structure according to claim 2, characterized in that: The material of the first barrier layer includes platinum; The material of the gate body layer includes gold.
10. A semiconductor device comprising the gate structure according to any one of claims 1 to 9, characterized in that: including a substrate; An epitaxial structure, located on one side of the substrate; a gate, located at a side of the epitaxial structure away from the substrate; A source electrode and a drain electrode, wherein the gate electrode is located between the source electrode and the drain electrode; The epitaxial structure comprises a buffer layer, a channel layer and a barrier layer which are stacked, and the barrier layer and the channel layer form a heterojunction structure; The gate comprises a gate contact layer, a bidirectional complementary barrier structure and a gate main body layer which are stacked; The gate contact layer forms a Schottky contact with the barrier layer.