Transistor structure
By designing the metal gate side with a nonlinear shape, including multiple protrusions and trenches, the problem of reducing the thickness of the metal gate in the semiconductor transistor structure is solved, and the electrical performance of the components is improved.
Patent Information
- Application Number
- CN202311234419.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-25
- Filing Date
- 2023-09-22
- Publication Date
- 2025-02-28
AI Technical Summary
In the semiconductor transistor structure, after using the metal gate process, the thickness of the metal gate is easily reduced due to chemical mechanical polishing, which leads to the problem of the metal gate being penetrated, affecting the electrical properties of the components.
A transistor structure is designed, with the gate having a nonlinear shape in the side of the direction interleaved with the channel length, including a plurality of protrusions and trenches, avoiding the occurrence of a dish-like phenomenon during chemical mechanical polishing.
The problem of reducing the thickness of the metal gate is effectively avoided, ensuring that the shape and thickness of the metal gate are unchanged, thereby avoiding the problem of the metal gate being penetrated when the contact is formed, and improving the electrical performance of the components.
Smart Images
Figure CN119545880A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure, and in particular to a transistor structure. Background Art
[0002] With the development of semiconductor technology, the demand for smaller device size and higher performance is increasing. In order to solve the electrical problem caused by the reduction of gate size, a technology of using a metal gate to replace a polysilicon gate has been developed. The method of forming the above-mentioned metal gate is usually to remove the dummy polysilicon gate after forming a dummy polysilicon gate, and then fill it with metal material as a metal gate. This method is usually called a gate-last process or a replacement metal gate process.
[0003] In the above process, after removing the dummy polysilicon gate, metal material is filled into the space accommodating the dummy polysilicon gate, and a chemical mechanical polishing (CMP) process is performed to remove the metal material outside the space. However, for a metal gate having a larger area, after the chemical mechanical polishing process, the metal gate is prone to dishing and the thickness is reduced. As a result, when forming a contact connected to the metal gate, the metal gate is easily penetrated, resulting in the electrical properties of the component being affected. Summary of the invention
[0004] The present invention is directed to a transistor structure, wherein the edge of a gate has a nonlinear shape when viewed from above a substrate.
[0005] The transistor structure of the present invention comprises a gate, a gate dielectric layer, a source region and a drain region. The gate is disposed on a substrate. The gate dielectric layer is disposed between the gate and the substrate. The source region and the drain region are disposed on opposite sides of the gate, respectively. From a top view from above the substrate, the gate has two opposite sides in a first direction, the first direction intersects with a second direction where the channel length of the transistor structure is located, and each of the two sides has a nonlinear shape.
[0006] In an embodiment of the transistor structure of the present invention, each of the two side edges has a plurality of protrusions when viewed from above the substrate.
[0007] In an embodiment of the transistor structure of the present invention, the outline of the protrusion is a rectangle when viewed from above the substrate.
[0008] In an embodiment of the transistor structure of the present invention, the corners of the protrusion are rounded when viewed from above the substrate.
[0009] In an embodiment of the transistor structure of the present invention, the nonlinear shape includes a wave shape when viewed from above the substrate.
[0010] In an embodiment of the transistor structure of the present invention, when viewed from above the substrate, a ratio of a length of the protrusion from the side to a distance between two adjacent protrusions is between 0.5 and 1.
[0011] In an embodiment of the transistor structure of the present invention, the length is between 160 nm and 330 nm.
[0012] In an embodiment of the transistor structure of the present invention, the sidewall of the gate in the first direction has a plurality of trenches, and each of the trenches extends from the bottom of the gate to the top of the gate.
[0013] In an embodiment of the transistor structure of the present invention, the material of the gate includes polysilicon.
[0014] In an embodiment of the transistor structure of the present invention, the material of the gate includes metal.
[0015] In an embodiment of the transistor structure of the present invention, an etching stop layer is further included on the sidewall of the gate.
[0016] In an embodiment of the transistor structure of the present invention, the material of the etching stop layer includes silicon nitride.
[0017] In summary, in the transistor structure of the present invention, the side of the gate in a direction intersecting with the direction of the channel length has a nonlinear shape when viewed from above the substrate. As a result, after the replacement metal gate process is performed on the transistor structure, the thickness of the gate will not be reduced, thereby effectively avoiding the problem of gate penetration when forming a contact connected to the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1A is a schematic top view of a transistor structure according to a first embodiment of the present invention;
[0019] Figure 1B yes Figure 1A A three-dimensional schematic diagram of the transistor structure in FIG.
[0020] Figure 2 is a schematic top view of a transistor structure according to a second embodiment of the present invention;
[0021] Figure 3 is a schematic top view of a transistor structure according to a third embodiment of the present invention;
[0022] Figure 4A is a schematic top view of a transistor structure according to a fourth embodiment of the present invention;
[0023] Figure 4B yes Figure 4A A three-dimensional schematic diagram of the transistor structure in FIG.
[0024] Figure 4C is along Figure 4B Schematic diagram of the cross section of the AA section line. DETAILED DESCRIPTION
[0025] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components are indicated by the same symbols in the following description.
[0026] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".
[0027] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component may also be referred to as the second component, and the second component may also be referred to as the first component, and this does not deviate from the scope of the present invention.
[0028] In addition, directional terms such as "upper", "lower", etc. mentioned herein are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when a component such as a layer or film is placed "on" another component, the component can be placed directly on the other component, or there can be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between the two.
[0029] In addition, in this article, the range expressed by "a value to another value" is a summary expression method to avoid listing all the values in the range one by one in the specification. Therefore, the description of a specific numerical range covers any value in the numerical range, and covers a smaller numerical range defined by any value in the numerical range.
[0030] Figure 1A FIG. 1 is a schematic top view of a transistor structure according to a first embodiment of the present invention. Figure 1B yes Figure 1A A three-dimensional schematic diagram of the transistor structure in .
[0031] Please also refer to Figure 1A and Figure 1B , the transistor structure 10 of the present embodiment includes a gate 102, a gate dielectric layer 104, a source region 106a and a drain region 106b. The gate 102 is disposed on a substrate 100. In the present embodiment, the substrate 100 may be a silicon substrate, but the present invention is not limited thereto. In other embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate. In the present embodiment, the material of the gate 102 is polysilicon, but the present invention is not limited thereto. In addition, a spacer is disposed on the sidewall of the gate 102. To make the drawings clear, Figure 1A and Figure 1B The spacer is not shown in the figure. The source region 106a and the drain region 106b are respectively disposed on opposite sides of the gate 102. In the present embodiment, the source region 106a and the drain region 106b are doped regions located in the substrate 100, but the present invention is not limited thereto. In other embodiments, the source region 106a and the drain region 106b may be doped semiconductor layers buried in the substrate 100 and / or disposed on the substrate 100.
[0032] In the transistor structure 10, the region between the source region 106a and the drain region 106b serves as a channel region, which has a channel length Lc. In this embodiment, the channel length Lc is the distance between the source region 106a and the drain region 106b. Figure 1A and Figure 1B As shown, the source region 106 a and the drain region 106 b are disposed on opposite sides of the gate 102 in the direction X, respectively, so the channel length Lc is located in the direction X.
[0033] From the top view direction above the substrate 100, the gate 102 has two opposite side edges E1 and E2 in the direction Y intersecting with the direction X, and the side edges E1 and E2 each have a nonlinear shape as a whole. In detail, the side edges E1 and E2 each have a plurality of protrusions 102a. These protrusions 102a protrude from the side edges E1 and E2. In the present embodiment, the number of the protrusions 102a located at the side edges E1 is the same as the number of the protrusions 102a located at the side edges E2, but the present invention is not limited thereto.
[0034] like Figure 1B As shown, in the direction Y, the two sidewalls SW of the gate 102 have a plurality of grooves G, and each groove G extends from the bottom of the gate 102 to the top of the gate 102. That is, the area between adjacent protrusions 102a is the groove G.
[0035] At the side E1, the length L of the protrusion 102a protruding from the side E1 may be between 160nm and 330nm, and the lengths L of the protrusions 102a may be the same or different, which is not limited by the present invention. In addition, in this embodiment, the ratio r of the length L to the spacing P between two adjacent protrusions 102a is between 0.5 and 1.
[0036] At the side E2, the length L of the protrusion 102a protruding from the side E2 may be between 160nm and 330nm, and the lengths L of these protrusions 102a may be the same or different from each other. In addition, the ratio r of the length L to the spacing P between two adjacent protrusions 102a is between 0.5 and 1. The length L and the ratio r at the side E1 may be the same or different from the length L and the ratio r at the side E2, and the present invention is not limited thereto.
[0037] In the present embodiment, the sidewall SW of the transistor structure 10 in the direction Y intersecting with the direction X in which the channel length Lc is located has a plurality of grooves G, so that the side E1 and the side E2 in the direction Y viewed from the top view above the substrate 100 each have a plurality of protrusions 102a and have a nonlinear shape. In this way, when the replacement metal gate process is performed on the transistor structure 10, the dishing phenomenon will not be generated during the chemical mechanical polishing process, so that the formed metal gate can have the same shape and thickness as the gate 102. Therefore, the problem of the metal gate being penetrated when forming a contact connected to the metal gate can be effectively avoided.
[0038] In the present embodiment, the length L of the protrusion 102a protruding from the side of the gate 102 is between 160nm and 330nm. When the length L is greater than 330nm, the size of the gate 102 will be too large and affect the layout design of the semiconductor device. When the length L is less than 160nm, the dishing phenomenon cannot be effectively avoided when the above-mentioned replacement metal gate process is performed. In addition, in the present embodiment, the ratio r of the length L to the spacing P between two adjacent protrusions 102a is between 0.5 and 1. When the spacing P between two adjacent protrusions 102a is too large, that is, when r is less than 0.5, the dishing phenomenon cannot be effectively avoided when the above-mentioned replacement metal gate process is performed.
[0039] In this embodiment, the outline of the protrusion 102a is rectangular when viewed from above the substrate 100, but the present invention is not limited thereto. In other embodiments, the outline of the protrusion 102a can be other shapes when viewed from above the substrate 100.
[0040] Figure 22 is a top view schematic diagram of a transistor structure of a second embodiment of the present invention. In this embodiment, the same components as those of the first embodiment are represented by the same reference symbols and will not be described again.
[0041] Please refer to Figure 2 In the transistor structure 20 of the present embodiment, the outline of the protrusion 102a is rectangular, and the corners of the protrusion 102b have rounded corners when viewed from above the substrate 100. In other embodiments, when the outline of the protrusion is rectangular, the corners of the protrusion may also have beveled corners.
[0042] Figure 3 1 is a top view schematic diagram of a transistor structure of a third embodiment of the present invention. In this embodiment, the same components as those of the first embodiment are represented by the same reference symbols and will not be described again.
[0043] Please refer to Figure 3 In the transistor structure 30 of the present embodiment, when viewed from above the substrate 100 , the profile of the protrusion 102 c is curved, and the side E1 and the side E2 are wavy.
[0044] In the above embodiments, the side E1 and the side E2 of the gate 102 have the same form, but the present invention is not limited thereto. In other embodiments, the side E1 and the side E2 of the gate 102 may have different forms, that is, the side E1 and the side E2 of the gate 102 may each have one of the protrusion 102a, the protrusion 102b and the protrusion 102c.
[0045] Figure 4B FIG. 4 is a schematic top view of a transistor structure according to a fourth embodiment of the present invention. Figure 4B yes Figure 4A A three-dimensional schematic diagram of the transistor structure in . Figure 4C is along Figure 4B In this embodiment, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described again.
[0046] Please also refer to Figure 4A , Figure 4B and Figure 4CIn the transistor structure 40 of the present embodiment, an etching stop layer 108 is disposed on the side wall SW of the gate 102. Specifically, in the present embodiment, the etching stop layer 108 is disposed on the substrate 100 to cover the surface of the substrate 100 and the side wall SW of the gate 102, and to expose the top surface of the gate 102. In the present embodiment, the material of the etching stop layer 108 includes silicon nitride, but the present invention is not limited thereto. When the etching stop layer 108 is disposed on the side wall of the gate 102, the dishing phenomenon caused by chemical mechanical polishing can be effectively avoided when performing the replacement metal gate process.
[0047] Similarly, the etch stop layer 108 may be disposed on the sidewall SW of the gate 102 in the second embodiment, the third embodiment, etc.
[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A transistor structure, characterized in that: include: A gate is disposed on the substrate; A gate dielectric layer, disposed between the gate and the substrate; as well as The source region and the drain region are respectively arranged on opposite sides of the gate. The gate has two opposite sides in a first direction when viewed from above the substrate, the first direction intersects with a second direction where the channel length of the transistor structure is located, and each of the two sides has a nonlinear shape.
2. The transistor structure according to claim 1, characterized in that: Each of the two side edges has a plurality of protrusions when viewed from above the substrate.
3. The transistor structure according to claim 2, characterized in that: When viewed from above the substrate, the protrusion has a rectangular outline.
4. The transistor structure according to claim 2, characterized in that: The protrusion has rounded corners when viewed from above the substrate.
5. The transistor structure according to claim 2, characterized in that: The nonlinear shape includes a wave shape when viewed from above the substrate.
6. The transistor structure according to claim 2, characterized in that: When viewed from above the substrate, a ratio of a length of the protrusion protruding from the side edge to a distance between two adjacent protrusions is between 0.5 and 1.
7. The transistor structure according to claim 6, characterized in that: The length is between 160 nm and 330 nm.
8. The transistor structure according to claim 1, characterized in that: The sidewall of the gate in the first direction has a plurality of trenches, and each of the trenches extends from the bottom of the gate to the top of the gate.
9. The transistor structure according to claim 1, characterized in that: The gate is made of polysilicon.
10. The transistor structure according to claim 1, characterized in that: The material of the gate includes metal.
11. The transistor structure according to claim 1, characterized in that: It also includes an etching stop layer, which is arranged on the side wall of the gate.
12. The transistor structure according to claim 11, characterized in that: The material of the etching stop layer includes silicon nitride.