Semiconductor structure and preparation method thereof, semiconductor layout, MOS device

Abstract

The embodiments of this specification provide a semiconductor structure and a method for preparing the same, a semiconductor layout, and a MOS device. The preparation method includes: providing a semiconductor substrate; the semiconductor substrate includes a shallow trench isolation region, and an active region defined by the shallow trench isolation region; wherein a pit connected to the surface of the active region is formed on the surface of the shallow trench isolation region; the pit has a rising surface extending from the bottom of the pit to the top of the pit away from the active region; a pseudo gate structure is made on the semiconductor substrate; the pseudo gate structure includes a functional layer in contact with the shallow trench isolation region and a pseudo gate material layer stacked on the functional layer; wherein a contact surface is provided between the functional layer and the shallow trench isolation region, and the contact surface does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface; a gate structure is prepared corresponding to the position of the pseudo gate structure. In this way, the missing of the functional layer and the damage to the active region in the preparation process can be reduced.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, a semiconductor layout, and a MOS device. Background Art

[0002] At present, in the process of preparing some gate structures, it is necessary to first use a dummy gate material to form a dummy gate structure on a semiconductor substrate, and use the dummy gate structure as a position reference to perform subsequent process steps, such as making gate sidewalls, interlayer dielectric layers, etc. Then, the dummy gate material is removed based on the DPRM (Dummy Poly Removal) process, and the gate material is used to prepare a gate structure.

[0003] The dummy gate structure usually also includes a functional layer consisting of a gate dielectric layer and an etch stop layer, which is located between the dummy gate material and the semiconductor substrate. However, technicians have found that after the dummy gate material is removed through the DPRM process, the functional layer is missing and the active area of ​​the semiconductor substrate is also damaged to a large extent, which affects the electrical performance and reliability of the product. Summary of the invention

[0004] In view of this, multiple embodiments of this specification are dedicated to providing a semiconductor structure and a method for manufacturing the same, a semiconductor layout, and a MOS device, which can reduce the loss of functional layers and damage to active areas in the manufacturing process.

[0005] An embodiment of the present specification provides a method for preparing a semiconductor structure, the method comprising: providing a semiconductor substrate; the semiconductor substrate comprising a shallow trench isolation region, and an active region defined by the shallow trench isolation region; wherein a pit connected to the surface of the active region is formed on the surface of the shallow trench isolation region; the pit has a rising surface extending from the bottom of the pit to the top of the pit away from the active region; a dummy gate structure is fabricated on the semiconductor substrate; the dummy gate structure comprises a functional layer in contact with the shallow trench isolation region and a dummy gate material layer stacked on the functional layer; wherein a contact surface is provided between the functional layer and the shallow trench isolation region, and the contact surface does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface; and a gate structure is prepared corresponding to the position of the dummy gate structure.

[0006] Optionally, the junction between the pit and the surface of the active area forms the top of the other side of the pit; the pit also has a descending surface extending from the top of the other side to the bottom of the pit; the width of the contact surface between the functional layer and the shallow trench isolation area is smaller than the width of the descending surface, or larger than the width of the pit.

[0007] Optionally, corresponding to the position of the dummy gate structure, the step of preparing a gate structure includes: forming a first side wall on both sides of the dummy gate structure; wherein both sides of the functional layer are respectively covered by the first side wall; forming a second side wall on the side of the first side wall away from the dummy gate structure; the first side wall and the second side wall constitute a gate side wall; removing the dummy gate material layer to form a trench between the gate side walls on both sides of the dummy gate structure; and preparing a gate structure corresponding to the position of the trench.

[0008] Optionally, the functional layer includes a gate dielectric layer in contact with the shallow trench isolation region and an etch stop layer disposed on the gate dielectric layer; and the dummy gate material layer is stacked on the etch stop layer.

[0009] An embodiment of the present specification provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate comprising a shallow trench isolation region, and an active region defined by the shallow trench isolation region; wherein a pit connected to the surface of the active region is formed on the surface of the shallow trench isolation region; the pit has a rising surface extending from the bottom of the pit to the top of the pit away from the active region; a gate structure, the gate structure comprising a functional layer in contact with the shallow trench isolation region and a gate material layer stacked on the functional layer; wherein a contact surface is provided between the functional layer and the shallow trench isolation region, and the contact surface does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface.

[0010] Optionally, the junction between the pit and the surface of the active area forms the top of the other side of the pit; the pit also has a descending surface extending from the top of the other side to the bottom of the pit; the width of the contact surface between the functional layer and the shallow trench isolation area is smaller than the width of the descending surface, or larger than the width of the pit.

[0011] Optionally, a first sidewall and a second sidewall located on a side of the first sidewall away from the gate structure are further provided on both sides of the gate structure; wherein both sides of the functional layer are respectively covered by the first sidewall.

[0012] Optionally, the functional layer includes a gate dielectric layer in contact with the shallow trench isolation region and an etch stop layer disposed on the gate dielectric layer; and the gate material layer is stacked on the etch stop layer.

[0013] An embodiment of the present specification provides a semiconductor layout pattern, which is used to prepare a semiconductor structure as in the aforementioned embodiment or is used in a method for preparing a semiconductor structure as in the aforementioned embodiment; the semiconductor layout pattern includes: a semiconductor substrate pattern; the semiconductor substrate pattern includes a preset shallow trench isolation region and a preset active region defined by the preset shallow trench isolation region; the surface of the preset shallow trench isolation region is connected to the surface of the preset active region and forms a preset boundary line; a gate structure pattern; the gate structure pattern is located on the semiconductor substrate pattern and is in contact with the preset shallow trench isolation region and the preset active region at the same time; wherein, in the preset contact surface between the gate structure pattern and the preset shallow trench isolation region, the value range of the preset spacing between the boundary on one side away from the preset boundary line and the preset boundary line satisfies: so that the contact surface in the prepared semiconductor structure does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface.

[0014] An embodiment of the present specification provides a MOS device, wherein the MOS device includes a semiconductor structure as described in any of the foregoing embodiments, or is prepared by a method for preparing a semiconductor structure as described in any of the foregoing embodiments.

[0015] The multiple embodiments provided in this specification, by making the contact surface between the functional layer in the pseudo gate structure and the shallow trench isolation area avoid the rising surface of the surface pit of the shallow trench isolation area during the process of manufacturing the pseudo gate structure on the semiconductor substrate, have the unexpected effect of reducing the loss of functional layers and damage to the active area caused by subsequent process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a semiconductor substrate provided for one embodiment of the present specification.

[0017] Figure 2 and Figure 3 A schematic diagram of manufacturing a dummy gate structure on a semiconductor substrate is provided for one embodiment of the present specification.

[0018] Figure 4 and Figure 5 A schematic diagram of forming a gate spacer according to an embodiment of the present disclosure.

[0019] Figure 6 and Figure 7 A schematic diagram of providing an interlayer dielectric layer on the surface of a semiconductor substrate according to an embodiment of the present specification.

[0020] Figure 8 A schematic diagram of removing a dummy gate material layer provided in one embodiment of the present specification.

[0021] Fig. 9 and Fig.10 A schematic diagram of the analysis of functional layer loss and active area damage provided for one embodiment of this specification.

[0022] Fig.11 A schematic diagram of a method for preparing a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0023] Fig.12 A schematic diagram of the layout design and TEM analysis of a pseudo gate structure provided in one embodiment of this specification.

[0024] Fig.13 A schematic diagram of a semiconductor structure provided for one embodiment of the present specification.

[0025] Description of reference numerals:

[0026] 11. semiconductor substrate; 111. shallow trench isolation region; 112. active region; 113. pit; 114. rising surface; 115. descending surface; 12. gate oxide material layer; 13. functional material layer; 131. gate dielectric material layer; 132. etch stop material layer; 14. pseudo gate initial material layer; 15. hard mask material layer; 16. oxide material layer; 17. photoresist layer; 21. pseudo gate structure; 211. First side wall; 212, second side wall; 22, gate oxide layer; 23, functional layer; 231, gate dielectric layer; 232, etch stop layer; 24, pseudo gate material layer; 25, hard mask layer; 26, oxide layer; 27, gate side wall; 271, first side wall; 272, second side wall; 28, groove; 29, interlayer dielectric layer; 231, bottom foot; 232, weak point; 30, semiconductor structure; 31, gate structure. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of this specification will be described clearly and completely below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, rather than all the embodiments.

[0028] In this specification, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0029] Unless otherwise stated, all technical and scientific terms used in this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing the specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of this specification are also intended to include the majority form, unless the context clearly indicates other meanings.

[0030] In the description of this specification, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this specification, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this specification, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of simplified description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0032] In the description of this specification, unless otherwise clearly defined, the terms "install", "connect", "connect", "fix", "set", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] See also Figure 1-Figure 8 One embodiment of the present specification provides a method for preparing a semiconductor structure, which can be applied to related product processes at different process nodes, such as a 28nm process. The preparation method can specifically include the following steps.

[0034] S110: providing a semiconductor substrate.

[0035] Specifically, Figure 1 As shown, the semiconductor substrate 11 includes a shallow trench isolation (STI) region and an active area 112 (Active Area, AA) defined by the shallow trench isolation region 111. A divot 113 (divot) connected to the surface of the active area 112 is formed on the surface of the shallow trench isolation region 111, and the divot 113 has a rising surface 114 extending from the bottom of the divot 113 to the top of one side of the divot 113 away from the active area 112, and a descending surface 115 extending from the top of the other side to the bottom of the divot 113.

[0036] S120: Fabricating a dummy gate structure on a semiconductor substrate.

[0037] Specifically, Figure 2 As shown, a gate oxide material layer 12, a gate dielectric material layer 131 and an etch stop material layer 132 composed of a functional material layer 13, a dummy gate initial material layer 14, a hard mask material layer 15, an oxide material layer 16 and a photoresist layer 17 can be stacked on the semiconductor substrate 11. The photoresist layer 17 opens an etching window by exposure and development. Then, an etching process is performed corresponding to the etching window to form a dummy gate structure located on the surface of the semiconductor substrate 11.

[0038] like Figure 3 As shown, the pseudo gate structure 21 formed may include a stacked gate oxide layer 22, a functional layer 23, a pseudo gate material layer 24, a hard mask layer 25, and an oxide layer 26. According to product requirements, the number of pseudo gate structures 21 produced may be multiple. Among them, a pseudo gate structure 21 may be produced on the surface at the junction of the shallow trench isolation region 111 and the active area 112, and the pseudo gate structure 21 is simultaneously located on the surface of the active area 112 and the surface of the pit 113 of the shallow trench isolation region 111. Since the gate oxide layer 22 is silicon dioxide, it usually grows only on the silicon surface of the active area 112, so the functional layer 23 of the pseudo gate structure 21 is in contact with the surface of the pit 113.

[0039] It can be understood that the functional layer 23 may include a gate dielectric layer 231 in contact with the shallow trench isolation region and an etch stop layer 232 disposed on the gate dielectric layer 231; the pseudo gate material layer 24 is stacked on the etch stop layer 232. The gate dielectric layer 231 may be made of a high dielectric constant (High K) material to reduce leakage current and improve device electrical performance. The etch stop layer 232 may be used to protect the gate dielectric layer 231 and the active area 112 during the process. Specifically, for example, the material of the etch stop layer 232 may be TiN.

[0040] The dummy gate material layer 24 can be used as a temporary structure to occupy the position of the gate and to serve as a reference in other process steps. Specifically, for example, the dummy gate material layer 24 can be made of polysilicon (Poly) or amorphous silicon (A-Si).

[0041] S130: forming gate sidewalls on both sides of the dummy gate structure.

[0042] Specifically, Figure 4 As shown, through OSW (Oxide Spacer Wall) deposition and etching process, a first spacer 271 is formed on both sides of the dummy gate structure 21. Then, a second spacer 272 is continuously formed on the side of the first spacer 271 to form a Figure 5 The structure shown.

[0043] S140: Disposing an interlayer dielectric layer on the surface of the semiconductor substrate.

[0044] Specifically, Figure 6 As shown, an interlayer dielectric material can be first deposited on the surface of the semiconductor substrate 11, and then planarized based on a CMP process to form a Figure 7 The interlayer dielectric layer 29 is shown in FIG.

[0045] S150: removing the dummy gate material layer, and forming a gate structure corresponding to the position of the dummy gate structure.

[0046] Specifically, Figure 8 As shown, based on the DPRM process, the dummy gate material layer 24 is removed to form a trench 28 between the gate sidewalls 27 on both sides of the dummy gate structure 21. The position corresponding to the trench 28 can be filled with gate materials, such as metal gate materials, to form a gate structure.

[0047] However, during the preparation process, technicians discovered that after the dummy gate material layer 24 was removed, the functional layer 23 was missing, and the active area 112 was also severely damaged at the position where the functional layer 23 was missing.

[0048] In this regard, after testing and analysis, the technicians discovered the reasons for the missing functional layer 23 and the damage to the active area 112.

[0049] See also Fig. 9 and Fig.10 Specifically, in the above step S120, polysilicon is usually used as the pseudo gate material, and the material of the etch stop layer in the functional layer 23 is usually TiN (titanium nitride). When the etching process is performed on the corresponding etching window, since the etching rate of polysilicon is greater than that of TiN, after the etching is completed, Fig. 9As shown, both side edges of the functional layer 23 have footings 231 extending relative to the dummy gate material layer 24 , and the width of the footings 231 gradually decreases from the bottom to the top.

[0050] Due to the presence of the footings 231 on both sides of the functional layer 23, in the subsequent gate spacer process step S130, the first spacer 271 formed by OSW will be relatively thin at the position of the footings 231, especially in the case of Fig. 9 This is more obvious when the foot 231 of the functional layer 23 shown in FIG. 1 is in contact with the rising surface 114 of the pit 113. Fig.10 As shown, the first sidewall 271 is very thin at the position of the foot 231 and can hardly even cover the functional layer 23 , so that the functional layer 23 is exposed outside the first sidewall 271 , forming a weak point 232 .

[0051] Furthermore, a large amount of SPM (Sulfuric Acid-Peroxide Mixture) is used in the cleaning process of the first sidewall 271. Due to the existence of the above-mentioned weak point 232, the SPM acid easily penetrates into the functional layer 23 from the weak point 232, thereby causing the functional layer 23 to be missing. Furthermore, during the subsequent S140 DPRM process, due to the lack of protection of TiN in the functional layer 23, the used TMAH (Tetramethylammonium Hydroxide) acid will penetrate the damaged functional layer 23, thereby causing damage to the active area 112.

[0052] Therefore, it is necessary to provide a method for preparing a semiconductor structure, which can reduce the loss of functional layers and the resulting damage to active areas caused by the above-mentioned preparation process.

[0053] Please continue reading Fig. 9 and Fig.10 , and see Fig.11 . In response to the problems of missing functional layers and damaged active areas in the aforementioned embodiments, an embodiment of the present specification provides a method for preparing a semiconductor structure, which improves the preparation method in the aforementioned embodiments. The method for preparing a semiconductor structure provided in this embodiment can refer to the aforementioned embodiments, and specifically may include: S210: providing a semiconductor substrate; S220: making a dummy gate structure on the semiconductor substrate; S230: preparing a gate structure corresponding to the position of the dummy gate structure.

[0054] Among them, the improvement compared with the above-mentioned embodiment is that, in step S220, the dummy gate structure includes a functional layer in contact with the shallow trench isolation region and a dummy gate material layer stacked on the functional layer; wherein, there is a contact surface between the functional layer and the shallow trench isolation region; the contact surface does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface.

[0055] refer to Fig. 9 and Fig.10 , which is different from step S120 in the above-mentioned embodiment, in this embodiment, the size of the dummy gate structure 21 can be changed so that the contact surface between the functional layer 23 and the shallow trench isolation region 111 included in the dummy gate structure 21 formed on the semiconductor substrate 11 is not within the range of the rising surface 114 of the pit 113 of the shallow trench isolation region 111, that is, the two do not overlap; or, the rising surface 114 of the pit 113 is completely covered by the contact surface between the functional layer 23 and the shallow trench isolation region 111, that is, the rising surface 114 is part of the contact surface. In this way, the foot 231 of the functional layer 23 caused by the inconsistent etching rate during the process of manufacturing the dummy gate structure 21 will not contact the rising surface 114 of the pit 113.

[0056] In this embodiment, during the process of manufacturing a dummy gate structure on a semiconductor substrate, the contact surface between the functional layer and the shallow trench isolation area in the dummy gate structure is made not to overlap with or completely covers the rising surface of the pit. An unexpected effect is that weak points can be avoided at the bottom of the functional layer to a certain extent, thereby reducing the destruction or damage to the functional layer and the active area caused by the weak points in subsequent process steps.

[0057] In some embodiments, corresponding to the position of the dummy gate structure, the steps of preparing and forming the gate structure may specifically include: forming a first side wall on both sides of the dummy gate structure; wherein both sides of the functional layer are respectively covered by the first side wall; forming a second side wall on the side of the first side wall away from the dummy gate structure; the first side wall and the second side wall constitute a gate side wall; removing the dummy gate material layer to form a trench between the gate side walls on both sides of the dummy gate structure; and preparing and forming the gate structure corresponding to the position of the trench.

[0058] refer to Fig. 9 and Fig.10Since the footings 231 on both sides of the functional layer 23 of the dummy gate structure 21 in step S220 can avoid the rising surface 114 of the pit 113, the surface of the shallow trench isolation region 111 in contact with the footings 231 can be the descending surface 115 of the pit 113 or a flat surface outside the pit 113. In this way, after the first sidewalls 271 are formed on both sides of the dummy gate structure 21, the first sidewalls 271 will not be too thin or the functional layer 23 will not be exposed at the footings 231, that is, the weak point 232 at the footings 231 of the functional layer 23 is avoided. Both sides of the functional layer 23 are completely wrapped by the first sidewalls 271 to form protection.

[0059] In some embodiments, the junction between the pit 113 and the surface of the active area 112 forms the top of the other side of the pit 113; the pit 113 also has a descending surface 115 extending from the top of the other side to the bottom of the pit 113; the width of the contact surface between the functional layer 23 and the shallow trench isolation area 111 is smaller than the width of the descending surface 115, or larger than the width of the pit 113.

[0060] In some embodiments, when the width of the contact surface between the functional layer 23 and the shallow trench isolation region 111 is smaller than the width of the descending surface 115, or larger than the width of the pit 113, the base 231 of the functional layer 23 can avoid the rising surface 114 of the pit 113, and no weak point 232 will appear after the first side wall 271 is formed.

[0061] Specifically, the width of the contact surface between the functional layer 23 and the shallow trench isolation region 111 may be greater than 42 nm, or less than 15 nm.

[0062] In some embodiments, the dummy gate structure 21 has a first sidewall 211 in contact with the surface of the active region 112, and a second sidewall 212 in contact with the surface of the shallow trench isolation region 111. The minimum spacing between the surface of the active region 112 and the shallow trench isolation region 111 and the second sidewall 212 is smaller than the width of the descending surface 115 or larger than the width of the pit 113, so that the foot 231 of the functional layer 23 can avoid the ascending surface 114 of the pit 113, and no weak point 232 will appear after the first sidewall 271 is manufactured.

[0063] See also Fig.12 One embodiment of the present specification also provides a semiconductor layout diagram, which can be applied in the aforementioned method for preparing a semiconductor structure to prepare a corresponding semiconductor structure. Specifically, the semiconductor layout diagram can be a layout design structure diagram corresponding to the semiconductor structure.

[0064] The semiconductor layout diagram may include: a semiconductor substrate pattern; the semiconductor substrate pattern includes a preset shallow trench isolation region and a preset active region defined by the preset shallow trench isolation region; the surface of the preset shallow trench isolation region is connected to the surface of the preset active region and forms a preset boundary line; a gate structure pattern; the gate structure pattern is located on the semiconductor substrate pattern and is in contact with the preset shallow trench isolation region and the preset active region at the same time; wherein, in the preset contact surface between the gate structure pattern and the preset shallow trench isolation region, the value range of the preset spacing between the boundary on the side away from the preset boundary line and the preset boundary line satisfies: so that the contact surface in the prepared semiconductor structure does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface.

[0065] In some embodiments, as a layout design structure, each pattern or preset structure in the semiconductor layout diagram may correspond to the actual structure in the aforementioned method for preparing the semiconductor structure. Specifically, for example, the semiconductor substrate pattern corresponds to the semiconductor substrate 11, the preset shallow trench isolation region corresponds to the shallow trench isolation region 111, the preset active region corresponds to the active region 112, and the interface where the surface of the preset shallow trench isolation region and the surface of the preset active region meet forms a preset intersection line. The gate structure pattern may correspond to the pseudo gate structure 21, and similar to the actual structure, the gate structure pattern and the preset shallow trench isolation region have a preset contact surface in contact. Taking into account the deviation between the actual size and the design size in the preparation process, as well as the occurrence of pits, the preset spacing between the boundary of one side away from the preset intersection line in the gate structure pattern and the preset intersection line can be reasonably designed, so that the pseudo gate structure 21 in the actual semiconductor structure preparation process can avoid the rising surface 114 of the pit 113, so as to avoid the weak point 232 at the foot 231 position of the functional layer 23, thereby solving the problem of missing the functional layer 23 and damaging the active area 112.

[0066] Specifically, see Fig.12 , Fig.12 The figure includes a layout design structure diagram corresponding to the dummy gate structure 21 in the aforementioned embodiment, and a TEM (Transmission Electron Microscopy) slice diagram of the dummy gate structure 21 in the actual preparation process of the aforementioned embodiment. Fig.12In the figure, A, B, and C are actual sizes, which respectively represent the width of the descending surface 115 of the pit 113, the total width of the pit 113, and the minimum spacing between the surface of the active area 112 and the junction of the shallow trench isolation area 111 relative to the second sidewall 212 during the actual preparation process. C' represents the preset spacing between the boundary of the side away from the preset junction line in the gate structure pattern and the preset junction line in the layout design structure. C is the size in the actual preparation process corresponding to C'. D1 and D2 respectively represent the deviation between the actual size of the active area 112 and the designed size, and the deviation between the actual size of the dummy gate structure 21 and the designed size.

[0067] In some embodiments, Fig.12 As shown in FIG. 2 , when C>B or C<A, the dummy gate structure 21 can avoid the rising surface 114 of the pit 113 to avoid forming a weak point 232. Since C'=C+D2-D1, the safe range of C' in the layout design structure is: C'>B+D2-D1 or C' <A+D2-D1。

[0068] In some embodiments, the approximate ranges of A, B, D1, and D2 can be determined by TEM slices in the actual preparation process, as shown in Tables 1 and 2, so as to infer that in the Layout design structure, the above-mentioned preset spacing C' needs to satisfy C'>30nm or C'<5nm, so that the semiconductor structure prepared based on the Layout design structure will not have the problem of missing functional layers and damage to the active area.

[0069] Table 1: 28HPC IPQV TEM slice analysis data table

[0070]

[0071] Table 2: 28HVA TEM slice analysis data table

[0072]

[0073] In Tables 1 and 2, 28HPC IPQV and 28HVA represent different 28nm process node-related products, and BK12, BK13, BK14, BK24, and BK25 represent different partitions in the products.

[0074] See also Fig.13 An embodiment of the present specification provides a semiconductor structure 30 , including a semiconductor substrate 11 and a gate structure 31 .

[0075] The semiconductor substrate 11 can be used as a basic structure, not only for providing mechanical support, but also for affecting the electrical properties of the device, such as threshold voltage and carrier mobility, by doping ions. Specifically, the semiconductor substrate 11 can be made of silicon (Si), or can be made of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), etc., according to requirements.

[0076] In this embodiment, the semiconductor substrate 11 may include a shallow trench isolation region 111 and an active area 112 defined by the shallow trench isolation region 111; wherein a pit 113 connected to the surface of the active area 112 is formed on the surface of the shallow trench isolation region 111; the pit 113 has a rising surface 114 extending from the bottom of the pit 113 to the top of the side of the pit 113 away from the active area 112.

[0077] In this embodiment, the specific explanation of the semiconductor substrate 11 can refer to the above-mentioned embodiment, which will not be repeated here.

[0078] In this embodiment, the gate structure 31 may include a functional layer 23 in contact with the shallow trench isolation region 111 and a gate material layer stacked on the functional layer 23; wherein, there is a contact surface between the functional layer 23 and the shallow trench isolation region 111, and the contact surface does not overlap with the rising surface 114 of the pit 113, or, the rising surface 114 of the pit 113 is completely covered by the contact surface.

[0079] The gate structure 31 in this embodiment can be prepared according to the preparation method of the previous embodiment by removing the dummy gate material layer 24 and filling the gate material in the trench 28. The specific explanation of the gate structure 31 can refer to the previous embodiment and will not be repeated here.

[0080] An unexpected effect of this embodiment is that the semiconductor structure 30 provided by this embodiment has no destruction or damage to its functional layer 23 and active region 112 and has good electrical performance and reliability.

[0081] In some embodiments, the junction between the pit 113 and the surface of the active area 112 forms the top of the other side of the pit 113; the pit 113 also has a descending surface 115 extending from the top of the other side to the bottom of the pit 113; the width of the contact surface between the functional layer 23 and the shallow trench isolation area 111 is smaller than the width of the descending surface 115, or larger than the width of the pit 113.

[0082] In some embodiments, the width of the contact surface between the functional layer 23 and the shallow trench isolation region 111 is greater than 42 nm, or less than 15 nm.

[0083] In some embodiments, first sidewall spacers 271 and second sidewall spacers 272 located on the side of the first sidewall spacer 271 away from the gate structure 31 are further disposed on both sides of the gate structure 31 ; wherein both sides of the functional layer 23 are respectively covered by the first sidewall spacers 271 .

[0084] In some embodiments, the functional layer 23 includes a gate dielectric layer 231 in contact with the shallow trench isolation region and an etch stop layer 232 disposed on the gate dielectric layer 231 ; and the gate material layer is stacked on the etch stop layer 232 .

[0085] An embodiment of the present specification provides a MOS device, including the semiconductor structure in any of the foregoing embodiments, or manufactured according to the method for manufacturing the semiconductor structure in any of the foregoing embodiments.

[0086] It should be understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this specification, rather than to limit the scope of the present invention.

[0087] It can be understood that in the various embodiments in this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0088] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments of this specification are not limited to this.

[0089] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification are the same as the meanings generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of this specification are also intended to include majority forms, unless the context clearly indicates other meanings.

[0090] The above description is only a specific embodiment of the present specification, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be covered by the protection scope of this specification.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: A semiconductor substrate is provided; the semiconductor substrate comprises a shallow trench isolation region and an active region defined by the shallow trench isolation region; wherein a pit connected to the surface of the active region is formed on the surface of the shallow trench isolation region; the pit has a rising surface extending from the bottom of the pit to the top of the pit away from the active region; A dummy gate structure is fabricated on the semiconductor substrate; the dummy gate structure comprises a functional layer in contact with the shallow trench isolation region and a dummy gate material layer stacked on the functional layer; wherein a contact surface is provided between the functional layer and the shallow trench isolation region; the contact surface does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface; A first spacer is formed on both sides of the dummy gate structure; wherein both sides of the functional layer are respectively covered by the first spacer; A second sidewall spacer is formed on a side of the first sidewall spacer away from the dummy gate structure; the first sidewall spacer and the second sidewall spacer constitute a gate sidewall spacer; Removing the dummy gate material layer to form a trench between the gate sidewalls on both sides of the dummy gate structure; A gate structure is formed corresponding to the position of the trench.

2. The method according to claim 1, characterized in that The junction between the pit and the surface of the active area forms the top of the other side of the pit; the pit also has a descending surface extending from the top of the other side to the bottom of the pit; the width of the contact surface between the functional layer and the shallow trench isolation area is smaller than the width of the descending surface, or larger than the width of the pit.

3. The method according to claim 1 or 2, characterized in that The functional layer includes a gate dielectric layer in contact with the shallow trench isolation region and an etch stop layer arranged on the gate dielectric layer; the dummy gate material layer is stacked on the etch stop layer.

4. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the semiconductor manufacturing method according to any one of claims 1 to 3; the semiconductor structure comprises: A semiconductor substrate, the semiconductor substrate comprising a shallow trench isolation region and an active region defined by the shallow trench isolation region; wherein a pit connected to the surface of the active region is formed on the surface of the shallow trench isolation region; the pit has a rising surface extending from the bottom of the pit to the top of the pit away from the active region; A gate structure, the gate structure comprising a functional layer in contact with the shallow trench isolation region and a gate material layer stacked on the functional layer; wherein, there is a contact surface between the functional layer and the shallow trench isolation region, and the contact surface does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface.

5. The semiconductor structure according to claim 4, characterized in that: The junction between the pit and the surface of the active area forms the top of the other side of the pit; the pit also has a descending surface extending from the top of the other side to the bottom of the pit; the width of the contact surface between the functional layer and the shallow trench isolation area is smaller than the width of the descending surface, or larger than the width of the pit.

6. The semiconductor structure according to claim 4, characterized in that: The gate structure is also provided with a first sidewall and a second sidewall located on a side of the first sidewall away from the gate structure; wherein both sides of the functional layer are respectively covered by the first sidewall.

7. The semiconductor structure according to any one of claims 4 to 6, characterized in that: The functional layer includes a gate dielectric layer in contact with the shallow trench isolation region and an etch stop layer arranged on the gate dielectric layer; the gate material layer is stacked on the etch stop layer.

8. A semiconductor layout, characterized in that: The semiconductor layout pattern is used for preparing the semiconductor structure according to any one of claims 4 to 7 or is used in the method for preparing the semiconductor structure according to any one of claims 1 to 3; The semiconductor layout includes: A semiconductor substrate pattern; the semiconductor substrate pattern includes a preset shallow trench isolation region and a preset active region defined by the preset shallow trench isolation region; a surface of the preset shallow trench isolation region is connected to a surface of the preset active region and forms a preset boundary line; A gate structure pattern; the gate structure pattern is located on the semiconductor substrate pattern and is in contact with the preset shallow trench isolation region and the preset active region at the same time; Among them, in the preset contact surface between the gate structure pattern and the preset shallow trench isolation area, the value range of the preset spacing between the side boundary away from the preset boundary line and the preset boundary line satisfies: so that the contact surface in the prepared semiconductor structure does not overlap with the rising surface of the pit, or the rising surface of the pit is completely covered by the contact surface.

9. A MOS device, characterized in that: The MOS device comprises a semiconductor structure as claimed in any one of claims 4 to 7, or is manufactured according to a method for manufacturing a semiconductor structure as claimed in any one of claims 1 to 3.

Images