Semiconductor device

Abstract

A semiconductor device includes: an insulating base layer; a plurality of semiconductor patterns stacked on the insulating base layer and spaced apart from each other; a gate structure surrounding the plurality of semiconductor patterns; a first source / drain pattern and a second source / drain pattern disposed on the insulating base layer and connected to both side surfaces of the plurality of semiconductor patterns, respectively; a contact structure connected to the first source / drain pattern through the insulating base layer; a sidewall insulating film disposed between an upper portion of the contact structure and an upper portion of the insulating base layer and extending to a region of a portion of the gate structure below a lowermost semiconductor pattern among the plurality of semiconductor patterns; and a power transmission line disposed on a lower surface of the insulating base layer and connected to the contact structure.

Description

Technical Field

[0001] Some inventive concepts relate to semiconductor devices. Background Art

[0002] As the demand for high performance, high speed and / or multi-function of semiconductor devices has been increasing, the integration of semiconductor devices has been increasing. According to the trend of high integration of semiconductor devices, semiconductor devices having a back side power supply network (BSPDN) structure in which a power rail is provided on the back side of a wafer have been developed. In addition, in order to overcome the limitation in operating characteristics due to the size reduction of a planar metal oxide semiconductor field effect transistor (MOSFET), efforts have been made to develop a semiconductor device having a channel with a three-dimensional structure. Summary of the invention

[0003] Various example embodiments provide a semiconductor device having improved electrical characteristics and reliability.

[0004] In some example embodiments, a semiconductor device includes: an insulating base layer having an insulating pattern extending in a first direction; a plurality of semiconductor patterns stacked on the insulating pattern and spaced apart from each other in a direction perpendicular to an upper surface of the insulating base layer; a gate structure extending in a second direction intersecting the first direction and surrounding the plurality of semiconductor patterns; a first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being located on the insulating pattern and connected to two side surfaces of the plurality of semiconductor patterns in the first direction, respectively; an interlayer insulating layer covering the first source / drain pattern and the second source / drain pattern; a first contact structure connected to the first source / drain pattern through the insulating base layer; and a first sidewall insulating film located between an upper portion of the first contact structure and an upper portion of the insulating pattern and extending to cover a side surface of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns.

[0005] In some example embodiments, a semiconductor device includes: an insulating base layer; a plurality of semiconductor patterns, the plurality of semiconductor patterns are stacked on a protruding portion of the insulating base layer and spaced apart from each other in a vertical direction; a first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being connected to two side surfaces of the plurality of semiconductor patterns in a first direction, respectively; a gate structure, the gate structure extending in a second direction intersecting the first direction and surrounding the plurality of semiconductor patterns; an interlayer insulating layer, the interlayer insulating layer covering the first source / drain pattern and the second source / drain pattern; a first contact structure, the first contact structure being connected to the first source / drain pattern through the insulating base layer. A first source / drain pattern; a second contact structure, which is connected to the second source / drain pattern through the interlayer insulating layer; a first sidewall insulating film, which surrounds an upper portion of the first contact structure and extends from a side surface of the protruding portion of the insulating base layer, wherein an upper end portion of the first sidewall insulating film has a height lower than a height of a lower surface of a lowermost semiconductor pattern among the plurality of semiconductor patterns; a vertical insulating pattern, which is connected to a lower surface of the second source / drain pattern and is arranged in the insulating base layer; and a second sidewall insulating film, which surrounds an upper portion of the vertical insulating pattern and is arranged at the same height as that of the first sidewall insulating film.

[0006] In some example embodiments, a semiconductor device includes: an insulating base layer; a plurality of semiconductor patterns stacked on the insulating base layer and spaced apart from each other; a gate structure surrounding the plurality of semiconductor patterns; a first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being located on the insulating base layer and respectively connected to two side surfaces of the plurality of semiconductor patterns; a contact structure connected to the first source / drain pattern through the insulating base layer; a sidewall insulating film located between an upper portion of the contact structure and an upper portion of the insulating base layer and extending to an area of ​​a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns; and a power transmission line located on a lower surface of the insulating base layer and connected to the contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1is a top view illustrating a semiconductor device according to an example embodiment of the inventive concept;

[0009] Figure 2 It is taken along the line I-I' Figure 1 A cross-sectional view of a semiconductor device;

[0010] Figure 3A and Figure 3B are respectively taken along lines II1-II1' and II2-II2' Figure 1 A cross-sectional view of a semiconductor device;

[0011] Figure 4A and Figure 4B They are shown separately Figure 2 A partial enlarged view of parts “A” and “B” of a semiconductor device;

[0012] Figure 5A and Figure 5B are cross-sectional views illustrating semiconductor devices according to various example embodiments of the inventive concept, respectively;

[0013] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept;

[0014] 7A to 7H are cross-sectional views of each main process for illustrating some processes (eg, sidewall insulating film and source / drain pattern forming processes) of a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept;

[0015] FIG. 8A to FIG. 8C They are shown separately FIG. 7F to FIG. 7H A partial enlarged view of the local areas A1, A2 and A3;

[0016] 9A to 9H is a cross-sectional view of each main process for illustrating another partial process (eg, a contact forming process) of a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept;

[0017] Fig. 10A and Fig. 10B They are shown separately Fig.9D and Figure 9H A partial enlarged view of the local areas A4 and A5; and

[0018] FIG. 11A to FIG. 11E is a cross-sectional view of each main process to illustrate another partial process (eg, a contact forming process) of the method of fabricating a semiconductor device according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0019] Hereinafter, some example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0020] As described herein, an element "on" another element may be above or below the other element or adjacent to the other element (e.g., horizontally adjacent). An element on another element may be directly on the other element, such that the element is in direct contact with the other element. An element on another element may be indirectly on the other element, such that the element is isolated from the other element by one or more intervening spaces and / or structures and is not in direct contact with the other element.

[0021] It is to be understood that elements and / or properties thereof may be described herein as being "identical" or "equal" to other elements, and it is to be further understood that elements and / or properties thereof described herein as being "identical", "identical" or "equal" to other elements may be "identical", "identical" or "equal" or "substantially identical", "substantially identical" or "substantially equal" to other elements and / or properties. Elements and / or properties thereof that are "substantially identical", "substantially identical" or "substantially equal" to other elements and / or properties are to be understood to include elements and / or properties thereof that are identical, identical or equal to other elements and / or properties within manufacturing tolerances and / or material tolerances. Elements and / or properties thereof that are identical or substantially identical and / or identical or substantially identical to other elements and / or properties may be identical or substantially identical in structure, identical or substantially identical in function and / or identical or substantially identical in composition.

[0022] It should be understood that elements and / or properties thereof described herein as being "substantially" the same and / or identical encompass elements and / or properties thereof having relative differences equal to or less than 10% in magnitude. Furthermore, regardless of whether an element and / or property thereof is qualified as "substantially," it should be understood that these elements and / or properties thereof should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated element and / or property thereof.

[0023] Figure 1 is a top view illustrating a semiconductor device according to an example embodiment of the inventive concept, Figure 2 It is taken along the line I-I' Figure 1 A cross-sectional view of a semiconductor device, and Figure 3A and Figure 3B are respectively taken along lines II1-II1' and II2-II2' Figure 1 A cross-sectional view of a semiconductor device.

[0024] refer to Figure 1 , Figure 2 , Figure 3A and Figure 3BAccording to some example embodiments, the semiconductor device 100 includes: an insulating base layer 210; a plurality of semiconductor patterns 130 stacked on a region of the insulating base layer 210 and spaced apart from each other in a vertical direction (e.g., Z direction); a first source / drain pattern 150A and a second source / drain pattern 150B, respectively connected to two side surfaces of the plurality of semiconductor patterns 130 in a first direction (e.g., X direction); and a gate structure GS extending in a second direction (e.g., Y direction) intersecting the first direction (e.g., X direction) and surrounding the plurality of semiconductor patterns 130.

[0025] In some example embodiments, the insulating base layer 210 extends in a first direction (e.g., X direction) and has an insulating pattern 210P (e.g., a protruding insulating pattern). A plurality of semiconductor patterns 130 are stacked on a region of the insulating pattern 210P and are spaced apart from each other. The gate structure GS may extend to intersect the insulating pattern 210P on the insulating base layer 210. The first source / drain pattern 150A and the second source / drain pattern 150B may be disposed on regions of the insulating pattern 210P located on both sides of the gate structure GS (e.g., reference numerals 24 and 25). Figure 2 ).

[0026] The insulating base layer 210 may be a substrate including a semiconductor material removed in a series of manufacturing processes for a semiconductor device (eg, referring to Fig. 9C '101') and then by additional processes (e.g., reference Fig.9D and Fig.9E ) or may be a layer formed by oxidizing the substrate. The insulating base layer 210 includes an insulating material such as an oxide or a nitride. For example, the insulating base layer 210 may include a spin-on hard mask (SOH), a flowable oxide (FOX), a toner silazane (TOSZ), an undoped quartz glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a plasma-enhanced tetraethyl orthosilicate (PETEOS), a fluorosilicate glass (FSG), a high-density plasma (HDP) oxide, a plasma-enhanced oxide (PEOX), a flowable CVD (FCVD) oxide, or a combination thereof, but example embodiments are not limited thereto. The insulating base layer 210 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process. In some example embodiments, the insulating base layer 210 may include a first insulating material layer 210a and a second insulating material layer 210b. The first insulating material layer 210a and the second insulating material layer 210b may include the same material, but may be manufactured by different processes (eg, referring to Fig.9E and Figure 9GIn some example embodiments, the insulating base layer 210 may have a single-layer structure (eg, referring to FIG. 11A to FIG. 11E ).

[0027] The insulating pattern 210P of the insulating base layer 210 may be understood as being connected to a fin-type active pattern (eg, Figure 7B The insulating pattern 210P may be formed in a process of replacing the aforementioned semiconductor substrate with the insulating base layer 210.

[0028] refer to Figure 3A and Figure 3B The device isolation layer 110 may define an insulating pattern 210P on the insulating base layer 210. The device isolation layer 110 may be disposed on the insulating base layer 210 to cover both side surfaces of the insulating pattern 210P. An upper portion of the insulating pattern 210P may be exposed from an upper surface of the device isolation layer 110.

[0029] As described above, a plurality of semiconductor patterns 130 may be stacked on the insulating pattern 210P and spaced apart from each other to function as a channel layer. Figure 2 As illustrated, both side surfaces of the plurality of semiconductor patterns 130 in a first direction (eg, X direction) may be connected to the first and second source / drain patterns 150 located on the insulating pattern 210P, respectively.

[0030] The widths of the plurality of semiconductor patterns 130 may be equal to or similar to the width of the insulating pattern 210P in the second direction (e.g., the Y direction). In some example embodiments, the widths of the plurality of semiconductor patterns 130 may be slightly different. For example, the widths of the highest semiconductor pattern and the lowest semiconductor pattern may be greater than the width of the semiconductor pattern located between the highest semiconductor pattern and the lowest semiconductor pattern.

[0031] The plurality of semiconductor patterns 130 may include a semiconductor material that may provide a channel region for a transistor. For example, the plurality of semiconductor patterns 130 may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In some example embodiments, the plurality of semiconductor patterns 130 may be a silicon semiconductor. In some example embodiments, the plurality of semiconductor patterns 130 are illustrated as four semiconductor patterns, but the number and shape may vary.

[0032] like Figure 2 and Figure 3AAs illustrated, the gate structure GS adopted in some example embodiments may include a gate electrode 145, a gate insulating film 142, a gate spacer 141 and a gate covering layer 147, wherein the gate electrode 145 extends in a second direction (e.g., the Y direction) and surrounds a plurality of semiconductor patterns 130, the gate insulating film 142 is disposed between the gate electrode 145 and the plurality of semiconductor patterns 130, the gate spacer 141 is disposed on both side surfaces of a portion of the gate electrode 145 located on the uppermost semiconductor pattern, and the gate covering layer 147 is disposed on the gate electrode 145 between the gate spacers 141.

[0033] The gate electrode 145 may include a conductive material. For example, the gate electrode 145 may include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC, but example embodiments are not limited thereto. In some example embodiments, the gate electrode 145 may include a semiconductor material such as doped polysilicon. At least one of the gate electrodes 145 may include a multilayer structure formed of different materials.

[0034] The gate insulating film 142 may include a dielectric material. For example, the gate insulating film 142 may include an oxide, a nitride, or a high-k material. The high-k material may refer to a dielectric material having a dielectric constant greater than that of silicon oxide (SiO 2 ) dielectric material with a high dielectric constant, and the high-k material may be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ), but example embodiments are not limited thereto. In some example embodiments, the gate insulating film 142 may include two or more different dielectric films.

[0035] The gate spacer 141 may include an insulating material. For example, the gate spacer 141 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some example embodiments, the gate spacer 141 may include a multilayer structure formed of different materials. The gate capping layer 147 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide.

[0036] According to some example embodiments, the gate structure GS may include an internal spacer 149. The internal spacer 149 may be disposed between the plurality of semiconductor patterns 130 and on both sides of the gate electrode portion 145S located between the bottommost semiconductor pattern 130U and the insulating pattern 210P. The gate electrode portion 145S may be surrounded by the gate insulating portion 142S in a first direction (e.g., X direction). The gate electrode portion 145S and the gate insulating portion 142S may be spaced apart from the first source / drain pattern 150A and the second source / drain pattern 150B by the internal spacer 149. The internal spacer 149 may have a convex side surface facing the gate electrode portion 145S, but example embodiments are not limited thereto. For example, the internal spacer 149 may include a low dielectric material such as an oxide, a nitride, and an oxynitride.

[0037] like Figure 2 As shown, the first source / drain pattern 150A and the second source / drain pattern 150B may be included in local regions of the insulating pattern 210P located on both sides of the gate structure GS. The region of the insulating pattern 210P in which the first source / drain pattern 150A and the second source / drain pattern 150B are formed may be a slightly recessed region. As described above, the first source / drain pattern 150A and the second source / drain pattern 150B may be connected to both side surfaces of the plurality of semiconductor patterns 130 as channel regions, respectively.

[0038] refer to Figure 2 and Figure 3A The first and second source / drain patterns 150A and 150B employed in some example embodiments include a first epitaxial layer 150a and a second epitaxial layer 150b disposed on the first epitaxial layer 150a. In some example embodiments, the first epitaxial layer 150a may directly contact side surfaces of the plurality of semiconductor patterns 130.

[0039] In some example embodiments, the first epitaxial layer 150a and the second epitaxial layer 150b may include different materials. For example, in the case of a PMOSFET, the first epitaxial layer 150a and the second epitaxial layer 150b may include SiGe having different Ge components (e.g., the second epitaxial layer 150b includes a higher Ge content), or the first epitaxial layer 150a and the second epitaxial layer 150b may include Si and SiGe, respectively. However, in the case of an NMOSFET, both the first epitaxial layer 150a and the second epitaxial layer 150b may include Si. In some example embodiments, the first epitaxial layer 150a and the second epitaxial layer 150b may include different types of impurities or the same impurities at different concentrations.

[0040] The semiconductor device 100 according to some example embodiments may include a first interlayer insulating layer 161 disposed on the device isolation layer 110 to cover the first source / drain pattern 150A and the second source / drain pattern 150B, and a second interlayer insulating layer 162 covering the gate structure GS on the first interlayer insulating layer 161. For example, the first interlayer insulating layer 161 and the second interlayer insulating layer 162 may include FOX, TOSZ, USG, BSG, PSG, BPSG, PETEOS, FSG, HDP oxide, PEOX, FCVD oxide, or a combination thereof, but example embodiments are not limited thereto. The first interlayer insulating layer 161 and the second interlayer insulating layer 162 may each be formed using chemical vapor deposition, a flowable CVD process, or a spin coating process.

[0041] refer to Figure 2 According to some example embodiments, the semiconductor device 100 may include a first contact structure 250 connected to the first source / drain pattern 150A and a second contact structure 180 connected to the second source / drain pattern 150B.

[0042] The first contact structure 250 may be connected to the first source / drain pattern 150A through the portion of the insulating base layer 210 immediately below the first source / drain pattern 150A. The first contact structure may extend inward from the lower surface of the first source / drain pattern 150A. Figure 2 and Figure 4A As illustrated, an upper portion 250P of the first contact structure 250 may be in contact with the second epitaxial layer 150 b .

[0043] In some example embodiments, the first contact structure 250 includes a first portion 250a penetrating the first insulating material layer 210a and a second portion 250b penetrating the second insulating material layer 210b. The first portion 250a of the first contact structure 250 may be formed on a vertical sacrificial pattern (eg, Figure 7G240) previously ensured space, the vertical sacrificial pattern is a contact alignment element (eg, reference Figure 9H ). The second portion 250b of the first contact structure 250 may be formed by a hole structure formed by the lower surface of the second insulating material layer 210b. Therefore, in some example embodiments, the first contact structure 250 may have a discontinuous side surface. The side surface of the first portion 250a may be discontinuously connected to the side surface of the second portion 250b. Here, "discontinuously connected" may mean that the side surfaces of the first portion 250a and the second portion 250b are connected to each other, but the profile of the side surface of the first portion 250a and the profile of the side surface of the second portion 250b are different. For example, this may refer to Figure 2 and Figure 3B As shown, the side surface of the first portion 250a and the side surface of the second portion 250b have different slopes or the slopes are different at points where the side surfaces are discontinuously connected.

[0044] In some example embodiments, the first sidewall insulating film 170A may be disposed between an upper portion of the first contact structure 150A and an upper portion of the insulating base layer 210 (eg, the insulating pattern 210P). The first sidewall insulating film 170A may surround an upper portion of the first contact structure 150A.

[0045] Figure 4A yes Figure 2 A partial enlarged view of "A" of the semiconductor device.

[0046] refer to Figure 4A as well as Figure 2 The first sidewall insulating film 170A may be disposed between the upper portion of the first contact structure 250 and the upper portion of the insulating base layer 210 (eg, the insulating pattern 210P), thereby effectively preventing (or reducing) the semiconductor substrate (eg, the reference pattern 210P) from being removed. Fig.9D and Fig. 10A ) when the first source / drain pattern 150A is lost. To this end, the first sidewall insulating film 170A may cover the upper portion of the insulating pattern 210P by a predetermined width d1. For example, the width d1 covered by the first sidewall insulating film 170 may be in the range of 0.5 nm to 10 nm.

[0047] The first sidewall insulating film 170A employed in some example embodiments may extend to cover the side surfaces of the portions 142S and 145S of the gate structure located below the lowermost semiconductor pattern 130U among the plurality of semiconductor patterns 130. This first sidewall insulating film 170A may prevent (or reduce) the occurrence of a gate electrode when removing the dummy gate structure DG (e.g., referring to Fig. 9A) to the vertical sacrificial pattern 240. To this end, the first sidewall insulating film 170A may cover a portion of the gate structure having a predetermined width d2. For example, the width d2 covered by the first sidewall insulating film 170A may be in the range of 0.5 nm to 5 nm.

[0048] An upper end portion of the first sidewall insulating film 170A may be located at a height lower than that of a lower surface of a lowermost semiconductor pattern 130U among the plurality of semiconductor patterns 130. The first sidewall insulating film 170A may not interfere with contact between the first source / drain pattern 150A and the lowermost semiconductor pattern 130U. For such a blocking effect, for example, a thickness t of the first sidewall insulating film 170A may be in a range of 0.5 nm to 3 nm.

[0049] refer to Figure 4A , the upper surface of the first contact structure 250 may be located at a height higher than the height of the upper end portion of the first sidewall insulating film 170A. As described above, the upper portion 250P of the first contact structure 250 may be in contact with the second epitaxial layer 150b. The portion S1 of the first contact structure 250 adjacent to the upper end portion of the first sidewall insulating film (or the edge region of the upper surface of the first contact structure 250) may have a concave portion lower than the upper end portion of the first sidewall insulating film 170A. Therefore, the upper surface of the first contact structure 250 may overlap with the lowermost semiconductor pattern 130U in the horizontal direction, or may be located at a height higher than the height of the lowermost semiconductor pattern 130U.

[0050] The insulating base layer 210 (e.g., the first insulating material layer 210a) immediately below the second source / drain pattern 150B connected to the second contact structure 180 may include a vertical insulating pattern IP. The vertical insulating pattern IP may be connected to the lower surface of the second source / drain pattern 150B. The vertical insulating pattern IP may be formed on the vertical sacrificial pattern (e.g., Figure 7G 240) ensures that the vertical sacrificial pattern is in contact with the alignment element (e.g., reference FIG. 9E to FIG. 9G In some example embodiments, the second sidewall insulating film 170B may surround an upper portion of the vertical insulating pattern IP.

[0051] Figure 4B yes Figure 2 A partial enlarged view of "B" of the semiconductor device.

[0052] refer to Figure 4B as well as Figure 2, similar to the first sidewall insulating film 170A, the second sidewall insulating film 170B may be disposed between the upper portion of the vertical insulating pattern IP and the insulating base layer 210 (e.g., the insulating pattern 210P). Due to this arrangement, similar to the first sidewall insulating film 170A, the second sidewall insulating film 170B may effectively prevent (or reduce) the occurrence of a problem in removing the semiconductor substrate (e.g., referring to FIG. 1 ). Fig.9D and Fig. 10A ) is used to reduce the loss of the second source / drain pattern 150B. To this end, the second sidewall insulating film 170B may cover the upper portion of the insulating pattern 210P by a predetermined width d1.

[0053] Similar to the first sidewall insulating film 170A, the second sidewall insulating film 170B employed in some example embodiments may extend to cover the side surfaces of the portions 142S and 145S of the gate structure located below the lowermost semiconductor pattern 130U among the plurality of semiconductor patterns 130. With this arrangement, the second sidewall insulating film 170B may prevent (or reduce) the occurrence of a gate structure DG (e.g., referring to FIG. 1 ) when removing the dummy gate structure DG. Fig. 9A ) to the vertical sacrificial pattern 240. To this end, the second sidewall insulating film 170B may cover a portion of the gate structure by a predetermined width d2. The second sidewall insulating film 170B may have a thickness corresponding to the thickness t of the first sidewall insulating film 170A.

[0054] In some example embodiments, the upper surface IP_T of the vertical insulation pattern IP is located at a height lower than that of the upper surface of the first contact structure 250 (eg, refer to FIG. 2 ). Figure 2 ), but may be located at a height higher than that of the upper end portion of the second sidewall insulating film 170B. The edge region S2 of the upper surface IP_T of the vertical insulating pattern IP may have a portion lower than the upper end portion of the second sidewall insulating film 170B.

[0055] The vertical insulating pattern IP employed in some example embodiments may be a local region of the second insulating material layer 210b. The second insulating material layer 210b may include the same material as the first insulating material layer 210a. In some example embodiments, the vertical insulating pattern IP may include a material different from that of the insulating base layer 210. For example, the vertical insulating pattern IP may be embedded in the insulating base layer 210 (e.g., refer to Fig.11E ).

[0056] The first contact structure 250 and the second contact structure 180 may each include a contact plug and a barrier layer surrounding the contact plug. For example, the contact plug may include Cu, Co, Mo, Ru, W, or an alloy thereof, but example embodiments are not limited thereto. For example, the barrier layer may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof, but example embodiments are not limited thereto.

[0057] The semiconductor device 100 according to some example embodiments has a double-sided interconnect structure including a first interconnect structure disposed on an upper surface of the semiconductor device 100 and a second interconnect structure disposed on a lower surface of the semiconductor device 100 .

[0058] The first interconnect structure may include a first interconnect insulating layer 191 and an upper interconnect line M1 disposed in the first interconnect insulating layer 191. Similarly, the second interconnect structure may include a second interconnect insulating layer 192 and a lower interconnect line M2 disposed in the second interconnect insulating layer 192. For example, the first interconnect insulating layer 191 and the second interconnect insulating layer 192 may include silicon oxide, silicon oxynitride, SiOC, SiCOH, or a combination thereof. For example, the upper interconnect line M1 and the lower interconnect line M2 may include copper or a copper-containing alloy. The lower interconnect line M2 may be provided as a power line for power transmission, and may supply power for device operation to the first source / drain pattern 150A through the first contact structure 250.

[0059] In some example embodiments, a sidewall insulating film may be introduced into an upper portion of the first contact structure and / or the vertical insulating pattern to prevent (or reduce) damage to the contact alignment portion when removing the dummy gate structure and / or loss of the source / drain pattern when removing the substrate. This sidewall insulating film and its peripheral components may be variously changed.

[0060] Figure 5A and Figure 5B are cross-sectional views illustrating semiconductor devices according to various example embodiments of the inventive concepts, respectively.

[0061] refer to Figure 5A The semiconductor device 100A according to some example embodiments may be understood as being similar to Figures 1 to 4B The semiconductor device 100 is shown. In addition, unless otherwise stated, reference may be made to Figures 1 to 4B The description of the same or similar components of the illustrated semiconductor device 100 is provided to understand the components of some example embodiments.

[0062] The upper surface IP_T' of the vertical insulating pattern IP' employed in some example embodiments may be lower than the upper end portion of the second sidewall insulating film 170B'. In general, the vertical sacrificial pattern 240 may have an upper surface that protrudes crystallographically during the overgrowth process (eg, referring to Figure 7F and Fig. 8A ). As a result, similar to the shape of the vertical sacrificial pattern 240, the upper surface of the vertical insulating pattern may also protrude. In some example embodiments, before removing the exposed portion of the blocking insulating layer 170L (eg, referring to Figure 7G ), an etching process may be additionally applied to remove or reduce the protruding portion of the vertical sacrificial pattern 240. As a result, Figure 5A As illustrated, the height of the upper surface IP_T' of the vertical insulation pattern IP' may be lower than the upper end of the second sidewall insulation film 170B'. For example, the height of a point corresponding to the center of the upper surface IP_T' of the vertical insulation pattern IP' in the first direction (e.g., the X direction) may be lower than the uppermost end of the second sidewall insulation film 170B'. In some example embodiments, the vertical insulation pattern IP' may have a concave upper surface IP_T'. For example, the lower surface of the second source / drain pattern 150B may have a convex shape toward the second interconnect structure.

[0063] The width d1′ of the upper portion of the insulating pattern 210P covered by the second sidewall insulating film 170B′ may be increased. The width d1′ may be varied by adjusting the first recess RS1 (eg, referring to Figure 7C ) depth. The width d2' of the portion of the gate structure covered by the second sidewall insulating film 170B' can also be adjusted. This change in width d2' can be achieved by adjusting the vertical sacrificial pattern 240 (for example, reference Figure 7F )’s overgrowth height.

[0064] refer to Figure 5B According to some example embodiments, the semiconductor device 100B may be understood as being similar to Figures 1 to 4B The semiconductor device 100 is shown. In addition, unless otherwise stated, reference may be made to Figures 1 to 4B The description of the same or similar components of the illustrated semiconductor device 100 is provided to understand the components of some example embodiments.

[0065] Similar to the previous example embodiments (e.g., reference Figure 4B), the height of the upper surface IP_T" of the vertical insulation pattern IP" is higher than the height of the upper end portion of the second sidewall insulation film 170B, and the edge region S of the upper surface IP_T" of the vertical insulation pattern IP" may have an area lower than the upper surface. However, the edge region S may have a concave area that is relatively deeper than the concave area of ​​the previous example embodiment. In addition, the upper end portion 170T of the second sidewall insulation film has an area that decreases upward. This profile may occur during the selective removal process of the blocking insulation film.

[0066] Figure 6 are cross-sectional views illustrating semiconductor devices according to some example embodiments of the inventive concepts.

[0067] refer to Figure 6 According to some example embodiments, the semiconductor device 100C may be understood to be similar to Figures 1 to 4B The semiconductor device 100 is shown. In addition, unless otherwise stated, reference may be made to Figures 1 to 4B The description of the same or similar components of the illustrated semiconductor device 100 is provided to understand the components of some example embodiments.

[0068] Compared with the previous example embodiments (e.g., Figure 3B ), the first contact structure 250' employed in some example embodiments may have a width W extending in the second direction (eg, the Y direction). The width of the first contact structure 250' in the second direction may correspond to the width of the insulating pattern (eg, Figure 3B In this way, by extending the width W of the first contact structure 250', the contact area with the first source / drain pattern 150A can be increased. As a result, the contact resistance between the first contact structure 250' and the first source / drain pattern 150A can be reduced.

[0069] like Figure 6 As illustrated, both side surfaces of the first contact structure 250' may partially contact the device isolation layer 110. For example, the first sidewall insulating film 170A' has a portion between the first contact structure 250' and an upper portion of the device isolation layer 110. The first sidewall insulating film 170A' may extend to a lower end portion of the first source / drain pattern 150A.

[0070] 7A to 7H are cross-sectional views illustrating main processes of some processes (eg, sidewall insulating film and source / drain pattern forming processes) of a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept, and FIG. 8A to FIG. 8C It's a picture. FIG. 7F to FIG. 7HPartially enlarged views of some areas A1, A2 and A3 in FIG.

[0071] refer to Fig. 7A , sacrificial layers 120L and semiconductor layers 130L may be alternately stacked on the substrate 101 .

[0072] The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, or a silicon on insulator (SOI) layer, but example embodiments are not limited thereto.

[0073] The semiconductor stack SL may be formed by alternately stacking sacrificial layers 120L and semiconductor layers 130L on a substrate. The sacrificial layers 120L may have a composition different from that of the semiconductor layers 130L to have selectivity to the semiconductor layers 130L. In some example embodiments, the sacrificial layers 120L and the semiconductor layers 130L may be implemented by making the germanium composition ratio different (e.g., 0% to 60%). For example, the semiconductor layer 130L provided as a channel region may include silicon. The sacrificial layer 120L may include silicon germanium having a relatively high germanium concentration (e.g., 15% or more).

[0074] Next, refer to Figure 7B , the semiconductor stack SL is patterned into a plurality of fin structures FS extending in a first direction (eg, X direction), and a plurality of dummy gate structures DG extending in a second direction (eg, Y direction) are formed.

[0075] In the process of forming the fin structure FS, the substrate 101 and the sacrificial layer 120L and the semiconductor layer 130L may be partially removed to form the fin type active pattern 105. Subsequently, a device isolation layer 110 (eg, reference numeral 110) is formed in the removed region. Figure 1 , Figure 3A and Figure 3B ).

[0076] Thereafter, a dummy gate structure DG and a gate spacer 141 extending in a second direction (eg, Y direction) across the fin structure FS may be formed. The dummy gate structure DG defines a formation region of the gate structure GS. The dummy gate structure DG may be arranged at a constant pitch along a first direction (eg, X direction).

[0077] The dummy gate structure DG may include a sacrificial gate layer 245 and a mask pattern 247 stacked sequentially. The sacrificial gate layer 245 may be patterned using the mask pattern 247. For example, the sacrificial gate layer 245 may include polysilicon. The sacrificial gate layer 245 may include a plurality of layers. The mask pattern 247 may include silicon oxide and / or silicon nitride. The gate spacer 141 may be formed on both sidewalls of the dummy gate structure DG. As described above, the gate spacer 141 may be formed of a low-k material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0078] Afterwards, refer to Figure 7C , the fin structure FS region exposed from the dummy gate structure DG may be removed to form a first recess RS1 .

[0079] Using the dummy gate structure DG and the gate spacer 141 as a mask, the exposed region of the fin structure FS may be removed to form a first recess RS1. In this process, the semiconductor pattern 130 may have a channel length in a first direction (e.g., X direction). The depth of the first recess RS1 may be adjusted so that at least a portion of the fin active pattern 105 is removed. The exposed sidewall region of the fin active pattern 105 may be provided to be covered by a sidewall insulating film (e.g., Fig. 7A The substrate area covered by 170).

[0080] Afterwards, refer to Fig.7D , the blocking insulating layer 170L may be conformally formed.

[0081] The blocking insulating layer 170L may be conformally formed on the surface exposed by the dummy gate structure DG and the first recess RS1. For example, the blocking insulating layer 170L may be formed not only on the surface of the dummy gate structure DG, but also on the exposed surface of the first recess RS1 between the dummy gate structures DG. The blocking insulating layer 170L may include a dielectric material that inhibits epitaxial growth. For example, the blocking insulating layer 170L may include silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN). The blocking insulating layer 170L may also be formed on the exposed sidewalls of the fin structure FS, for example, on the side surfaces of the sacrificial pattern 120 and the semiconductor pattern 130, to prevent (or reduce) unwanted epitaxial growth in subsequent processes.

[0082] Afterwards, refer to Fig. 7E , portions of the blocking insulating layer 170L located on the bottom surface of the first recess RS1 are removed, and a process of forming the second recess RS2 is performed.

[0083] The selective removal process of the blocking insulating layer 170L' to expose the bottom surface of the first recess RS1 can be performed using an anisotropic etching process such as dry etching. For example, by the anisotropic etching process, not only the portions of the blocking insulating layer 170L located on the bottom surface of the first recess RS1 can be removed, but also the portions located on the upper surface of the dummy gate structure DG can be removed. As a result, the blocking insulating layer 260 can be left on the exposed sidewall portions of the dummy gate structure DG. The blocking insulating layer 170L' can be left to cover the side surfaces of the sacrificial pattern 120 and the semiconductor pattern 130.

[0084] The second recess RS2 is formed by applying an additional etching process to the open bottom surface of the first recess RS1. The second recess RS2 may be formed to have a greater depth than the depth of the fin-type active pattern. These second recesses RS2 may provide space for contact alignment, for example, for forming a vertical sacrificial pattern (e.g., Figure 7F 240) space in the.

[0085] Afterwards, refer to Figure 7F , a vertical sacrificial pattern 240 may be formed in the second recess RS2.

[0086] The lower surface of the vertical sacrificial pattern 240 may be defined by the depth of the second recess RS2. The height of the lower surface of the vertical sacrificial pattern 240 may be lower than the height of the lower surface of the fin-type active pattern 105 (e.g., the lower surface of the device isolation layer 110). The vertical sacrificial pattern 240 may include a material that is selective to the material of the substrate 101. For example, the substrate 101 may be silicon, and the vertical sacrificial pattern 240 may be silicon germanium (SiGe). Similar to the sacrificial pattern 120, the vertical sacrificial pattern 240 may have a relatively high germanium composition ratio.

[0087] The vertical sacrificial pattern 240 grows from the exposed surface of the second recess RS2. In some example embodiments, the vertical sacrificial pattern 240 may be overgrown and formed to cover a partial region of the remaining blocking insulating layer 170L'.

[0088] refer to Fig. 8A , the vertical sacrificial pattern 240 may be formed to have a height higher than the height of the lower surface of at least the lowermost sacrificial pattern 120U. The upper portion 240P of the vertical sacrificial pattern 240 may have a protruding structure defined by a crystal plane. The space around the protruding upper portion 240P of the vertical sacrificial pattern 240 may gradually narrow in a downward direction.

[0089] Next, refer to Figure 7G , the exposed blocking insulating layer 170 may be removed to form a sidewall insulating film 170 .

[0090] As described above, even if there is a space around the protruding upper portion 240P of the vertical sacrificial pattern 240, the space gradually narrows in the downward direction so that a portion of the blocking insulating layer located in the space may remain in a subsequent removal process of the blocking insulating layer 170L'. Figure 8B As shown, a portion of the blocking insulating layer may remain to cover at least a portion of the lowermost sacrificial pattern 120U. Therefore, the sidewall insulating film 170 may be disposed between the vertical sacrificial pattern 240 and the substrate 101 (eg, the fin type active pattern 105), and may extend to a partial region of the lowermost sacrificial pattern 120U.

[0091] The portion extending from the sidewall insulating film 170 to the lowermost sacrificial pattern 120U can prevent (or reduce) the occurrence of a problem when removing the dummy gate structure DG (eg, referring to Fig. 9A ) during the process of removing the vertical sacrificial pattern 240 formed of a material similar to that of the sacrificial pattern 120. In addition, the portion of the sidewall insulating film 170 located on the side surface of the substrate 101 can prevent (or reduce) the damage of the vertical sacrificial pattern 240 formed of a material similar to that of the sacrificial pattern 120 during the process of removing the substrate 101 (refer to Fig.9D ) process, the loss of the source / drain patterns 150A and 150B.

[0092] Afterwards, refer to Figure 7H , an epitaxial growth process may be performed with respect to the first source / drain pattern 150A and the second source / drain pattern 150B.

[0093] The first source / drain pattern 150A and the second source / drain pattern 150B are formed by growing an epitaxial layer on the side surfaces of the sacrificial pattern 120 and the semiconductor pattern 130 exposed by the first recess RS1 on the vertical sacrificial pattern 240. The first source / drain pattern 150A and the second source / drain pattern 150B may include impurities by in-situ doping. Within the first recess RS1, the first source / drain pattern 150A and the second source / drain pattern 150B may contact the sacrificial pattern 120 and the semiconductor pattern 130. The vertical sacrificial pattern 240 may be connected to the lower surfaces of the first source / drain pattern 150A and the second source / drain pattern 150B, respectively.

[0094] refer to Figure 8C , the lower surfaces of the first source / drain pattern and the second source / drain pattern may have a protruding portion 150S along the space around the upper portion 240P of the vertical sacrificial pattern 240. In some example embodiments, a portion of the space V of the upper portion 240P of the vertical sacrificial pattern 240 may remain even after the epitaxial growth. Some of these vertical sacrificial patterns 240 may be used as an element providing a space for forming a backside contact structure.

[0095] 9A to 9H are cross-sectional views illustrating each main process of another partial process (eg, a contact forming process) of the method of fabricating a semiconductor device according to some example embodiments of the inventive concepts.

[0096] refer to Fig. 9A , a first interlayer insulating layer 161 may be formed, and the dummy gate structure DS and the sacrificial pattern 120 may be removed.

[0097] The first interlayer insulating layer 161 may be formed to cover the dummy gate structure DG and the first and second source / drain patterns 150A and 150B, and then a planarization process may be performed thereon. Through the planarization process, the mask pattern 247 may be removed and the sacrificial gate layer 245 and the sacrificial pattern 120 may be selectively removed to form a gate space DH and a gap region OP. The gate space DH and the gap region OP may be provided as a space for forming a gate structure GS surrounding the semiconductor pattern 130.

[0098] In this process, since the vertical sacrificial pattern 240 includes a material similar to that of the sacrificial pattern 120 (e.g., SiGe), damage to the vertical sacrificial pattern 240 can be prevented (or reduced) by the previously prepared sidewall insulating film 170 during the process of removing the sacrificial pattern 120, especially even after the lowermost sacrificial pattern 120U is removed.

[0099] Then, refer to Fig. 9B , the gate space DH and the gap area OP form a gate structure GS surrounding the semiconductor pattern 130 .

[0100] The gate structure GS may be formed by sequentially forming a gate insulating film 142 and a gate electrode 145. In some example embodiments, before forming the gate insulating film 142 and the gate electrode 145, an inner spacer 149 may be formed on the epitaxial surface exposed to the gap region OP. After forming the inner spacer 149, the gate insulating film 142 may be conformally formed on the surface of the gate space DH and the gap region OP. After forming the gate insulating film 142, the remaining space may be filled with the gate electrode 145. After etching back the gate electrode 145 in the gate region DH, a gate capping layer 147 may be formed in the removed region of the gate electrode.

[0101] Afterwards, refer to Fig. 9C , a second contact structure 180 connected to the second source / drain pattern 150B is formed, and a first interconnection structure connected to the second contact structure 180 is formed.

[0102] After forming the second interlayer insulating layer 162, a contact hole connected to the second source / drain pattern 150A is formed through the first interlayer insulating layer 161 and the second interlayer insulating layer 162, and a second contact structure 180 may be formed by filling the contact hole with a conductive material. A lower surface of the contact hole may extend into the second source / drain pattern 150A.

[0103] Then, refer to Fig.9D , the substrate 101 can be selectively removed.

[0104] Prior to the substrate 101 removal process, a process of polishing the substrate 101 to a specific thickness may be first performed. For example, the substrate 101 may be removed and thinned by a grinding, lapping, or polishing process. Subsequently, the remaining substrate region may be removed by a wet etching and / or oxidation process. During the removal of the substrate 101, the etchant may affect the first source / drain pattern 150A and the second source / drain pattern 150B (e.g., the upper surface of the fin-type active pattern 105) on the substrate 101. However, in some example embodiments, such an etchant may be used as Fig. 10A As shown, the sidewall insulating film 170 is blocked. In this way, the sidewall insulating film 170 can prevent (or reduce) loss of the first source / drain pattern 150A and the second source / drain pattern 150B even during removal of the substrate 101.

[0105] Next, refer to Fig.9E , a first insulating material layer 210a is formed in the region where the substrate 101 is removed.

[0106] The first insulating material layer 210a may be formed to cover the vertical sacrificial pattern 240 in the region where the substrate 101 is removed. The first insulating material layer 210a may have an insulating pattern 210P defined by a space located in the fin type active pattern 105. The insulating pattern 210P may have a structure extending in a first direction (eg, X direction) (eg, referring to Figure 1 ).

[0107] Then, refer to Fig.9F After the first insulating material layer 210a is polished to expose the vertical sacrificial patterns 240, some of the vertical sacrificial patterns 240 are selectively removed to form vertical holes OH. In this process, except for the vertical sacrificial patterns 240 on which the backside contacts (e.g., the first contact structures 250) are to be formed, the other vertical sacrificial patterns 240 are selectively removed. Such selective removal can be performed using a photomask (PM).

[0108] Afterwards, refer to Figure 9G, a second insulating material layer 210b is formed on the first insulating material layer 210a. The second insulating material layer 210b may fill the vertical hole OH to provide a vertical insulating pattern IP connected to the second source / drain pattern 150B. In some example embodiments, the second insulating material layer 210b may include the same material as that of the first insulating material layer 210a. Even if the first insulating material layer 210a and the second insulating material layer 210b include the same material, they are formed by different processes so that the interface between them can be visually distinguished. In some example embodiments, the vertical insulating pattern IP may be formed to fill the vertical hole OH with the sidewall insulating film 170 (reference Figure 4B )'s upper end adjacent to the space (for example, reference Fig. 10A in the text).

[0109] Then, refer to Figure 9H , a first contact structure 250 connected to the second source / drain pattern 150A may be formed.

[0110] After forming an opening connected to the vertical sacrificial pattern 240 in the second insulating material layer 210b, the vertical sacrificial pattern 240 may be removed, and a first contact structure 250 may be formed in the opening and in a space where the vertical sacrificial pattern 240 is removed. Fig. 10B As shown, the first contact structure 250 may have an upper portion 250P that is further extended to have a sufficient contact area with the first source / drain pattern 150A. In addition, the first contact structure 250 may have a filling and sidewall insulating film 170 (refer to Figure 4A )'s upper end adjacent to the space (for example, Fig. 10A The "v" part in the figure is 250v.

[0111] The manufacturing process according to the inventive concept may be changed into various forms. FIG. 11A to FIG. 11E are cross-sectional views illustrating each main process of another partial process (eg, a contact forming process) of the method of fabricating a semiconductor device according to some example embodiments of the inventive concepts.

[0112] First, refer to Fig.11A , as a follow-up Fig. 9C In the process after the process of , the substrate 101 may be thinned to expose the lower surface of the vertical sacrificial pattern 240. Next, referring to Fig. 11B , the vertical sacrificial pattern 240 is removed from the exposed lower surface of the vertical sacrificial pattern 240 to form the vertical holes OH1 and OH2 .

[0113] Afterwards, refer to Fig. 11C , vertical insulation patterns IP may be formed in the vertical holes OH1 and OH2 , respectively.

[0114] The vertical insulating pattern IP may be formed by forming an insulating material layer to fill the vertical holes OH1 and OH2 and then performing a planarization process to remove a portion of the insulating material layer from the lower surface of the substrate 101. The vertical insulating pattern IP may contact the lower surfaces of the first source / drain pattern 150A and the second source / drain pattern 150B, respectively. The vertical insulating pattern IP may include an insulating material that can be easily removed by a wet etching process. For example, the vertical insulating pattern IP may include a material such as aluminum oxide (AlO).

[0115] Then, refer to Fig.11D , the substrate 101 is selectively removed. The substrate 101 may be removed by a wet etching and / or oxidation process. Fig.9D ), an etchant used during removal of the substrate 101 may be prevented from reaching the first source / drain pattern 150A and the second source / drain pattern 150B by the sidewall insulating film 170.

[0116] Afterwards, refer to Fig.11E , an insulating base layer 210 is formed. The insulating base layer 210 may have an insulating pattern 210P defined by a space located in the fin type active pattern 105. The insulating pattern 210P may have a structure extending in a first direction (eg, X direction) (eg, referring to Figure 1 In some example embodiments, the insulating base layer 210 may include an insulating material different from that of the vertical insulating patterns IP.

[0117] Subsequently, an opening connected to the vertical insulating pattern IP located below the first source / drain pattern 150A is formed in the insulating base layer 210, and the vertical insulating pattern IP is removed through the opening. Thereafter, a first contact structure 250 may be formed in the opening and in the space from which the vertical insulating pattern IP is removed. The vertical insulating pattern IP located in the lower region of the second source / drain pattern 150B may remain buried in the insulating base layer 210.

[0118] According to some of the above-mentioned example embodiments, by introducing a sidewall insulating film in the lower region of the multi-channel structure, damage to the contact alignment portion when removing the dummy gate structure and / or loss of the source / drain pattern when removing the substrate can be effectively prevented (or reduced).

[0119] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: an insulating base layer having an insulating pattern extending in a first direction; a plurality of semiconductor patterns stacked on the insulating pattern and spaced apart from each other in a direction perpendicular to an upper surface of the insulating base layer; a gate structure extending in a second direction intersecting the first direction and surrounding the plurality of semiconductor patterns; a first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being located on the insulating pattern and respectively connected to both side surfaces of the plurality of semiconductor patterns in the first direction; an interlayer insulating layer, the interlayer insulating layer covering the first source / drain pattern and the second source / drain pattern; a first contact structure connected to the first source / drain pattern through the insulating base layer; as well as A first sidewall insulating film is located between an upper portion of the first contact structure and an upper portion of the insulating pattern and extends to cover a side surface of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns.

2. The semiconductor device according to claim 1, wherein An upper end portion of the first sidewall insulating film is lower than a lower surface of the lowermost semiconductor pattern.

3. The semiconductor device according to claim 2, wherein: A height of an upper surface of the first contact structure is higher than a height of the upper end portion of the first sidewall insulating film.

4. The semiconductor device according to claim 3, wherein: A portion of the first contact structure adjacent to the upper end portion of the first sidewall insulating film is lower than the upper end portion of the first sidewall insulating film.

5. The semiconductor device according to claim 3, wherein: The upper surface of the first contact structure is higher than an upper surface of the lowermost semiconductor pattern or overlaps with the lowermost semiconductor pattern in a horizontal direction.

6. The semiconductor device according to claim 1, wherein A width of an upper portion of the insulating pattern covered by the first sidewall insulating film is in a range of 0.5 nm to 10 nm.

7. The semiconductor device according to claim 1, wherein A width of a portion of the gate structure covered by the first sidewall insulating film is in a range of 0.5 nm to 5 nm.

8. The semiconductor device according to claim 1, wherein The thickness of the first sidewall insulating film is in the range of 0.5 nm to 3 nm.

9. The semiconductor device according to claim 1, wherein: The width of the first contact structure in the second direction corresponds to the width of the insulation pattern in the second direction.

10. The semiconductor device according to claim 1, further comprising: a device isolation layer, the device isolation layer being located on the insulating base layer and defining the insulating pattern, In the cross section along the second direction, a side surface of the first contact structure contacts the device isolation layer, and the first sidewall insulating film has a portion located between an upper portion of the device isolation layer and the first contact structure.

11. The semiconductor device according to claim 1, further comprising: a vertical insulating pattern connected to a lower surface of the second source / drain pattern and arranged in the insulating base layer; as well as A second sidewall insulating film is located on a sidewall of an upper portion of the vertical insulating pattern and is disposed at the same height as that of the first sidewall insulating film.

12. The semiconductor device according to claim 11, further comprising: A second contact structure is provided, wherein the second contact structure is connected to the second source / drain pattern through the interlayer insulating layer.

13. The semiconductor device according to claim 11, wherein The vertical insulating pattern includes the same material as that of the insulating base layer.

14. The semiconductor device according to claim 11, wherein The vertical insulating pattern includes a material different from that of the insulating base layer, and the vertical insulating pattern is embedded in the insulating base layer.

15. A semiconductor device, comprising: Insulating base layer; a plurality of semiconductor patterns stacked on the protruding portion of the insulating base layer and spaced apart from each other in a vertical direction; a first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being connected to both side surfaces of the plurality of semiconductor patterns in a first direction, respectively; a gate structure extending in a second direction intersecting the first direction and surrounding the plurality of semiconductor patterns; an interlayer insulating layer, the interlayer insulating layer covering the first source / drain pattern and the second source / drain pattern; a first contact structure connected to the first source / drain pattern through the insulating base layer; a second contact structure connected to the second source / drain pattern through the interlayer insulating layer; a first sidewall insulating film surrounding an upper portion of the first contact structure and extending from a side surface of the protruding portion of the insulating base layer, wherein an upper end portion of the first sidewall insulating film has a height lower than a height of a lower surface of a lowermost semiconductor pattern among the plurality of semiconductor patterns; a vertical insulating pattern connected to a lower surface of the second source / drain pattern and arranged in the insulating base layer; as well as A second sidewall insulating film surrounds an upper portion of the vertical insulating pattern and is disposed at the same height as that of the first sidewall insulating film.

16. The semiconductor device according to claim 15, wherein: An upper surface of the first contact structure is higher than an upper surface of the vertical insulation pattern.

17. The semiconductor device according to claim 15, wherein: A height of an upper surface of the vertical insulating pattern is higher than a height of an upper end portion of the second sidewall insulating film.

18. The semiconductor device according to claim 17, wherein: An edge region of the upper surface of the vertical insulation pattern has a portion lower than the upper end portion of the second sidewall insulation film.

19. The semiconductor device according to claim 15, wherein: A height of an upper surface of the vertical insulating pattern is lower than a height of an upper end portion of the second sidewall insulating film.

20. A semiconductor device, comprising: Insulating base layer; a plurality of semiconductor patterns stacked on the insulating base layer and spaced apart from each other; a gate structure, the gate structure surrounding the plurality of semiconductor patterns; a first source / drain pattern and a second source / drain pattern, the first source / drain pattern and the second source / drain pattern being located on the insulating base layer and respectively connected to two side surfaces of the plurality of semiconductor patterns; a contact structure connected to the first source / drain pattern through the insulating base layer; a sidewall insulating film located between an upper portion of the contact structure and an upper portion of the insulating base layer and extending onto a region of a portion of the gate structure located below a lowermost semiconductor pattern among the plurality of semiconductor patterns; as well as A power transmission line is located on the lower surface of the insulating base layer and is connected to the contact structure.

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